CN116092949B - Method for manufacturing interposer, interposer and chip package - Google Patents
Method for manufacturing interposer, interposer and chip package Download PDFInfo
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- CN116092949B CN116092949B CN202310369317.1A CN202310369317A CN116092949B CN 116092949 B CN116092949 B CN 116092949B CN 202310369317 A CN202310369317 A CN 202310369317A CN 116092949 B CN116092949 B CN 116092949B
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- interposer
- carrier plate
- dielectric layer
- metal film
- current
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000003292 glue Substances 0.000 claims abstract description 16
- 230000001070 adhesive effect Effects 0.000 claims abstract description 11
- 239000000853 adhesive Substances 0.000 claims abstract description 10
- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000007723 die pressing method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The embodiment of the invention provides a method for manufacturing an interposer, the interposer and a chip package, wherein the method comprises the following steps: s1, providing a carrier plate, wherein the carrier plate comprises a first part and a second part, the first part is an outer edge of one side of the carrier plate, and the second part is a plane of the side defined by the outer edge; s2, adding stripping glue to the first part, adding a metal film to the second part, and curing the stripping glue; s3, adding a dielectric layer on the surface of the metal film; s4, preparing a redistribution wire layer on the dielectric layer; s5, removing the current first part, wherein the current first part at least comprises stripping adhesive attached on the first part; and S6, peeling off the current second part, and cutting to form the intermediate layer. The method can rapidly peel the carrier plate without high temperature or laser to obtain the organic medium layer with the thickness less than 30 micrometers.
Description
Technical Field
The present invention relates to the field of chip fabrication, and in particular, to a method for fabricating an interposer, and a chip package.
Background
In the field of chip manufacturing, a carrier is required for multi-chip packaging and fan-out, and specifically, the method comprises the steps of connecting a plurality of chips or intermediaries by using a wafer process or a panel-level process, fixing the chips or intermediaries on the carrier by using organic glue, and separating the carrier by using high temperature or laser to break the adhesive property of the organic glue so as to obtain the required chips or intermediaries. The method is performed at high temperature, and the structure of the redistribution layer (RDL) and the dielectric layer is changed under the high temperature condition, so that the performance of the chip is affected. In the case of thinner interposers, the interposers may be damaged and delaminated or broken, failing to be successfully peeled from the carrier.
Disclosure of Invention
The invention provides a method for manufacturing an interposer, the interposer and a chip package.
To achieve the above object, an embodiment of the present invention provides a method for fabricating an interposer, the method including the steps of: s1, providing a carrier plate, wherein the carrier plate comprises a first part and a second part, the first part is an outer edge of one side of the carrier plate, and the second part is a side plane defined by the outer edge; s2, adding stripping glue to the first part, adding a metal film to the second part, and curing the stripping glue; s3, adding a dielectric layer on the surface of the metal film; s4, preparing a redistribution wire layer on the dielectric layer; s5, removing the current first part, wherein the current first part at least comprises stripping adhesive attached on the first part; and S6, peeling off the current second part, and cutting to form the intermediate layer.
Optionally, for step S1, a carrier plate prepared by at least one of silicon, glass, metal and organic plastic is provided.
Optionally, for step S2, the metal film is added by vacuum lamination.
Optionally, for step S2, a release glue is added by spraying a resin or sticking a dry film.
Optionally, for step S3, the dielectric layer is added by vacuum roll lamination or spin coating.
Optionally, for step S3, the dielectric layer is prepared by coating at least one of polyimide, benzocyclobutene, and a resin material.
Optionally, the width of the first portion ranges from 2 to 10 millimeters.
In another aspect, the present invention provides an interposer manufactured according to the above method for manufacturing an interposer.
In another aspect, the present invention further provides a chip package, where the chip package includes a substrate, at least one chip, and the interposer described above.
The invention provides a method capable of rapidly stripping a carrier plate, which does not damage the structures of a redistribution layer (RDL) and a dielectric layer, so that the performance of a chip is more stable.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a flow chart of a method of fabricating an interposer according to the present invention;
FIG. 2 is a schematic illustration of edge coating of a carrier plate according to the present invention;
FIG. 3 is a schematic view of a vacuum die of the present invention;
FIG. 4 is a schematic illustration of the present invention for preparing a redistribution conductor layer;
FIG. 5 is a schematic illustration of the present invention with a first portion removed;
fig. 6 is a schematic view of the invention with carrier removed.
Description of the reference numerals
101-a carrier plate;
102-stripping adhesive;
103-a metal film;
104-a dielectric layer;
105-the portion to be removed.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Fig. 1 is a flow chart of a method for fabricating an interposer according to the present invention, and as shown in fig. 1, the method for fabricating an interposer according to the present invention includes the following steps:
s1: a carrier plate 101 is provided, wherein the carrier plate 101 comprises a first part and a second part, the first part is an outer edge of one side of the carrier plate 101, and the second part is the side plane defined by the outer edge. According to a specific embodiment, when the shape of the carrier 101 is selected to be circular, the first portion is an outer edge of one side of the carrier 101, that is, a ring of the outer edge of the carrier 101, and the width of the first portion ranges from 2 mm to 10mm, that is, the width of the ring ranges from 2 mm to 10 mm. For step S1, the providing the carrier plate 101 includes: a carrier plate is provided that is made from at least one of silicon, glass, metal, and an organic plastic.
S2: to the first part a release glue 102 is added. Fig. 2 is a schematic diagram of edge gluing of the carrier plate 101 according to the present invention, the glue can be uniformly coated by using a high-precision dispensing method, or the pre-cut film glue is used for alignment and adhesion, fig. 2 is the carrier plate 101 (the upper diagram is a top view, the lower diagram is a side view) under different observation angles, the outer edge of one side of the carrier plate 101 is coated with the release glue 102, and the width of the release glue 102 ranges from 2 mm to 10 mm.
The step S2 further includes: a metal film 103 is added to the second portion, and the release adhesive 102 is cured. Fig. 3 is a schematic view of the vacuum die of the present invention, and as shown in fig. 3, the metal film 103 is added by vacuum die pressing for step S2. The curing comprises the following steps: spraying resin or pasting dry film. The metal film is preferably copper and aluminum, and the dry film is an organic film such as polyimide film, resin film. An organic film may be added to the second portion, or a multi-structure film may be added to the second portion, wherein the metal film 103 is provided inside the multi-structure film and the organic film is provided outside the multi-structure film. In the implementation process, the metal film 103 can be added first and then coated, and the process can achieve the same technical effect as long as the first part of the edge of the metal film 103 is reserved, and the metal film 103 is sealed on the carrier plate. As shown in FIG. 3, the carrier plate structure formed by the invention only has the stripping adhesive in the first partial area with the edge smaller than 10mm, and the second partial area has no adhesive, so that the flatness of the second part can be ensured, and no deformation caused by the curing of the adhesive can be generated.
S3: a dielectric layer 104 is added to the surface of the metal film 103. For step S4, the dielectric layer 104 is added by vacuum roll lamination or spin coating. The dielectric layer 104 may be at least one of polyimide, benzocyclobutene, and a resin material. The dielectric layer is provided with a circuit pattern. The circuit pattern is provided in the second portion, and a circuit design with higher accuracy than the existing technology can be made due to the excellent flatness of this portion.
S4: a redistribution layer (RDL) is fabricated on the dielectric layer 104. FIG. 4 is a schematic diagram of the redistribution layer according to the present invention, wherein a multi-layer RDL is fabricated by photolithography and electroplating processes, and an interposer structure is formed as shown in FIG. 4, and the interposer is formed with connection points capable of being connected to the outside, the connection points being used for connecting a chip or a substrate. The specific design of the preparation redistribution conductor layer is determined according to the function of an intermediate layer, and the intermediate layer can be a bridge connected left and right of a chip or a conductor redistribution or vertical signal transmission channel for conducting up and down of the chip.
S5: the current first portion is removed, the current first portion including at least the release adhesive 102 attached thereto. As shown in fig. 5, the current first portion is a portion to be removed 105. The removing the current first portion may include removing the release adhesive 102, or cutting the current first portion.
S6: and peeling off the current second part, and cutting to form the intermediate layer. The peeling does not need any external force, after the first part is removed, the interface between the metal of the second part and the carrier plate can be automatically separated, as shown in fig. 6, the second part is a part of carrier plate at present, part of carrier plate is peeled off, then the metal film layer on the back of the rest part is etched and removed, and the final intermediate layer is obtained, and the intermediate layer can be used after being cut.
The application also provides an interposer manufactured according to the method for manufacturing the interposer.
The application also provides a chip package, which comprises a substrate, at least one chip and the intermediate layer, wherein the intermediate layer and the chip are arranged on the substrate.
The invention provides a method for rapidly peeling a carrier plate 101, which does not damage the structures of a redistribution layer (RDL) and a dielectric layer 104, wherein after a first part is removed, a second part is not provided with peeling glue, a second part metal film is not bonded with the carrier plate through chemical bonds, the carrier plate can be automatically separated, an intermediate layer generated on the surface can not receive external stress in separation, and the intermediate layer can be transferred to a cutting film for cutting and then is attached to a used interface by using a flip-chip technology. Since this technique does not introduce external stresses during production, an interposer below 30 microns can be fabricated without fracture or delamination.
The foregoing details of the optional implementation of the embodiment of the present invention have been described in detail with reference to the accompanying drawings, but the embodiment of the present invention is not limited to the specific details of the foregoing implementation, and various simple modifications may be made to the technical solution of the embodiment of the present invention within the scope of the technical concept of the embodiment of the present invention, and these simple modifications all fall within the protection scope of the embodiment of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, various possible combinations of embodiments of the present invention are not described in detail.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (9)
1. A method of fabricating an interposer, the method comprising:
s1: providing a carrier plate, wherein the carrier plate comprises a first part and a second part, the first part is an outer edge of one side of the carrier plate, and the second part is a plane of the side defined by the outer edge;
s2: adding stripping glue to the first part, adding a metal film to the second part, and curing the stripping glue;
s3: adding a dielectric layer on the surface of the metal film;
s4: preparing a redistribution conductor layer on the dielectric layer;
s5: removing the current first portion, the current first portion including at least a release adhesive attached thereto; and
s6: and peeling off the current second part, and cutting to form the intermediate layer.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
for step S1, a carrier plate prepared by at least one of silicon, glass, metal and organic plastic is provided.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
for step S2, the metal film is added by vacuum lamination.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
for step S2, a release glue is added by spraying a resin or sticking a dry film.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
for step S3, the dielectric layer is added by vacuum roller lamination or spin-coating.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
for step S3, the dielectric layer is prepared by coating at least one of polyimide, benzocyclobutene, and a resin material.
7. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the width of the first portion ranges from 2 to 10 millimeters.
8. An interposer, characterized in that it is manufactured according to the method of manufacturing an interposer according to any one of claims 1-7.
9. A chip package comprising a substrate, at least one chip, and the interposer of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310369317.1A CN116092949B (en) | 2023-04-10 | 2023-04-10 | Method for manufacturing interposer, interposer and chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310369317.1A CN116092949B (en) | 2023-04-10 | 2023-04-10 | Method for manufacturing interposer, interposer and chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116092949A CN116092949A (en) | 2023-05-09 |
| CN116092949B true CN116092949B (en) | 2023-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310369317.1A Active CN116092949B (en) | 2023-04-10 | 2023-04-10 | Method for manufacturing interposer, interposer and chip package |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005197582A (en) * | 2004-01-09 | 2005-07-21 | North:Kk | Manufacturing method for connecting element between wiring films, and manufacturing device thereof |
| JP2010199616A (en) * | 2010-05-12 | 2010-09-09 | Shinko Electric Ind Co Ltd | Method of manufacturing wiring board |
| WO2020122014A1 (en) * | 2018-12-10 | 2020-06-18 | 凸版印刷株式会社 | Wiring board for semiconductor device, method of manufacturing same, and semiconductor device |
| CN115332088A (en) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | Package based on interposer and manufacturing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5904556B2 (en) * | 2010-03-03 | 2016-04-13 | ジョージア テック リサーチ コーポレイション | Through-package via (TPV) structure on inorganic interposer and manufacturing method thereof |
| IL223414A (en) * | 2012-12-04 | 2017-07-31 | Elta Systems Ltd | Integrated electronic device and a method for fabricating the same |
| US9455160B2 (en) * | 2013-01-14 | 2016-09-27 | Infineon Technologies Ag | Method for fabricating a semiconductor chip panel |
| US20210202338A1 (en) * | 2019-12-31 | 2021-07-01 | Sj Semiconductor (Jiangyin) Corporation | Wafer-level sip module structure and method for preparing the same |
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- 2023-04-10 CN CN202310369317.1A patent/CN116092949B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005197582A (en) * | 2004-01-09 | 2005-07-21 | North:Kk | Manufacturing method for connecting element between wiring films, and manufacturing device thereof |
| JP2010199616A (en) * | 2010-05-12 | 2010-09-09 | Shinko Electric Ind Co Ltd | Method of manufacturing wiring board |
| WO2020122014A1 (en) * | 2018-12-10 | 2020-06-18 | 凸版印刷株式会社 | Wiring board for semiconductor device, method of manufacturing same, and semiconductor device |
| CN115332088A (en) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | Package based on interposer and manufacturing method |
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| CN116092949A (en) | 2023-05-09 |
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