CN113471160A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN113471160A CN113471160A CN202110729589.9A CN202110729589A CN113471160A CN 113471160 A CN113471160 A CN 113471160A CN 202110729589 A CN202110729589 A CN 202110729589A CN 113471160 A CN113471160 A CN 113471160A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
Abstract
The invention provides a chip packaging structure and a manufacturing method thereof, wherein the chip packaging structure comprises a plastic packaging layer, a bare chip and an external electric connection structure; the plastic packaging layer is internally provided with a groove; the bare chip is arranged in the groove; an opening of the die having an active side facing the recess; a filling layer is arranged between the bare chip and the side wall of the groove, and the thermal expansion coefficient of the filling layer is between that of the bare chip and that of the plastic packaging layer; the external electric connection structure is located on the active surface of the bare chip and the plastic package layer outside the groove, and the external electric connection structure is electrically connected with the bonding pad located on the active surface of the bare chip. According to the embodiment of the invention, the precise positioning and the pasting can be carried out through the metal pattern of the active surface of the bare chip. In addition, during thermal expansion, the filling layer limits the displacement of the bare chip, and the subsequently manufactured electric connection structure, such as the metal pattern block of the redistribution layer, can be accurately aligned with the bonding pad on the bare chip, so that the electric connection performance is reliable, and the miniaturization is facilitated to improve the integration level.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a manufacturing method thereof.
Background
In recent years, in the packaging process, in order to improve the packaging efficiency, a panel level packaging technology is developed in the industry.
In the panel level packaging technology, the process of transferring each bare chip to the carrier plate is as follows: and adsorbing the back surfaces of the bare chips by using a suction head, enabling the active surface of each bare chip to face the carrier plate, and then placing the bare chips to the calculated positions. And then packaging by adopting a plastic packaging material.
After the actual process of plastic package material packaging is finished, it is found that a large size deviation occurs at the position of the bare chip, which causes reliability problems such as short circuit and open circuit of the electrical connection between the redistribution layer and the bonding pad on the bare chip in the subsequent manufacturing.
In order to avoid the above problems, in the related art, the sizes of the metal pattern blocks and the pads of the redistribution layer need to be large, which is not favorable for improving the integration level.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a manufacturing method thereof, which can relieve the offset of a bare chip in the plastic packaging process, thereby improving the product integration level.
In order to achieve the above object, an aspect of the present invention provides a chip package structure, including:
the plastic packaging layer is provided with a groove;
a die disposed within the recess; an active face of the die facing an opening of the recess; a filling layer is arranged between the die and the side wall of the groove, and the thermal expansion coefficient of the filling layer is between that of the die and that of the molding layer;
and the external electric connection structure is positioned on the active surface of the bare chip and the plastic packaging layer outside the groove, and the external electric connection structure is electrically connected with the bonding pad positioned on the active surface of the bare chip.
Optionally, the filling layer is further located on the active surface of the die and the molding layer outside the groove, and the external electrical connection structure is located on the filling layer.
Optionally, the chip package structure further includes: a redistribution layer on the active side of the die and the molding layer outside the groove, the redistribution layer for implementing a circuit layout of the pad; the external electrical connection structure is located on the redistribution layer.
Optionally, the grooves have two or more grooves, and each groove is provided with one die; the redistribution layer electrically connects at least two of the dies.
Optionally, a plastic package film is arranged between the back surface of the bare chip and the bottom wall of the groove, and the thermal expansion coefficient of the plastic package film is between that of the bare chip and that of the plastic package layer.
Another aspect of the present invention provides a method for manufacturing a chip package structure, including:
providing a plastic packaging layer, and forming at least one groove in the plastic packaging layer;
the back side of the die faces the grooves, and one die is placed in one groove;
forming a filling layer at least between each die and the side wall of each groove, wherein the thermal expansion coefficient of the filling layer is between that of the die and that of the plastic packaging layer;
forming at least an external electrical connection structure on the active surface of each die and the plastic package layer outside the groove, wherein the external electrical connection structure is electrically connected with a bonding pad on the active surface of the die;
and cutting to form a plurality of chip packaging structures.
Optionally, the filling layer is further formed on the active surface of the die and the molding layer outside the groove, and the external electrical connection structure is formed on the filling layer.
Optionally, before the step of forming the external electrical connection structure, a redistribution layer is formed on the active surface of the die and the molding layer outside the groove, and the redistribution layer is used for realizing the circuit layout of the pad; the external electrical connection structure is formed on the redistribution layer.
Optionally, the number of the grooves is two or more, and the redistribution layer electrically connects at least two of the dies.
Optionally, the back side of the die has a molding film having a coefficient of thermal expansion between that of the die and that of the molding layer.
The inventor analyzes that the reason for the large size deviation of the bare chip position in the plastic packaging process is that: firstly, in the process of transferring the bare chips to the carrier plate, the active surface of each bare chip faces the carrier plate, and the bare chips can be pasted only by estimating the central points of the bare chips, so that deviation exists; secondly, the die can be shifted by releasing the stress of the molding compound at high temperature.
Based on the analysis, the plastic package layer is provided with the groove, the back surface of the bare chip faces the groove, and the bare chip is placed in the groove; and then forming a filling layer at least between the bare chip and the side wall of the groove, wherein the thermal expansion coefficient of the filling layer is between that of the bare chip and that of the plastic packaging layer.
Compared with the prior art, the invention has the beneficial effects that: when the bare chip is placed in the groove, the active surface of the bare chip faces the opening of the groove, so that accurate alignment and pasting can be carried out through the metal pattern of the active surface of the bare chip. In addition, during thermal expansion, the filling layer limits the displacement of the bare chip, and the subsequently manufactured electric connection structure, such as the metal pattern block of the redistribution layer, can be accurately aligned with the bonding pad on the bare chip, so that the electric connection performance is reliable, and the miniaturization is facilitated to improve the integration level.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a chip package structure according to a first embodiment of the invention;
FIG. 2 is a flow chart of a method of fabricating the chip package structure of FIG. 1;
FIGS. 3-7 are schematic intermediate structures corresponding to the flow chart of FIG. 2;
fig. 8 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the invention;
fig. 9 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the invention;
fig. 10 is a schematic cross-sectional view of a chip package structure according to a fourth embodiment of the invention.
To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:
plastic-sealed layer 11 groove 111
Die 12 die active surface 12a
Die backside 12b fill layer 13
First dielectric layer 15 of external electrical connection structure 14
Second dielectric layer 18
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic cross-sectional structure diagram of a chip package structure according to a first embodiment of the invention.
Referring to fig. 1, a chip package structure 1 includes:
the plastic packaging layer 11 is provided with a groove 111;
a bare chip 12 disposed in the groove 111; the active face 12a of the die 12 faces the opening of the recess 111; a filling layer 13 is arranged between the bare chip 12 and the side wall of the groove 111, and the thermal expansion coefficient of the filling layer 13 is between that of the bare chip 12 and that of the molding layer 11;
the external electrical connection structure 14 is located on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111, and the external electrical connection structure 14 is electrically connected to the pad 121 located on the active surface 12a of the die.
The material of the molding layer 11 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 11 can also be various polymers or a composite material of resin and polymer.
In this embodiment, the number of the grooves 111 is one.
The DIE 12 may be a POWER DIE (POWER DIE), a MEMORY DIE (MEMORY DIE), a sensing DIE (SENSOR DIE), a RADIO frequency DIE (RADIO frequency DIE), or the like.
Referring to fig. 1, the die 12 includes opposing active and back surfaces 12a and 12 b. The pad 121 is exposed to the active surface 12 a. The die 12 may include a variety of devices formed on a semiconductor substrate, as well as electrical interconnect structures electrically connecting the various devices. The pads 121 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
In the present invention, "/" denotes "or".
In this embodiment, the thermal expansion coefficient of the filling layer 13 is between the thermal expansion coefficient of the die 12 and the thermal expansion coefficient of the molding layer 11, which means that: the coefficient of thermal expansion of the die 12 < the coefficient of thermal expansion of the filler layer 13 < the coefficient of thermal expansion of the molding layer 11. The material of the filling layer 13 may be: certain components of epoxy resins or mixtures comprising these modified epoxy resins are added. The thermal expansion coefficients of these components are less than that of epoxy.
In this embodiment, the active surface 12a of the die 12 and the molding layer 11 outside the groove 111 have a first dielectric layer 15 thereon. The first dielectric layer 15 has a conductive bump 141 thereon. The conductive bump 141 is connected to the pad 121 by a conductive plug located within the first dielectric layer 15.
The conductive bump 141 is coated with an anti-oxidation layer 142.
The oxidation resistant layer 142 may include: a1) a tin layer, or a2) a nickel layer and a gold layer stacked from bottom to top, or a3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The oxidation resistant layer 142 may be formed using an electroplating process. The conductive bump 141 may be made of copper, and the anti-oxidation layer 142 may prevent oxidation of copper, thereby preventing deterioration of electrical connection performance due to oxidation of copper.
The conductive bump 141 and the covering anti-oxidation layer 142 form an external electrical connection structure 14.
An embodiment of the present invention further provides a method for manufacturing the chip package structure in fig. 1, and fig. 2 is a corresponding flowchart; fig. 3 to 7 are intermediate schematic diagrams corresponding to the flow chart in fig. 2.
First, referring to step S1 in fig. 2 and fig. 3, a molding layer 11 is provided, and a plurality of grooves 111 are formed in the molding layer 11.
The material of the molding layer 11 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 11 can also be various polymers or a composite material of resin and polymer.
The molding layer 11 may be placed on the carrier plate 20.
The carrier plate 20 is a rigid plate and may comprise a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
The carrying surface of the carrier 20 may be provided with an adhesive layer. The adhesive layer may be made of a material that is easily peeled off to peel off the carrier 20. For example, a thermal release material capable of being made tack-free by heating or a UV release material capable of being made tack-free by ultraviolet irradiation may be used.
The groove 111 may be formed by dry etching, wet etching, or a laser grooving method.
In this embodiment, the number of the grooves 111 is multiple, so that a plurality of chip package structures can be manufactured at the same time, and the manufacturing efficiency can be improved. In other embodiments, there may be one groove 111.
Next, referring to step S2 in fig. 2 and fig. 4, the back surface 12b of the die 12 faces the grooves 111, and one die 12 is placed in one of the grooves 111.
The die 12 is formed as a singulated wafer. The wafer includes a wafer active side and a wafer backside, the wafer active side exposing the bonding pads 121. After the wafer dicing, a die 12 is formed, and accordingly, the die 12 includes an active surface 12a and a back surface 12b, and the bonding pad 121 is exposed to the active surface 12a of the die.
The process transfer of the die 12 includes: adsorbing the active surface 12a of the bare chip 12 by using a suction head, and moving the bare chip 12 to the upper part of the groove 111; the back side 12b of the die 12 is placed to the bottom wall of the recess 111 by precise alignment of the metal pattern of the die active side 12 a.
Thereafter, referring to step S3 in fig. 2 and fig. 5, a filling layer 13 is formed between each die 12 and the sidewall of each groove 111, and the thermal expansion coefficient of the filling layer 13 is between the thermal expansion coefficient of the die 12 and the thermal expansion coefficient of the molding layer 11.
The filling layer 13 may be formed by filling an organic material having good fluidity into each of the grooves 111 and then curing the organic material to form an organic film.
Next, referring to step S4 in fig. 2 and fig. 6, an external electrical connection structure 14 is formed on the active surface 12a of each die 12 and the molding layer 11 outside the groove 111, and the external electrical connection structure 14 is electrically connected to the pad 121 on the active surface 12a of the die.
Step S4 may specifically include steps S41 to S43.
Step S41: a first dielectric layer 15 is formed on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111.
The first dielectric layer 15 is an insulating material, and may be an organic polymer insulating material or an inorganic insulating material. The organic polymer insulating material is, for example, polyimide, epoxy resin, abf (ajinomoto build film), pbo (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other organic materials having similar insulating properties.
The organic polymer insulating material may be a) laminated on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111 by a lamination process, or b) coated on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111 and then cured, or c) cured on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111 by an injection molding process.
When the material of the first dielectric layer 15 is an inorganic insulating material such as silicon dioxide or silicon nitride, it can be formed on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111 by a deposition process.
Compared with inorganic insulating materials, the organic polymer insulating materials have smaller tensile stress, and can prevent the plastic package body from warping caused by the large-area formation of the first dielectric layer 15.
The first dielectric layer 15 may include one or more layers.
Step S42: an opening is formed in the first dielectric layer 15 exposing a partial region of the pad 121.
The opening may be formed by dry etching, wet etching, or laser drilling.
Step S43: a conductive bump 141 is formed on the first dielectric layer 15.
The conductive bump 141 may be formed by depositing a metal material layer and then patterning the metal material layer; or may be formed by electroplating.
If the metal material layer is deposited by deposition, the metal material layer is simultaneously deposited in the opening. If by electroplating, metal is simultaneously electroplated within the openings.
In addition, an oxidation-resistant layer 142 may be further plated outside the conductive bump 141. The conductive bump 141 and the covering anti-oxidation layer 142 form an external electrical connection structure 14.
Next, referring to step S5 in fig. 2, fig. 7 and fig. 1, a plurality of chip package structures 1 are formed by dicing.
Fig. 8 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the invention. Referring to fig. 8, the chip package structure 2 of the present embodiment is substantially the same as the chip package structure 1 of the first embodiment, and the differences are only: the filling layer 13 is also located on the active surface 12a of the die 12 and the molding layer 11 outside the groove 111, and the external electrical connection structure 14 is located on the filling layer 13.
Correspondingly, for the manufacturing method, in step S3, the liquid organic material may cover the active surface 12a of the die 12 and the molding layer 11 outside the groove 111. This embodiment reduces the amount of liquid organic material required relative to an implementation.
In this embodiment, the first dielectric layer 15 may be omitted.
Fig. 9 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the invention. Referring to fig. 9, the chip package 3 of the present embodiment is substantially the same as the chip packages 1 and 2 of the first and second embodiments, and the differences are only: a plastic film 16 is arranged between the back surface 12b of the bare chip 12 and the bottom wall of the groove 111, and the thermal expansion coefficient of the plastic film 16 is between that of the bare chip 12 and that of the plastic layer 11.
In this embodiment, the thermal expansion coefficient of the plastic film 16 is between the thermal expansion coefficient of the die 12 and the thermal expansion coefficient of the plastic layer 11: the coefficient of thermal expansion of the die 12 < the coefficient of thermal expansion of the molding film 16 < the coefficient of thermal expansion of the molding layer 11.
The plastic film 16 can buffer the problem of stress mismatch caused by thermal expansion of the film layers of the chip package structure 3 in the vertical direction.
The material of the plastic film 16 may refer to the material of the filling layer 13. In addition, the molding film 16 may be a high melting point organic film with a certain viscosity to prevent the flow during the high temperature process, thereby preventing the die 12 from being displaced. The patterned metal material layer may be used to form the conductive bump 141, or the conductive bump 141 may be formed by electroplating, and the patterned photoresist may be used as a mask layer, and the high temperature process may be a photoresist baking process.
Correspondingly, in the manufacturing method, in step S2, the plastic film 16 may be disposed on the back surface of the wafer, and after the wafer is diced, the back surface 12b of each die 12 also has the plastic film 16.
Fig. 10 is a schematic cross-sectional view of a chip package structure according to a fourth embodiment of the invention. Referring to fig. 10, the chip package structure 4 of the present embodiment is substantially the same as the chip package structures 1, 2, and 3 of the first, second, and third embodiments, and the differences are only: the number of the grooves 111 is two, and each groove 111 is provided with one bare chip 12; the chip package structure 4 further includes: a redistribution layer 17 located on the active surfaces 12a of the two dies 12 and the plastic encapsulation layer 11 outside the groove 111, the redistribution layer 17 being used for realizing the electrical connection of the two dies 12; the external electrical connection structure 14 is located on the redistribution layer 17.
The second dielectric layer 18 may be disposed on the conductive bump 141 of the external electrical connection structure 14 and the redistribution layer 17, and the conductive bump 141 is exposed outside the second dielectric layer 18.
The redistribution layer 17 may include one or more metal pattern layers.
In other embodiments, the redistribution layer 17 may implement a circuit layout of the pads 121 on one die 12. The grooves 111 may also have more than two numbers.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A chip package structure, comprising:
the plastic packaging layer is provided with a groove;
a die disposed within the recess; an active face of the die facing an opening of the recess; a filling layer is arranged between the die and the side wall of the groove, and the thermal expansion coefficient of the filling layer is between that of the die and that of the molding layer;
and the external electric connection structure is positioned on the active surface of the bare chip and the plastic packaging layer outside the groove, and the external electric connection structure is electrically connected with the bonding pad positioned on the active surface of the bare chip.
2. The chip package structure according to claim 1, wherein the filling layer is further located on the active surface of the die and the molding layer outside the recess, and the external electrical connection structure is located on the filling layer.
3. The chip package structure according to claim 1, further comprising: a redistribution layer on the active side of the die and the molding layer outside the groove, the redistribution layer for implementing a circuit layout of the pad; the external electrical connection structure is located on the redistribution layer.
4. The chip package structure according to claim 3, wherein the recess has two or more, and one of the dies is disposed in each recess; the redistribution layer electrically connects at least two of the dies.
5. The chip package structure according to claim 1, wherein a molding film is provided between the back surface of the die and the bottom wall of the groove, and a thermal expansion coefficient of the molding film is between that of the die and that of the molding layer.
6. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a plastic packaging layer, and forming at least one groove in the plastic packaging layer;
the back side of the die faces the grooves, and one die is placed in one groove;
forming a filling layer at least between each die and the side wall of each groove, wherein the thermal expansion coefficient of the filling layer is between that of the die and that of the plastic packaging layer;
forming at least an external electrical connection structure on the active surface of each die and the plastic package layer outside the groove, wherein the external electrical connection structure is electrically connected with a bonding pad on the active surface of the die;
and cutting to form a plurality of chip packaging structures.
7. The method for manufacturing the chip package structure according to claim 6, wherein the filling layer is further formed on the active surface of the die and the molding layer outside the groove, and the external electrical connection structure is formed on the filling layer.
8. The method for manufacturing the chip package structure according to claim 6, wherein before the step of forming the external electrical connection structure, a redistribution layer is formed on the active surface of the die and the molding layer outside the groove, and the redistribution layer is used for realizing a circuit layout of the bonding pad; the external electrical connection structure is formed on the redistribution layer.
9. The method of claim 8, wherein the number of the grooves is two or more, and the redistribution layer electrically connects at least two of the dies.
10. The method for manufacturing the chip package structure according to claim 6, wherein the die has a molding film on a back surface thereof, and a thermal expansion coefficient of the molding film is between a thermal expansion coefficient of the die and a thermal expansion coefficient of the molding layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110729589.9A CN113471160A (en) | 2021-06-29 | 2021-06-29 | Chip packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110729589.9A CN113471160A (en) | 2021-06-29 | 2021-06-29 | Chip packaging structure and manufacturing method thereof |
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| CN113471160A true CN113471160A (en) | 2021-10-01 |
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| CN202110729589.9A Pending CN113471160A (en) | 2021-06-29 | 2021-06-29 | Chip packaging structure and manufacturing method thereof |
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