CN210006732U - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

Info

Publication number
CN210006732U
CN210006732U CN201921141727.6U CN201921141727U CN210006732U CN 210006732 U CN210006732 U CN 210006732U CN 201921141727 U CN201921141727 U CN 201921141727U CN 210006732 U CN210006732 U CN 210006732U
Authority
CN
China
Prior art keywords
layer
conductive
protective layer
chip package
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201921141727.6U
Other languages
Chinese (zh)
Inventor
周辉星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pep Innovation Pte Ltd
Original Assignee
Pep Innovation Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pep Innovation Pte Ltd filed Critical Pep Innovation Pte Ltd
Application granted granted Critical
Publication of CN210006732U publication Critical patent/CN210006732U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

The present disclosure provides chip package structures, which include at least bare chips having a bare chip active surface and a bare chip back surface, the bare chip active surface including an electrical connection point and an insulating layer, a protective layer having material characteristics and formed on the bare chip active surface and having a conductive filling through hole formed therein, at least part of the conductive filling through hole being electrically connected with at least part of the electrical connection point, a molding layer having material characteristics and used for encapsulating the bare chips, a conductive layer formed at least partially on the surface of the protective layer and having at least part of the conductive layer being electrically connected with at least part of the conductive filling through hole, and a dielectric layer formed on the conductive layer, wherein the chip package structure has series of material and structure characteristics, thereby reducing warpage during packaging, lowering bare chip accuracy requirements, reducing difficulty of panel packaging process, and enabling the packaged chip structure to have durable service cycle, and is particularly suitable for large-panel-level packaging and packaging of large-electric-flux and thin chips.

Description

Chip packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a chip package structure.
Background
Panel-level packaging (panel-level packaging), i.e., dicing a wafer to separate a plurality of dies, arranging and adhering the dies on a carrier, and packaging the dies simultaneously in the same process flow, has attracted attention as a technology emerging in recent years , and compared with the conventional wafer-level packaging (wafer-level packaging), the panel-level packaging has the advantages of high production efficiency, low production cost, and suitability for mass production.
However, panel packaging has a number of barriers in the art, such as warpage of the panel; die alignment accuracy on the panel, etc.
Particularly, in the trend of miniaturization and light weight of electronic devices, small and thin chips are increasingly favored by the market, but the difficulty of the packaging process for packaging the small and thin chips by using the large panel packaging technology is not small and non-trivial.
SUMMERY OF THE UTILITY MODEL
The disclosure provides chip packaging structures, which comprise at least bare chips, a protective layer formed on the active surface of the bare chips, conductive filling through holes formed in the protective layer, at least parts of the conductive filling through holes being electrically connected with at least parts of the electric connection points, a plastic packaging layer used for packaging the bare chips, a conductive layer at least partially formed on the surface of the protective layer and electrically connected with at least parts of the conductive filling through holes, and a dielectric layer formed on the conductive layer.
In embodiments, the Young's modulus of the protective layer is any of value ranges or values of 1000-20000MPa, 1000-10000MPa, 4000-8000MPa, 1000-7000 MPa, 4000-7000 MPa and 5500 MPa.
In embodiments, the material of the protective layer is an organic/inorganic composite material.
In another embodiments, the thickness of the passivation layer is any of value ranges or values of 15-50 μm, 20-50 μm, 35 μm, 45 μm, and 50 μm.
In still another embodiments, the protective layer has a thermal expansion coefficient of any of value ranges or values from 3 to 10ppm/K, 5ppm/K, 7ppm/K, 10 ppm/K.
In preferred embodiments, the plastic layer has a thermal expansion coefficient of any of value ranges or values from 3 to 10ppm/K, 5ppm/K, 7ppm/K, 10 ppm/K.
In another preferred embodiments, the protective layer and the molding layer have the same or similar coefficients of thermal expansion.
In yet another preferred embodiments, the protective layer includes inorganic filler particles having a diameter of less than 3 μm.
In advantageous embodiments, the inorganic filler particles have a diameter of 1-2 μm.
In advantageous embodiments, the conductively filled via is formed as a conductive dielectric filled protective layer opening, the conductively filled via having a conductively filled via lower surface and a conductively filled via upper surface, a ratio of an area of the conductively filled via lower surface to the conductively filled via upper surface being in a range of 60% to 90%.
In advantageous embodiments, the lower surface of the conductively filled via has a void between the insulating layer and the lower surface of the conductively filled via, and/or the lower surface of the conductively filled via is at a nearly central location of the electrical connection point.
In preferred embodiments, the resist opening is a laser patterned resist opening.
In another preferred embodiments, the conductive layer comprises conductive traces and/or conductive posts, wherein at least portion of the conductive traces closest to the active side of the die are formed on the surface of the protective layer and electrically connected to the conductive filled vias, and the conductive posts are formed on pads or connection points of the conductive traces.
In yet another preferred embodiments, the conductive layer is layers or multilayers.
In preferred embodiments, a conductive coating is formed over the electrical connection points.
In advantageous embodiments, the conductive coating has a thickness of 2-3 μm.
In advantageous embodiments, the conductive capping layer is a Cu layer.
In preferred embodiments, at least portions of the conductive traces closest to the active side of the die are formed on the molding compound front side and extend to the edge of the package body.
In preferred embodiments, the die backside is exposed from the molding layer.
In preferred embodiments, the surface of the dielectric layer has a recess at a location corresponding to the conductive layer.
In preferred embodiments, the at least dice are a plurality of dice with electrical connections between the dice according to a product design.
In preferred embodiments, the multiple dies are dies with different functions to form a multi-chip assembly.
Drawings
Fig. 1 to 12 are flowcharts of a proposed chip packaging method according to an exemplary embodiment of the present disclosure;
FIG. 1 is a schematic view of a semiconductor wafer according to an exemplary embodiment of the present disclosure;
FIG. 2 is a schematic illustration of a semiconductor wafer after a protective layer is applied in accordance with an exemplary embodiment of the present disclosure;
FIG. 3a is a schematic view of a semiconductor wafer with openings for a protective layer formed in accordance with an exemplary embodiment of the present disclosure;
FIG. 3b is a schematic view of a semiconductor wafer with conductively filled vias formed in accordance with an exemplary embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a semiconductor wafer diced to form dies with protective layers in accordance with an exemplary embodiment of the present disclosure;
fig. 5a is a schematic diagram of a die attached to a carrier board according to an exemplary embodiment of the present disclosure;
fig. 5b is a schematic diagram of a die assembly attached to a carrier board according to an exemplary embodiment of the disclosure;
fig. 6 is a schematic diagram of forming a molding layer on a carrier plate according to an exemplary embodiment of the present disclosure;
fig. 7a is a schematic illustration of thinning a thickness of a plastic encapsulant layer according to an exemplary embodiment of the present disclosure;
fig. 7b is a schematic illustration of thinning the molding layer to the backside of the bare die according to an exemplary embodiment of the present disclosure;
FIG. 8 is a schematic view of a peel-off carrier sheet and adhesive layer in accordance with an exemplary embodiment of the present disclosure;
FIG. 9 is a schematic diagram of the formation of a conductive filled via and conductive trace on a panel assembly according to an exemplary embodiment of the present disclosure;
fig. 10 is a schematic view of forming conductive posts on a panel assembly according to an exemplary embodiment of the present disclosure;
fig. 11a and 11b are schematic views of forming a dielectric layer on a panel assembly according to an exemplary embodiment of the present disclosure;
fig. 12 is a schematic diagram of a packaged chip formed from a cutting panel assembly according to an exemplary embodiment of the present disclosure;
fig. 13a is a schematic diagram of a chip package structure obtained by the above packaging method according to an exemplary embodiment of the disclosure;
fig. 13b is a schematic diagram of a chip package structure obtained by the above packaging method according to an exemplary embodiment of the disclosure;
fig. 13c is a schematic diagram of a chip assembly package structure obtained by the above-mentioned packaging method according to an exemplary embodiment of the present disclosure;
FIG. 14a is a schematic diagram of a packaged chip in use according to an exemplary embodiment of the present disclosure;
fig. 14b is a schematic view of a packaged chip assembly in use according to an exemplary embodiment of the present disclosure.
Detailed Description
To make the technical solutions of the present disclosure clearer and the technical effects thereof more obvious, the following detailed description and the description of the preferred embodiments of the present disclosure are given with reference to the accompanying drawings, which should not be construed as limiting the present disclosure to only implementation forms of the present disclosure.
Fig. 1 to 12 are flowcharts of a proposed chip packaging method according to an exemplary embodiment of the present disclosure.
As shown in fig. 1, at least wafers 100 are provided, the wafer 100 has a wafer active surface 1001 and a wafer back surface 1002, the wafer 100 includes a plurality of dies 113, wherein the active surface of each die constitutes the wafer active surface 1001, the active surface of each die in the wafer 100 forms series active components and passive components through series processes of doping, deposition, etching and the like, the active components include diodes, triodes and the like, the passive components include voltage transformers, capacitors, resistors, inductors and the like, and the active components and the passive components are connected by connecting wires to form functional circuits, so as to realize various functions of the chip, the wafer active surface 1001 further includes an electrical connection point 103 for leading out the functional circuits, and an insulating layer 105 for protecting the electrical connection point 103.
An electroless plating process step is preferably performed on the wafer active side 1001 to form a conductive cap layer on the electrical connection points 103. optionally, the conductive cap layer is layers or multiple layers of Cu, Ni, Pd, Au, Cr. preferably, the conductive protective layer is a Cu layer, the thickness of the conductive protective layer is preferably 2-3 μm. the conductive cap layer is not shown in fig. 1.
As shown in fig. 2, a protective layer 107 is applied to the active side 1001 of the wafer.
In embodiments, a protective layer is applied to the active side 1001 of the wafer by lamination.
Optionally, before the step of applying the protective layer 107 on the active side 1001 of the wafer, the active side 1001 of the wafer and/or the side of the wafer 100 to which the protective layer 107 is applied are physically and/or chemically treated to make the bond between the protective layer 107 and the wafer 100 tighter, optionally by plasma surface treatment to roughen the surface to increase the adhesion area and/or chemically promoted modifier treatment, introducing a promoted modifying group, such as a surface modifier with both affinity organic and affinity inorganic groups, between the wafer 100 and the protective layer 107 to increase the adhesion between the organic/inorganic interface layers.
The protective layer 107 may be used to protect the die active surface 1131. In the subsequent plastic packaging process, since the plastic packaging material flowing under heating easily penetrates into the gaps between the die 113 and the carrier plate 117 due to the plastic packaging pressure, and damages the circuit on the die active surface 1131, when the die active surface 1131 has the protection layer, the protection layer 107 can protect the die active surface 1131 from the plastic packaging material penetrating, so as to protect the die active surface 1131 from being damaged.
The protective layer 107 can also make the bonding effect between the bare chip 113 and the adhesive layer 121 stronger, so that the bare chip 113 is not easily displaced on the carrier plate 117 by the plastic package pressure during the plastic package process.
In preferred embodiments, the Young's modulus of the protective layer 107 is in the range of 1000 to 20000MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000 to 10000MPa, further step is preferably 1000 to 7000, 4000 to 7000 or 4000 to 8000MPa, and in a most preferred embodiment the Young's modulus of the protective layer 107 is 5500 MPa.
In preferred embodiments, the thickness of the protective layer 107 is in the range of 15-50 μm, more preferably in the range of 20-50 μm, in preferred embodiments the thickness of the protective layer 107 is 35 μm, in another preferred embodiments the thickness of the protective layer 107 is 45 μm, and in yet another preferred embodiments the thickness of the protective layer 107 is 50 μm.
When the Young's modulus of the protective layer 107 is in the range of 1000-.
Particularly, in kinds of chips, it is required to use a thin die for packaging, and it is also required that the conductive layer has a thickness value of to form a large electric flux, at this time, the thickness of the protection layer 107 is selected to be in the range of 15-50 μm, the young modulus of the protection layer 107 is in the range of 1000-10000mpa, the protection layer 107 is soft and flexible, and a buffer layer can be formed between the die 113 and the conductive layer, so that the conductive layer does not excessively press the die 113 during the use of the chip, and the die 113 is prevented from being broken by the pressure of the thick conductive layer, and at the same time, the protection layer 107 has sufficient material strength, and the protection layer 107 can provide sufficient support for the thick conductive layer.
When the young modulus of the protection layer 107 is 1000-;
the die transfer process is a process (interconnection process) of rearranging and bonding the cut and separated die 113 to the carrier plate 117, and the die transfer process requires a die transfer apparatus (binder machine) including a lift pin for lifting up the die 113 on the wafer 100, and a suction head (binder head) for sucking up the lifted die 113 and transferring and bonding the die 113 to the carrier plate 117.
In the process of jacking up the bare chip 113 by the ejector pin, the bare chip 113, especially the thin bare chip 113, is brittle and is easy to be broken by the jacking pressure of the ejector pin, and the protective layer 100 with material characteristics can protect the brittle bare chip 113 and can keep the integrity of the bare chip 113 even under the higher jacking pressure.
In preferred embodiments, the protective layer 107 is an organic/inorganic composite layer including filler particles the filler particles are inorganic oxide particles, the filler particles are SiO2In embodiments, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as SiO2Mixed TiO2And (3) granules. Preferably, the filler particles in the protective layer 107 are, for example, inorganic oxide particles, such as SiO2Particles, e.g. SiO2Mixed TiO2 preferred embodiments, the filler particles in the protective layer 107 are inorganic oxide particles, such as SiO2Particles, e.g. SiO2Mixed TiO2The filling amount of the particles is more than 50%.
The organic material has the advantage of easy operation and application, and when the to-be-packaged die 113 is made of an inorganic material, such as silicon, and the protective layer 107 is made of an organic material alone, the packaging process is difficult due to the difference between the material properties of the organic material and the inorganic material, which affects the packaging effect. By adopting the organic/inorganic composite material with inorganic particles added in the organic material, the material properties of the organic material can be modified, and the material has the characteristics of both the organic material and the inorganic material.
In preferred embodiments, the protective layer 107 has a coefficient of thermal expansion in the range of 3 to 10ppm/K when (T < Tg), in preferred embodiments the protective layer 107 has a coefficient of thermal expansion of 5ppm/K, in preferred embodiments the protective layer 107 has a coefficient of thermal expansion of 7ppm/K, and in preferred embodiments the protective layer 107 has a coefficient of thermal expansion of 10 ppm/K.
In the next plastic packaging process, the bare chip 113 applied with the protective layer 107 expands and contracts correspondingly in the heating and cooling processes in the plastic packaging process, when the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K, the expansion and contraction degree between the protective layer 107 and the bare chip 113 is kept relatively , the connecting interface between the protective layer 107 and the bare chip 113 is not easy to generate interface stress, the combination between the protective layer 107 and the bare chip 113 is not easy to break, and the packaged chip structure is more stable.
During the use process of the packaged chip, the chip is required to undergo a cold-hot cycle frequently, the thermal expansion coefficient of the protective layer 107 ranges from 3 ppm/K to 10ppm/K, the bare chip 113 has the same or similar thermal expansion coefficient, during the cold-hot cycle, the protective layer 107 and the bare chip 113 keep the expansion and contraction degrees caused by relative , the interface fatigue is prevented from being accumulated at the interface between the protective layer 107 and the bare chip 113, the packaged chip has durability, and the service life of the chip is prolonged.
In another aspect, the thermal expansion coefficient of the protective layer is too low, so that the composite material of the protective layer 107 needs to be filled with too many filler particles, and the young's modulus of the material is increased while the thermal expansion coefficient is further reduced by steps, so that the flexibility of the material of the protective layer is reduced, the rigidity is too high, and the buffer effect of the protective layer 107 is not good, and the thermal expansion coefficient of the protective layer is optimally limited to 5-10 ppm/k.
In preferred embodiments, the filler particles in the protective layer 107, such as inorganic oxide particles, e.g., SiO2Particles having a diameter of less than 3 μm, preferably filler particles in the protective layer 107, e.g. inorganic oxide particles, e.g. SiO2The diameter of the particles is 1-2 μm.
The diameter of the filler particles is controlled to be smaller than 3 μm, which is beneficial to forming a protective layer opening with a smoother side wall on the protective layer 107 in the laser patterning process, so that the material can be fully filled in the conductive material filling process, and the conductive material cannot be filled on the side wall 109c of the protective layer opening with large size and concave-convex at the back side of the side wall shielded by the protrusion, which affects the conductive performance of the conductive filling through hole 111.
Meanwhile, the filling size of 1-2 μm can expose the filler with small particle size in the laser patterning process, so that the side wall 109c of the opening of the protective layer has constant roughness, the side wall with constant roughness can be larger in contact surface with the conductive material, the contact is tighter, and the conductive filling through hole 111 with good conductivity is formed.
The above-mentioned diameter size of the filler is an average value of the particle diameter.
In preferred embodiments, the tensile strength of the protective layer 107 ranges from 20 MPa to 50MPa, and in preferred embodiments, the tensile strength of the protective layer 107 is 37 MPa.
Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, the back side 1002 of the wafer is ground to thin the wafer to a desired thickness.
Modern electronic devices are small and light, and chips tend to be thin, in this step, the wafer 100 may need to be thinned to a very thin thickness sometimes, however, the processing and transferring difficulty of the thin wafer 100 is great, the process difficulty of the grinding and thinning process is great, and it is often difficult to thin the wafer 100 to a desired thickness. When the surface of the wafer 100 has the protective layer 107, the protective layer 107 having material properties can support the wafer 100, thereby reducing the difficulty in processing, transferring and thinning the wafer 100.
As shown in fig. 3a, a protective layer opening 109 is formed on the surface of the protective layer 107.
A protective layer opening 109 is formed in the protective layer 107 at a location corresponding to the electrical connection point 103 on the wafer active side 1001, exposing the electrical connection point 103 on the wafer active side 1001.
Preferably, the protective layer opening 109 corresponds to between the electrical connection points 103 on the active side 1001 of the wafer.
Optionally, at least portions of the protective layer openings 109 correspond to a plurality of the electrical connection points 103 for every of the protective layer openings 109.
Optionally, at least portions of the electrical connection points 103 correspond to a plurality of the protective layer openings 109.
Optionally, at least portions of the protective layer openings 109 do not have corresponding electrical connection points 103, or at least portions of the electrical connection points 103 do not have corresponding protective layer openings 109.
Preferably, the protective layer opening is formed by laser patterning.
In the process flow of laser patterning to form the protective layer opening 2021, the electrically conductive cap layer formed on the electrical connection point 103 in the electroless plating process step can protect the electrical connection point 103 on the wafer active side 1001 from laser damage.
Preferably, as shown in the enlarged partial view of fig. 3a, a gap is provided between the lower surface 109a of the protective layer opening and the insulating layer 105, and/or the lower surface 109a of the protective layer opening is located at a position close to the center of the electrical connection point 103.
, the shape of the passivation opening 109 is such that the area of the passivation opening top surface 109b is larger than the area of the passivation opening bottom surface 109a, and the ratio of the area of the passivation opening bottom surface 109a to the area of the passivation opening top surface 109b is between 60% and 90%.
At this time, the slope of the sidewall 109c of the opening of the protection layer may facilitate the filling of the conductive material, and the conductive material may be uniformly and continuously formed on the sidewall during the filling process.
Optionally, as shown in fig. 3b, a conductive medium is filled in the passivation layer opening 109, such that the passivation layer opening 109 becomes a conductive filled via 111, and at least portions of the conductive filled via 111 are electrically connected to the electrical connection point 103 on the active side 1001 of the wafer, such that the conductive filled via 111 extends the electrical connection point 103 on the active side 1001 of the wafer to the surface of the passivation layer, and the passivation layer surrounds the conductive filled via 111, wherein the conductive medium may be gold, silver, copper, tin, aluminum, or a combination thereof, or may be formed by PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process on the passivation layer opening 109 to form the conductive filled via 111.
The conductive medium may be filled completely into the passivation opening 109, or may be formed only in the passivation opening 109 to form layers of conductive material, which can be electrically connected to the conductive layer.
By forming the passivation opening 109 on the passivation layer 107 and/or filling the conductive medium in advance, the position of the electrical connection point 103 on the active surface 1001 of the wafer can be precisely located through the passivation opening 109, the area of the passivation opening 109 can be made smaller, and the distance between the openings can also be made smaller, so that during the subsequent conductive layer forming step, the conductive trace can be tighter without worrying about the problem of the positional deviation of the electrical connection point 103.
As shown in fig. 4, the wafer 100 with the protective layer 107 applied thereon is cut along the dicing streets to obtain a plurality of dies 113 with the protective layer formed thereon, wherein the dies 113 have a die active surface 1131 and a die back surface 1132.
In embodiments, the wafer 100 with the protective layer 107 as shown in FIG. 2 is cut to form the die 113.
In embodiments, the wafer 100 with the protective layer 107 and the protective layer opening 109 as shown in fig. 3a is cut to form the die 113.
In embodiments, the wafer 100 with the protective layer 107 and the conductively filled vias 111 as shown in FIG. 3b is cut to form dies 113.
Due to the material properties of the protective layer, the separated die 113 is free of burrs and chips (die chips) during the dicing process of the wafer 100.
In embodiments, before the step of separating the die 113 by cutting the wafer 100, a step of performing plasma surface treatment on the surface of the wafer 100 with the protective layer 107 applied thereon to increase the surface roughness is further included, so that the adhesiveness of the die 113 on the carrier board 117 in the subsequent process is increased, and the die movement of the die 113 under the molding pressure is not easily generated.
It is understood that, when the process allows, after the wafer 100 is optionally cut into the dies 113 to be packaged according to specific practical situations, a protective layer is formed on the die active surface 1131 of each die 113 to be packaged.
As shown in fig. 5a, carrier boards 117 are provided, the carrier board 117 has a carrier board front side 1171 and a carrier board back side 1172, the divided dies 113 are arranged on the predetermined position of the carrier board front side 1171, the die active side 1131 faces the carrier board 117, and the die back side 1132 faces away from the carrier board 117.
The shape of the carrier plate 117 is: the carrier 117 may be a small wafer substrate or a rectangular carrier with various sizes, especially large sizes, and the material of the carrier 117 may be metal, nonmetal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-size quadrilateral panel made of stainless steel.
The carrier plate 117 has a carrier plate front side 113 and a carrier plate back side 115, the carrier plate front side 113 preferably being planes.
In embodiments, die 113 is bonded and secured to carrier board 117 with adhesive layer 121.
The adhesive layer 121 may be formed on the carrier plate front side 1171 by lamination, printing, spraying, coating, etc. In order to facilitate separation of the carrier board 117 and the die 113 subjected to back mold sealing in the subsequent process, the adhesive layer 121 is preferably made of a material that is easily separable, for example, a thermal separation material.
Preferably, the arrangement position of the bare chip 113 may be identified in advance on the carrier 117, the identification may be formed on the carrier 117 by laser, mechanical patterning, and the like, and the bare chip 113 is also provided with an alignment identification to aim at the pasting position on the carrier 117 when pasting.
Optionally, as shown in fig. 5b, in the times of packaging processes, a plurality of dies 113a and 113b, two of which may be more than two, may be arranged on the carrier 117 according to the requirements of the actual product, and packaged, and then cut into a plurality of packages after the packaging is completed, so that packages include a plurality of dies 113a and 113b to form a multi-chip module (MCM), and the positions of the dies 113a and 113b may be freely set according to the requirements of the actual product.
The die 113 arranged on the carrier board 117 may be the die 113 cut from the wafer 100 with the protective layer 107 as shown in fig. 2.
As shown in fig. 3a, the bare chip 113 cut from the wafer 100 having the protective layer 107 and the protective layer opening 109 may be in a hollow state after the bare chip 113 formed with the protective layer 107 and the protective layer opening 109 is adhered to the adhesive layer 121 of the carrier board 117.
There may also be die 113 cut from the wafer 100 with the protective layer 107 and conductively filled vias 111 as shown in fig. 3 b.
As shown in fig. 6, a molding layer 123 is formed.
A molding layer 123 is formed around the die 113 to be packaged and on the exposed surface of the carrier front side 1171 or the adhesive layer 121. the molding layer 123 is used to completely encapsulate the carrier front side 1171 and the die 113 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 117 is peeled off, the next packaging step can be continued on the reconstructed flat plate structure.
The side of the molding layer 123 that contacts the carrier plate front side 1171 or the adhesive layer 121 is defined as the molding layer front side 1231 and the side of the molding layer 123 that faces away from the carrier plate front side 1171 or the adhesive layer 121 is defined as the molding layer back side 1232.
Preferably, the front molding layer 1231 and the back molding layer 1232 are substantially flat and parallel to the front carrier 1171.
In the embodiment, the molding layer 123 is formed by molding an organic/inorganic composite material.
Preferably, the thermal expansion coefficient of the molding layer 123 is 3-10 ppm/K, in preferred embodiments the thermal expansion coefficient of the molding layer 123 is 5ppm/K, in another preferred embodiments the thermal expansion coefficient of the molding layer 123 is 7ppm/K, and in yet another preferred embodiments the thermal expansion coefficient of the molding layer 123 is 10 ppm/K.
Preferably, the molding layer 123 and the protection layer 107 have the same or similar thermal expansion coefficients.
The thermal expansion coefficient of the plastic package layer 123 is selected to be 3-10 ppm/K, the thermal expansion coefficient is selected to be the same as or similar to that of the protective layer 107, the expansion and contraction degree between the protective layer 107 and the plastic package layer 123 is kept in the heating and cooling processes of the plastic package process, interface stress is not easily generated between the two materials, the thermal expansion coefficients of the plastic package layer, the protective layer and the bare chip are close to each other due to the low thermal expansion coefficient, the interfaces of the plastic package layer 123, the protective layer 107 and the bare chip 113 are tightly combined, and interface layer separation is avoided.
The packaged chip is often required to undergo a cold-hot cycle in the use process, and because the thermal expansion coefficients of the protective layer 107, the plastic layer 123 and the bare chip 113 are similar, in the cold-hot cycle process, the fatigue of the interface between the protective layer 107 and the plastic layer 123 as well as the interface between the bare chip 113 is small, and an interface gap is not easy to occur between the protective layer 107, the plastic layer 123 and the bare chip 113, so that the service life of the chip is prolonged, and the applicable field of the chip is wide.
The difference between the thermal expansion coefficients of the bare chip 113 and the molding layer 123 also causes warpage of the molded panel assembly, and due to the warpage, it is difficult to position the bare chip 113 at the precise position in the panel assembly in the subsequent conductive layer forming process, which greatly affects the conductive layer forming process.
In particular, in the large panel packaging process, since the size of the panel is large, even if the panel is slightly warped, the position of the die in the outer peripheral portion of the panel away from the center is changed relatively to the position before molding, so that in the large panel packaging process, solving the warping problem becomes which is the key of the whole process, and the warping problem even limits the enlargement development of the panel size, and becomes a technical barrier in the large panel packaging process.
The thermal expansion coefficients of the protective layer 107 and the plastic package layer 123 are limited within the range of 3-10 ppm/K, and preferably, the plastic package layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, so that the generation of warping of a panel assembly can be effectively avoided, and the packaging process adopting a large panel is realized.
Meanwhile, in the plastic package process, since the pressure of the plastic package can generate pressure on the back of the bare chip 113, the pressure can easily press the bare chip 113 into the adhesive layer 121, so that the bare chip 113 is sunk into the adhesive layer 121 in the process of forming the plastic package layer 123, after the plastic package layer 123 is formed, the bare chip 113 and the front surface 1231 of the plastic package layer are not in the same plane, the surface of the bare chip 113 protrudes out of the front surface 1231 of the plastic package layer to form step-shaped structures, and in the subsequent conductive layer forming process, the conductive traces 125 correspondingly have step-shaped structures, so that the package structure is unstable.
When the die active surface 1131 has the protective layer 107 with material properties, the buffer effect can be achieved under the molding pressure, and the die 113 is prevented from sinking into the adhesive layer 121, so that the generation of the step-like structure on the front surface 1231 of the molding layer is avoided.
As shown in fig. 7a, the thickness of the molding layer 123 can be reduced by grinding or polishing the molding layer back surface 1232.
In , as shown in fig. 7b, the molding layer 123 can be thinned down to the die backside 1132 of the die 113, thereby exposing the die backside 1132, and the packaged chip structure is shown in fig. 13 b.
As shown in fig. 8, the carrier board 117 is peeled off to expose the molding layer front surface 1231 and the protection layer 107.
In embodiments, when the die 113 disposed on the carrier board 117 is in the form of the die 113 with the protection layer 107 and the protection layer opening 109 as shown in fig. 3a, the carrier board 1172 is peeled off to expose the protection layer opening 109.
In embodiments, when the die 113 disposed on the carrier board 117 is in the form of the die 113 cut from the wafer 100 having the protection layer 107 but not yet forming the protection layer opening on the protection layer 107 as shown in fig. 2, there is a step of forming the protection layer opening on the protection layer 107 on the die 113 covered by the molding compound layer 123 after the carrier board 117 is peeled off.
In the embodiments, when the die 113 arranged on the carrier board 117 is in the form of a die 113 cut from the wafer 100 having the protective layer 107 and the conductive filling via 111 as shown in fig. 3b, the conductive filling via 111 is also exposed.
The separated plastic package layer 123 coated with the bare chip 113 of the carrier 117 is defined as a panel assembly 150.
Fig. 9 and 10 illustrate an embodiment of a process for forming conductively filled vias and patterning a conductive layer on a die 113 in a molding layer 123.
When the conductive filling through hole 111 is not formed in the protection layer 107 coated on the surface of the die 113 in the molding layer 123, a conductive medium is filled in the protection layer opening 109, so that the protection layer opening 109 becomes the conductive filling through hole 111, and the conductive filling through hole 111 is electrically connected with the electrical connection point 103 on the wafer active surface 1001, so that the conductive filling through hole 111 extends the electrical connection point 103 on the wafer active surface 1001 to the surface of the protection layer in a single manner, and the protection layer surrounds the conductive filling through hole 111.
The conductive medium may be filled completely into the passivation opening 109, or may be formed only in the passivation opening 109 to form layers of conductive material, which can be electrically connected to the conductive layer.
Conductive traces (trace)125 are formed on the die 113 in the molding compound 123, at least portions of the conductive traces 125 are formed on the surface of the passivation layer 107 on the active surface 1131 of the die and are electrically connected to at least portions of the conductive filled vias 111. in embodiments, the conductive traces 125 extend along the surface of the passivation layer 107 and the molding compound front surface 1231 and extend to the edge of the chip package when the package is completed, and the packaged chip structure is shown in fig. 13 b. the conductive traces 125 extend to the edge of the package, and the conductive traces 125 cover and connect the interface between the passivation layer 107 and the molding compound 132, so as to increase the stability of the chip structure after the package.
The conductive traces 125 may be layers or layers of copper, gold, silver, tin, aluminum, or combinations thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.
Preferably, the conductively filled vias 111 and conductive traces 125 are formed in the same conductive layer forming step as .
Of course, it is also possible to form the conductive filled via 111 first and then form the conductive trace 125.
Fig. 10 illustrates the formation of conductive stud (stud)127 on the pad or connection point of conductive trace 125. conductive stud 127 may be round in shape, or may have other shapes such as oval, square, linear, etc. conductive stud 127 may be layers or layers of copper, gold, silver, tin, aluminum, or combinations thereof, or may be formed of other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.
The conductive layer is formed by conductive traces 125 and/or conductive posts 127, and may be layers or multiple layers.
As shown in fig. 11a and 11b, a dielectric layer 129 is formed on the conductive layer.
The dielectric layer 129 is formed or multiple layers on the surface of the conductive layer using suitable methods such as lamination, coating, spraying, printing, molding, and the like.
The dielectric layer 129 may be BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, polymer matrix dielectric film, organic polymer film, or organic composites, resin composites, polymer composites, such as epoxy with filler, ABF, or other polymers with suitable fillers, or other materials with similar insulating and structural properties, in preferred embodiments the dielectric layer 129 is ABF, the dielectric layer 129 serves to protect the conductive layer and insulate, in embodiments the dielectric layer 129 is applied thicker than the conductive layer, the conductive layer is exposed by a grinding process, in another embodiments the dielectric layer 133 is applied to the same thickness as the conductive layer, and the conductive layer is exposed after the dielectric layer 129 is applied.
In embodiments, the steps of fig. 9-11 b are repeated to form multiple conductive layers on the die active surface 1131 of die 113.
Returning again to the steps of fig. 9-11 b, in embodiments, the conductive layer may be formed by:
forming conductive traces 125 on a die active surface 1131 of die 113;
forming a layer or layers of dielectric layer 129 on the surface of conductive trace 125 using lamination, coating, spraying, printing, molding, and other suitable methods, the height of dielectric layer 129 being greater than the height of conductive trace 125, completely encapsulating conductive trace 125 within dielectric layer 129;
openings are formed in dielectric layer 129 corresponding to the pads or connections of conductive traces 125, within which conductive posts 127 are formed.
In yet another embodiment , the conductive posts 127 may not be formed in the openings, such that the pads or connection points of the conductive traces 125 of the completed package are exposed through the openings.
In the preferred embodiment of , after the step of applying the dielectric layer 129, the outermost conductive layer is etched to reduce its thickness to form a recess 131 in the outer surface of the dielectric layer 129, and the packaged chip structure is shown in fig. 13 b.
Alternatively, as shown in fig. 11b, in the packaging processes, a plurality of dies 113a and 113a, especially a plurality of dies 113a and 113a with different functions, two shown in the figure, or more than two shown in the figure, may be packaged into a multi-chip package assembly, the patterned design of the conductive layers of the dies 113a and 113b is designed according to the electrical connection requirement of the actual product, and the chip structure of the package molding is shown in fig. 13 c.
As shown in fig. 12, the packaged single body is cut to form a packaged chip, and the cutting can be performed by using a machine or a laser.
Fig. 13a, 13b and 13c are schematic views of chip package structures.
Fig. 13a is a schematic diagram of a chip package structure obtained by the packaging method provided in the exemplary embodiment of the present disclosure.
As shown in the figure, the chip package structure comprises a die 113, a protective layer 107, a conductive filling through hole 111, a conductive layer 123 and a dielectric layer, wherein the die 113 comprises a die active surface 1131 and a die back surface 1132, the die active surface 1131 comprises an electrical connection point 103 and an insulating layer 105, the protective layer 107 is formed on the die active surface 1131, the conductive filling through hole 111 is formed in the protective layer 107, at least parts of the conductive filling through hole 111 and at least parts of the electrical connection point 103 are electrically connected, the electrical connection point 103 is at least parts of the electrical connection point 103 is led out of the die active surface 1131, the plastic sealing layer 123 is used for encapsulating the die 113, the conductive layer is at least partially formed on the surface of the protective layer 107, the conductive layer is electrically connected with at least parts of the.
In embodiments, the Young's modulus of the protective layer 107 is any of value ranges or values of 1000 to 20000MPa, 1000 to 10000MPa, 4000 to 8000MPa, 1000 to 7000MPa, 4000 to 7000MPa, and 5500 MPa.
In embodiments, the material of the protective layer 107 is an organic/inorganic composite material.
In embodiments, the thickness of the passivation layer 107 is any of value ranges or values of 15-50 μm, 20-50 μm, 35 μm, 45 μm, and 50 μm.
In embodiments, the protective layer 107 has a thermal expansion coefficient of any of value ranges or values from 3 to 10ppm/K, 5ppm/K, 7ppm/K, 10 ppm/K.
In embodiments, the molding layer 123 has a thermal expansion coefficient of any of value ranges or values from 3 to 10ppm/K, 5ppm/K, 7ppm/K, and 10 ppm/K.
In embodiments, the protective layer 107 and the molding layer 123 have the same or similar coefficients of thermal expansion.
In embodiments, the protective layer 107 includes inorganic filler particles having a diameter of less than 3 μm or 1-2 μm.
In embodiments, the ratio of the area of the lower surface 111a of the conductively filled via to the area of the upper surface 111b of the conductively filled via is between 60% and 90%.
In embodiments, the conductively filled via 111 is formed for a conductive dielectric filled protective layer opening 109.
In embodiments, the electrical connection points 103 have a conductive coating formed thereon.
In embodiments, the conductively filled via lower surface 111a has a void between it and the insulating layer 105, as shown in the enlarged partial view of fig. 13 a.
In embodiments, the conductive filled via lower surface 111a is located near the center of the electrical connection point 103, as shown in the close up view of fig. 13 a.
In embodiments, the conductive layer includes conductive traces 125 and/or conductive posts 127, wherein at least the portion of the conductive traces 125 closest to the die active surface 1131 is formed on the surface of the protective layer 107 and electrically connected to the conductive filled vias 111.
The conductive posts 127 are formed on pads or connection points of the conductive traces 125.
The conductive layer may be layers or may be multi-layered.
In embodiments, as shown in fig. 13b, at least portions of the conductive traces 125 closest to the die active surface 1131 are formed on the molding layer front surface 1231 and extend to the edge of the package body.
In yet another embodiments, the die backside 1132 is exposed from the molding layer 123, as shown in fig. 13 b.
In still another embodiments, the surface of the dielectric layer 129 has a recess at a location corresponding to the conductive layer, as shown in FIG. 13 b.
In embodiments, as shown in FIG. 13c, the package structure includes a plurality of dies 113, and the plurality of dies 113 are electrically connected according to the product design.
Fig. 14a shows a schematic view of a packaged chip in use, during which the packaged chip is attached to a circuit board or substrate 161 by solder 160 and then connected to other circuit elements.
When the surface of the dielectric layer 129 of the packaged chip is provided with the groove 131, the solder 160 can be stably connected and is not easy to move.
Fig. 14b shows a schematic view of a packaged chip assembly in use, during which the packaged chip assembly is attached to a circuit board or substrate 161 by solder 160 and then connected to other circuit elements.
Although the present disclosure has been described in detail with reference to specific embodiments thereof for purposes of illustration , it will be understood by those skilled in the art that the present disclosure is not limited to the specific embodiments, and that various modifications, equivalents, improvements and the like can be made within the spirit and scope of the present disclosure.

Claims (16)

1, kinds of chip package structure, characterized by, include:
at least dies;
a protective layer on the side of die active surface and having a conductive filled via formed therein, at least portion of the conductive filled via being electrically connected to an electrical connection point;
a molding layer for encapsulating the die;
a conductive layer at least partially formed on the surface of the protective layer, at least portions of the conductive layer being electrically connected to the conductive filled vias;
a dielectric layer formed on the conductive layer;
the Young modulus of the protective layer is any value range or value of 1000-20000MPa, 1000-10000MPa, 4000-8000MPa and 5500 MPa.
2. The chip package structure according to claim 1, wherein the material of the protection layer is an organic/inorganic composite material.
3. The chip package structure of claim 1, wherein the thickness of the passivation layer is any value ranges or values from 15 μm to 50 μm, 20 μm to 50 μm, 35 μm, 45 μm, and 50 μm.
4. The chip package structure according to claim 1, wherein the thermal expansion coefficient of the protection layer is any value range or value from 3 ppm/K to 10ppm/K, 5ppm/K, 7ppm/K, 10 ppm/K.
5. The chip package structure of claim 1, wherein the molding layer has a thermal expansion coefficient of any value ranges from 3 ppm/K to 10ppm/K, 5ppm/K, 7ppm/K, or 10 ppm/K.
6. The chip package structure according to claim 1, wherein the protection layer and the molding layer have the same or similar thermal expansion coefficients.
7. The chip packaging structure according to claim 2, wherein the protective layer comprises inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or 1-2 μm.
8. The chip package structure according to claim 1, wherein the conductive filled via is formed by a conductive dielectric filled protection layer opening, the conductive filled via has a lower conductive filled via surface and an upper conductive filled via surface, and the area ratio of the lower conductive filled via surface to the upper conductive filled via surface is 60-90%.
9. The chip package structure according to claim 8, wherein a gap is formed between the lower surface of the conductive filled via and the insulating layer, and/or the lower surface of the conductive filled via is located at a position where the electrical connection point is approximately in the center.
10. The chip package structure according to any one of claims 1 to 9 and , wherein the conductive layer comprises conductive traces and/or conductive posts;
wherein at least portions of the conductive traces closest to the active side of the die are formed on the surface of the protective layer and electrically connected to the conductive filled vias;
the conductive layer is layers or a plurality of layers.
11. The chip package structure according to any one of claims 1 to 9 and , wherein the electrical connection points have a conductive coating formed thereon.
12. The chip package structure of claim 10, wherein at least portions of the conductive traces closest to an active side of the die are formed on the molding compound front side and extend to an edge of the package body.
13. The chip package structure according to any one of claims 1 to 9 and , wherein the die backside is exposed from the molding layer.
14. The chip package structure according to any one of claims 1 to 9 and , wherein the surface of the dielectric layer has a groove at a position corresponding to the conductive layer.
15. The chip package structure of any one of claims 1 to 9 and , wherein the at least number of dies is a plurality of dies, and the plurality of dies are electrically connected with each other according to a product design.
16. The chip package structure according to any one of claims 1 to 9 and , wherein the plurality of dies are dies with different functions to form a multi-chip assembly.
CN201921141727.6U 2019-03-04 2019-07-19 Chip packaging structure Active CN210006732U (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
SG10201901893Q 2019-03-04
SG10201901893Q 2019-03-04
SG10201902149Q 2019-03-11
SG10201902149Q 2019-03-11
SG10201902426V 2019-03-19
SG10201902426V 2019-03-19

Publications (1)

Publication Number Publication Date
CN210006732U true CN210006732U (en) 2020-01-31

Family

ID=69217701

Family Applications (6)

Application Number Title Priority Date Filing Date
CN201921141738.4U Active CN210006733U (en) 2019-03-04 2019-07-19 Chip packaging structure
CN201921141727.6U Active CN210006732U (en) 2019-03-04 2019-07-19 Chip packaging structure
CN201921142392.XU Active CN210182379U (en) 2019-03-04 2019-07-19 Chip packaging structure
CN201910656802.0A Pending CN110729270A (en) 2017-11-29 2019-07-19 Chip packaging method and packaging structure
CN201910657495.8A Pending CN110729272A (en) 2017-11-29 2019-07-19 Chip packaging method and packaging structure
CN201910656851.4A Pending CN110729271A (en) 2017-11-29 2019-07-19 Chip packaging method and packaging structure

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201921141738.4U Active CN210006733U (en) 2019-03-04 2019-07-19 Chip packaging structure

Family Applications After (4)

Application Number Title Priority Date Filing Date
CN201921142392.XU Active CN210182379U (en) 2019-03-04 2019-07-19 Chip packaging structure
CN201910656802.0A Pending CN110729270A (en) 2017-11-29 2019-07-19 Chip packaging method and packaging structure
CN201910657495.8A Pending CN110729272A (en) 2017-11-29 2019-07-19 Chip packaging method and packaging structure
CN201910656851.4A Pending CN110729271A (en) 2017-11-29 2019-07-19 Chip packaging method and packaging structure

Country Status (2)

Country Link
CN (6) CN210006733U (en)
TW (8) TWI725519B (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11232957B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US11114315B2 (en) 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
US11610855B2 (en) 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
CN113725100A (en) * 2020-03-27 2021-11-30 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113725102B (en) * 2020-03-27 2024-02-27 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113725090A (en) * 2020-03-27 2021-11-30 矽磐微电子(重庆)有限公司 Semiconductor packaging method
CN113725095A (en) * 2020-03-27 2021-11-30 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113725098B (en) * 2020-03-27 2023-12-26 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113725101B (en) * 2020-03-27 2024-02-27 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113471086A (en) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN115692331A (en) * 2021-07-30 2023-02-03 矽磐微电子(重庆)有限公司 Chip packaging structure and manufacturing method thereof
TW202320276A (en) * 2021-11-04 2023-05-16 胡迪群 Semiconductor substrate structure and manufacturing method thereof
TWI806263B (en) * 2021-11-30 2023-06-21 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI822387B (en) * 2022-10-11 2023-11-11 廖富江 Semiconductor device, semiconductor package and manufacturing method the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120326300A1 (en) * 2011-06-24 2012-12-27 National Semiconductor Corporation Low profile package and method
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US9419156B2 (en) * 2013-08-30 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method for integration of heterogeneous integrated circuits
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
CN104779220A (en) * 2015-03-27 2015-07-15 矽力杰半导体技术(杭州)有限公司 Chip packaging structure and manufacture method thereof
US10636773B2 (en) * 2015-09-23 2020-04-28 Mediatek Inc. Semiconductor package structure and method for forming the same
US20170133334A1 (en) * 2015-11-09 2017-05-11 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR102448099B1 (en) * 2016-06-02 2022-09-27 에스케이하이닉스 주식회사 Semiconductor package including heat spreader
KR102576764B1 (en) * 2016-10-28 2023-09-12 에스케이하이닉스 주식회사 Semiconductor packages of asymmetric chip stacks
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10204889B2 (en) * 2016-11-28 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming thereof
CN106601627A (en) * 2016-12-21 2017-04-26 江苏长电科技股份有限公司 Process of first sealing then corrosion electro copper column conduction three-dimensional packaging structure
TW201832297A (en) * 2017-02-20 2018-09-01 力成科技股份有限公司 Package on package structure and manufacturing method thereof
TWI621187B (en) * 2017-03-07 2018-04-11 力成科技股份有限公司 Package on package structure and manufacturing method thereof
TW201836098A (en) * 2017-03-17 2018-10-01 力成科技股份有限公司 Semiconductor package structure and manufacturing method thereof
US10177011B2 (en) * 2017-04-13 2019-01-08 Powertech Technology Inc. Chip packaging method by using a temporary carrier for flattening a multi-layer structure
TWI637474B (en) * 2017-06-03 2018-10-01 力成科技股份有限公司 Package structure and manufacturing method thereof
US10163803B1 (en) * 2017-06-20 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same
TWI635579B (en) * 2017-07-13 2018-09-11 力成科技股份有限公司 Package structure and manufacturing method thereof

Also Published As

Publication number Publication date
TWM601901U (en) 2020-09-21
TW202034441A (en) 2020-09-16
TWM589895U (en) 2020-01-21
TWI728434B (en) 2021-05-21
TWM589897U (en) 2020-01-21
CN210006733U (en) 2020-01-31
CN110729271A (en) 2020-01-24
TWI756076B (en) 2022-02-21
TW202129829A (en) 2021-08-01
CN110729272A (en) 2020-01-24
TW202135252A (en) 2021-09-16
TWI725519B (en) 2021-04-21
CN210182379U (en) 2020-03-24
TW202034442A (en) 2020-09-16
CN110729270A (en) 2020-01-24
TW202036813A (en) 2020-10-01
TWI751944B (en) 2022-01-01

Similar Documents

Publication Publication Date Title
CN210006732U (en) Chip packaging structure
TWI772672B (en) Chip packaging method and chip packaging structure
US10128211B2 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
CN107887346B (en) Integrated fan-out package
US11233028B2 (en) Chip packaging method and chip structure
US10121736B2 (en) Method of fabricating packaging layer of fan-out chip package
US20210398822A1 (en) Chip packaging method and package structure
CN217035634U (en) Chip packaging structure and chip structure
US11232957B2 (en) Chip packaging method and package structure
US11610855B2 (en) Chip packaging method and package structure
US20240030174A1 (en) Quad flat no-lead (qfn) package with backside conductive material and direct contact interconnect build-up structure and method for making the same
CN112133695B (en) System-in-package structure and manufacturing method thereof

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant