TWM589895U - Chip package structure - Google Patents

Abstract

The present disclosure provides a chip packaging structure, which includes: at least one crystal grain, the crystal grain including a crystal grain active surface and a crystal grain back surface; a conductive structure formed on one side of the crystal grain active surface; having A protective layer with material characteristics is formed on the side of the active surface of the crystal grain; a plastic encapsulation layer with material characteristics, the plastic encapsulation layer is used to encapsulate the crystal grain; and a dielectric layer. The chip packaging structure has a series of materials and structural characteristics, thereby reducing warpage during the packaging process, reducing the accuracy requirements of the die, reducing the difficulty of the panel packaging process, and making the packaged wafer structure durable to use The cycle is especially suitable for large-scale panel-level packaging and packaging of large electric flux and thin chips.

Description

Chip packaging structure

The present disclosure relates to the field of semiconductor technology, and in particular to a wafer packaging structure.

A panel-level package (panel-level package) is to separate a plurality of dies from a wafer by cutting, arranging and pasting the dies on a carrier board, and encapsulating the plurality of dies simultaneously in the same process. Panel-level packaging has attracted widespread attention as a technology that has emerged in recent years. Compared with traditional wafer-level packages, panel-level packaging has the advantages of high production efficiency, low production cost, and is suitable for large-scale production.

However, there are many technical barriers to panel packaging, such as the warpage of the panel; the accuracy of die alignment on the panel.

Especially in today's trend of small and light-weight electronic devices, small and thin wafers are increasingly favored by the market. However, the difficulty of packaging technology using large panel packaging technology to package small and thin wafers cannot be underestimated.

The present disclosure provides a chip packaging structure including: at least one die, the die including a die active surface and a die back surface; a conductive structure formed on one side of the die active surface; a protective layer formed on One side of the active surface of the crystal grain; a plastic encapsulation layer for encapsulating the crystal grain; and a dielectric layer.

In one embodiment, the conductive structure includes a wafer conductive layer, a conductive filled via, and a panel-level conductive layer; the conductive filled via is formed in the protective layer.

In another embodiment, the conductive filled via has a lower surface of the conductive filled via and an upper surface of the conductive filled via, and the area of the lower surface of the conductive filled via is smaller than the area of the upper surface of the conductive filled via.

In still another embodiment, the active surface of the die includes an electrical connection point and an insulating layer; at least a portion of the wafer conductive layer and at least a portion of the electrical connection point are electrically connected to connect at least a portion of the electrical connection point It is drawn from the active surface of the crystal grain; the lower surface of the conductive filled via is electrically connected to the conductive layer of the wafer; the upper surface of the conductive filled via is electrically connected to the panel-level conductive layer.

In one embodiment, at least a portion of the wafer conductive layer separates at least a portion of the electrical connection points.

In another embodiment, at least a part of the wafer conductive layer interconnects and leads out a plurality of the electrical connection points in at least a part.

In yet another embodiment, the contact area of the wafer conductive layer and the single contact area of the electrical connection point is smaller than the contact area of the wafer conductive layer and the single contact area of the conductive filled via.

In one embodiment, the panel-level conductive layer includes conductive traces and/or conductive bumps; the conductive bumps are formed on pads or connection points of the conductive traces; the dielectric layer, including Covering the panel-level conductive layer; the panel-level conductive layer is one or more layers.

In one embodiment, at least a portion of the conductive trace closest to the active surface of the die is formed on the front of the plastic encapsulation layer and extends to the edge of the package.

In another embodiment, the back side of the die is exposed from the molding compound layer.

In still another embodiment, the surface of the dielectric layer has a groove at a position corresponding to the conductive layer.

In one embodiment, the at least one die is a plurality of die, and the plurality of die are electrically connected according to product design.

In another embodiment, the plurality of dies are dies with different functions to form a multi-chip module.

In another embodiment, the material of the protective layer is an organic/inorganic composite material.

In one embodiment, the Young's modulus of the protective layer is any one of the following numerical ranges or values: 1000~20000 MPa, 1000~10000 MPa, 4000~8000 MPa, 1000~7000 MPa, 4000~7000 MPa, 5500 MPa.

In still another embodiment, the thickness of the protective layer is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In one embodiment, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In another embodiment, the thermal expansion coefficient of the plastic encapsulation layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In still another embodiment, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients.

In one embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

In one embodiment, the diameter of the inorganic filler particles is 1-2 μm.

In order to make the technical solutions of the present disclosure clearer and the technical effects clearer, the following gives detailed and specific descriptions and descriptions of the preferred embodiments of the present disclosure in conjunction with the drawings, and it cannot be understood that the following descriptions are the only implementation form of the present disclosure or Open restrictions.

1 to 14 are flowcharts of a chip packaging method according to an exemplary embodiment of the present disclosure.

As shown in FIG. 1, at least one wafer 100 is provided. The wafer 100 has a wafer active surface 1001 and a wafer back surface 1002. The wafer 100 includes a plurality of dies 113, wherein the active surface of each die constitutes Wafer active surface 1001, the active surface of each die in the wafer 100 forms a series of active components and passive components through a series of processes such as doping, deposition, etching, etc. The active components include diodes, triodes, etc. Passive components include voltage regulators, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form functional circuits, so as to realize various functions of the chip. The wafer active surface 1001 further includes an electrical connection point 103 for leading out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103.

As shown in FIGS. 2a and 2b, a wafer conductive layer 106 is formed on the wafer active surface 1001.

The wafer conductive layer 106 may be copper, gold, silver, tin, aluminum, or other materials or a combination thereof, or may be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, Or other suitable metal deposition process.

At least a portion of the wafer conductive layer 106 is electrically connected to at least a portion of the electrical connection point 103 on the wafer active surface 1001.

Optionally, as shown in FIG. 2a, the wafer conductive layer 106 interconnects and leads out a plurality of the electrical connection points 103 in at least a portion of the active surface 1001 of the wafer.

The formation of the wafer conductive layer 106 can reduce the number of protective layer openings 109 formed in the subsequent process. The wafer conductive layer 106 is used to first interconnect multiple electrical connection points 103 according to the circuit design, eliminating the need for each electrical connection point The requirement of forming a protective layer opening 109 on 103.

Optionally, as shown in FIG. 2b, the wafer conductive layer 106 leads at least a part of the electrical connection points 103 on the active surface 1001 of the wafer separately.

The formation of the wafer conductive layer 106 helps to reduce the difficulty of forming the protective layer opening 109 later. Due to the presence of the wafer conductive layer 106, the lower surface 109a of the protective layer opening can have a larger area. Correspondingly, Providing the protective layer opening 109 with a larger area, especially on the wafer 100 having the smaller exposed electrical connection points 103, enables the formation of the protective layer opening.

Although not shown in the figure, it can be understood that the wafer conductive layer 106 leads a part of the electrical connection points 103 on the active surface 1001 of the wafer separately and connects the In another part, the electrical connection points 103 are interconnected and led out.

As shown in FIG. 3, a protective layer 107 is applied on the wafer active surface 1001 and the wafer conductive layer 106.

The protective layer 107 uses an insulating material, such as BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), polymer matrix dielectric film, organic polymer film, or Other materials with similar insulation and structural properties are formed by lamination, coating, printing, etc.

In one embodiment, the protective layer is applied in a laminated manner.

Optionally, before the step of applying the protective layer 107, physical and/or chemical treatment is performed on the wafer active surface 1001 and/or the side of the protective layer 107 applied to the wafer 100, to The bonding between the protective layer 107 and the wafer 100 is made closer. The treatment method is optionally plasma surface treatment to roughen the surface to increase the bonding area and/or chemical acceleration modifier treatment, introducing a modification-promoting group between the wafer 100 and the protective layer 107, For example, surface modifiers with both affinity organic and affinity inorganic groups increase the adhesion between the organic/inorganic interface layer.

The protective layer 107 can be used to protect the crystal active surface 1131. In the subsequent molding process, due to the molding pressure, the molding material flowing under the heating condition tends to penetrate into the gap between the die 113 and the carrier plate 117, especially when the wafer conductive layer 106 is formed on the die active surface 1131. The gap between the crystal grains and the carrier plate becomes larger, and the plastic packaging material easily penetrates during plastic packaging. When the crystal active surface 1131 has a protective layer, the protective layer 107 can protect the crystal active surface 1131 from penetration of the molding compound to protect the crystal active surface 1131 from damage.

The presence of the protective layer 107 can also make the adhesion between the die 113 and the adhesive layer 121 stronger, so that during the molding process, the molding pressure is not easy to cause the die 113 to be on the carrier board A position shift occurred on 117.

In a preferred embodiment, the Young's modulus of the protective layer 107 is in the range of 1000~20000 MPa, more preferably, the Young's modulus of the protective layer 107 is in the range of 1000~10000 MPa; further preferred The Young's modulus of the protective layer 107 is 1000 to 7000, 4000 to 7000, or 4000 to 8000 MPa; in a preferred embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

In a preferred embodiment, the thickness of the protective layer 107 is in the range of 15-50 μm; more preferably, the thickness of the protective layer is in the range of 20-50 μm; in a preferred embodiment, the protective layer The thickness of 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus of the protective layer 107 ranges from 1000 to 20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient support The force makes the protective layer 107 have sufficient support for the conductive layer formed on its surface. At the same time, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient cushioning and support.

Especially in some types of wafers, it is necessary to use thin die for packaging, and the conductive layer needs to reach a certain thickness to form a large electrical flux. At this time, the thickness of the protective layer 107 is selected to be 15-50 μm The value range of the Young's modulus of the protective layer 107 is 1000~10000MPa. The protective layer 107, which is soft and flexible, can form a buffer layer between the die 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the wafer, the conductive layer on the surface of the protective layer does not The crystal grains 113 will be excessively compressed to prevent the pressure of the thick conductive layer from crushing the crystal grains 113. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000~20000MPa, especially when the Young's modulus of the protective layer 107 is 4000~8000MPa, when the thickness of the protective layer 107 is 20~50μm, due to The material characteristics of the protective layer 107, so that the protective layer 107 can effectively protect the crystal grains against the thimble pressure of the crystal grain transfer equipment during the subsequent crystal grain transfer process;

The grain transfer process is a process of rearranging and bonding the separated and separated grains 113 to the carrier board 117 (reconstruction process). The grain transfer process requires the use of a grain transfer device (bonder machine), which includes a thimble Then, the die 113 on the wafer 100 is lifted up with a thimble, and the lifted die 113 is transferred with a suction head (bonder head) to be transferred and bonded to the carrier board 117.

In the process of ejecting the grain 113 by the thimble, the grain 113, especially the thin grain 113, is brittle and easily broken by the ejection pressure of the thimble. The protective layer 100 with material characteristics can protect the brittle crystal in this process The grain 113 can keep the grain 113 intact even under a relatively large jacking pressure.

In a preferred embodiment, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO ₂ particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types Of inorganic oxide particles, such as SiO ₂ mixed with TiO ₂ particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, are spherical or spherical. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed with TiO ₂ particles, the filling amount is more than 50%.

Organic materials have the advantages of easy operation and easy application. The grains to be packaged 113 are inorganic materials, such as silicon materials. When the protective layer 107 uses organic materials alone, due to the difference between the material properties of the organic materials and the inorganic materials The difference will make the packaging process difficult and affect the packaging effect. The use of organic/inorganic composite materials in which inorganic particles are added to organic materials will modify the material properties of the organic materials, so that the materials have both the characteristics of organic materials and inorganic materials.

In a preferred embodiment, when (T>Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm/K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the subsequent plastic packaging process, the grains 113 with the protective layer 107 applied will expand and contract accordingly during the heating and cooling process of the plastic packaging process, when the thermal expansion coefficient of the protective layer 107 is in the range of 3 to 10 ppm/K , The degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, the connection interface between the protective layer 107 and the die 113 is not easy to produce interface stress, and it is not easy to damage the connection between the protective layer 107 and the die 113, so that after packaging The wafer structure is more stable.

The packaged wafers often need to undergo cold and heat cycles during use. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the die 113 has the same or similar thermal expansion coefficient. During the cold and thermal cycle, the protective layer 107 It maintains a relatively consistent degree of expansion and contraction with the die 113 to prevent accumulation of interface fatigue at the interface between the protective layer 107 and the die 113, so that the packaged wafer has durability and extends the service life of the wafer.

On the other hand, the thermal expansion coefficient of the protective layer is too small, and it is necessary to fill the composite material of the protective layer 107 with too much filler particles. While further reducing the thermal expansion coefficient, it will also increase the Young's modulus of the material and make the protective layer material The flexibility is reduced, the rigidity is too strong, and the cushioning effect of the protective layer 107 is not good. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10 ppm/k.

In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles have a diameter of less than 3 μm, the preferred filler particles in the protective layer 107, such as inorganic oxide particles For example, the diameter of SiO ₂ particles is between 1 and 2 μm.

Controlling the diameter of the filler particles to be less than 3 μm is conducive to the formation of a protective layer opening with smoother sidewalls on the protective layer 107 in the laser patterning manufacturing process, so that the material can be fully filled in the conductive material filling process, avoiding large The side wall 109c of the protective layer opening with uneven size cannot be filled with conductive material behind the side wall covered by the protrusion, which affects the conductive performance of the conductive filled via 111.

At the same time, the filling size of 1~2μm will expose the filler with small particle size during the laser patterning process, so that the protective opening side wall 109c has a certain roughness, and this side wall with a certain roughness will interact with the conductive material The contact surface is larger and the contact is closer, forming a conductive filled via 111 with good conductivity.

The diameter of the filler mentioned above is the average of the particle diameters.

In a preferred embodiment, the numerical value of the tensile strength of the protective layer 107 is 20-50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after applying the protective layer 107 on the active surface 1001 of the wafer, the back surface 1002 of the wafer is ground to reduce the thickness of the wafer to a desired thickness.

Modern electronic equipment is small and lightweight, and the wafer has a thinning trend. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 is difficult and grinding The process of the thinning process is difficult, and it is often difficult to thin the wafer 100 to an ideal thickness. When a protective layer 107 is provided on the surface of the wafer 100, the protective layer 107 with material characteristics will support the wafer 100, reducing the difficulty of processing, transferring, and thinning the wafer 100.

As shown in FIGS. 4a and 4b, a protective layer opening 109 is formed on the surface of the protective layer 107.

At least a portion of the protective layer opening 109 corresponds to the wafer conductive layer 106, and the wafer conductive layer 106 is exposed through the protective layer opening 109; the protective layer opening 109 has a protective layer opening lower surface 109a and a protective layer opening Upper surface 109b.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening. In this case, the slope of the side wall 109c of the protective layer opening can fill the conductive material Easy to carry out, during the filling process, the conductive material will be uniformly and continuously formed on the side wall.

Optionally, each of the at least a portion of the wafer conductive layers 106 corresponds to one or more protective layer openings 109.

Optionally, the contact area α1 of the single contact area of the wafer conductive layer 106 and the electrical connection point 103 is smaller than the contact area β1 of the single contact area of the wafer conductive layer 106 and the protective layer opening 109.

When the type of the wafer 100 is that the exposed electrical connection points 103 have a small area, forming a conductive layer on the wafer active surface 1001 and then forming a protective layer opening can effectively reduce the difficulty of forming the protective layer opening, avoiding the protective layer The opening lower surface 109a is too small, making it difficult to form the protective layer opening 109.

Preferably, the protective layer opening is formed in a laser patterning manner.

Corresponding to the wafer conductive layer 106 in FIG. 2a, FIG. 4a shows that the protective layer 107 is formed on the wafer conductive layer 106 interconnecting and drawing a plurality of the electrical connection points 103 with each other. Each wafer conductive layer 106 corresponds to multiple protective layer openings 109. It can be understood that each wafer conductive layer 106 can correspond to one protective layer opening 109, or can correspond to one protective layer opening 109 for a portion of the wafer conductive layer 106. , Another portion of the wafer conductive layer 106 corresponds to a plurality of protective layer openings 109.

Corresponding to the wafer conductive layer 106 in FIG. 2b, FIG. 4b shows that the protective layer 107 is formed on the wafer conductive layer 106 which leads the electrical connection point 103 separately, preferably, each wafer conductive layer 106 may correspond to one protective layer opening 109.

Optionally, as shown in FIG. 5, the protective layer opening 109 is filled with a conductive medium, so that the protective layer opening 109 becomes a conductive filled through hole 111, and at least a part of the conductive filled through hole 111 and the wafer The conductive layer 106 is electrically connected, and the protective layer surrounds the conductive filled via 111. The conductive medium can be gold, silver, copper, tin, aluminum, or other materials or a combination of materials, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating process, or other suitable metals A deposition process is formed in the protective layer opening 109 to form a conductive filled via 111.

The filling of the conductive medium may be the complete filling of the protective layer opening 109, or it may be that only a layer of conductive material is formed in the protective layer opening 109, which can be electrically connected to the panel-level conductive layer. Correspondingly, the conductive filled via 111 is understood as long as a conductive medium is provided in the opening of the protective layer, and the conductive medium can be electrically connected to the panel-level conductive layer, and it is not necessary to completely fill the opening of the protective layer.

First, the wafer conductive layer 106 is electrically connected to the electrical connection point 103. Since the wafer conductive layer 106 is formed at the wafer level, its alignment accuracy with the electrical connection point 103 is high, and then by forming a protective layer opening on the protective layer 107 109 and/or a method of filling with a conductive medium, so that the position of the wafer conductive layer 106 can be accurately positioned through the protective layer opening 109.

As shown in FIG. 6, the wafer 100 on which the wafer conductive layer 106 and the protective layer 107 have been applied is cut along the scribe line to obtain a plurality of crystal grains 113 having the crystal grain active surface 1131 and The back of the die 1132.

In one embodiment, the wafer 100 having the wafer conductive layer 106 and the protective layer 107 as shown in FIG. 3 is cut to form the die 113.

In one embodiment, the wafer 100 having the wafer conductive layer 106, the protective layer 107 and the protective layer opening 109 as shown in FIGS. 4 a and 4 b is cut to form a die 113.

In one embodiment, the wafer 100 having the wafer conductive layer 106, the protective layer 107 and the conductive filled via 111 as shown in FIG. 5 is cut to form a die 113.

Due to the material characteristics of the protective layer, in the dicing process of the wafer 100, the separated crystal grains 113 are free of burrs and die chips.

In one embodiment, before the step of cutting the wafer 100 to separate the die 113, the method further includes performing plasma surface treatment on the side of the wafer 100 to which the protective layer 107 is applied, having the protective layer 107, The surface roughness is increased to increase the adhesion of the crystal grains 113 on the carrier board 117 in the subsequent process, and it is difficult for the crystal grains 113 to move under the molding pressure.

It can be understood that, if the process permits, after the wafer 100 is selectively cut into the dies 113 to be packaged according to the specific actual situation, crystals are formed on the die active surface 1131 of each die 113 The round conductive layer 106 and/or the protective layer 107. The wafer conductive layer 106 refers to the conductive layer formed before the wafer 100 is cut into the die 113 and mounted on the carrier board.

As shown in FIGS. 7a, 7b and 7c, a carrier board 117 is provided. The carrier board 117 has a carrier board front 1171 and a carrier board back 1172. The carrier board 117 is arranged and divided at preset positions on the carrier board front 1171 The die 113, the die active surface 1131 faces the carrier plate 117, and the die back 1132 is arranged away from the carrier plate 117.

The shape of the carrier board 117 is: round, triangular, quadrangular or any other shape. The size of the carrier board 117 can be a small-sized wafer substrate, or a rectangular carrier board of various sizes, especially a large size, carrier board The material of 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a quadrilateral large-size panel made of stainless steel.

The carrier board 117 has a carrier board front 113 and a carrier board back 115, and the carrier board front 113 is preferably a flat surface.

In one embodiment, the die 113 is bonded and fixed on the carrier board 117 by the adhesive layer 121.

The adhesive layer 121 may be formed on the front surface 1171 of the carrier board by lamination, printing, spraying, coating, or the like. In order to facilitate the separation of the carrier board 117 and the back-molded die 113 in the subsequent process, the adhesive layer 121 preferably uses a material that can be easily separated, for example, a thermal separation material is used as the adhesive layer 121.

Preferably, the position where the die 113 is arranged can be pre-marked on the carrier plate 117. The logo can be formed on the carrier plate 117 by means of laser, mechanical engraving, etc. At the same time, the die 113 is also provided with an alignment mark To aim and align with the pasting position on the carrier board 117 during pasting.

The form of the die 113 arranged on the carrier 117 may be the wafer conductive layer 106 on the die 113 shown in FIG. The electrical connection points 103 are in the form of grains interconnected with each other and lead out; at least a part of the electrical connection on the active surface 1131 of the grain may be electrically connected to the wafer conductive layer 106 as shown in FIG. 7b The form of the grains led out by the point 103 alone; it can also be in the form of the grains 113 formed by cutting the wafer 100 having the wafer conductive layer 106 and the protective layer 107 shown in FIG. 3; the cutting is shown in FIG. 5 The wafer 100 having the wafer conductive layer 106, the protective layer 107, and the conductive filled via 111 is formed in the form of a die 113.

Optionally, as shown in FIG. 7c, in one packaging process, multiple, especially multiple die 113a and 113b with different functions may be used. Two or more than two die shown in the figure may be used. The actual product needs are arranged on the carrier board 117 and packaged. After the package is completed, it is cut into multiple packages; thus one package includes a plurality of the die 113a and 113b to form a multi-chip module (Multi-chip module, MCM), and the positions of the plurality of die 113a and 113b can be freely set according to the needs of actual products.

As shown in FIG. 8, the plastic encapsulation layer 123 is formed.

A plastic encapsulation layer 123 is formed around the die 113 to be packaged and the exposed surface of the front surface 1171 of the carrier board or the exposed surface of the adhesive layer 121. The plastic encapsulation layer 123 is used to completely encapsulate the front surface 1171 of the carrier board and the die 113 to be encapsulated, so as to reconstruct a flat plate structure, so that after the carrier board 117 is peeled off, it can continue on the reconstructed flat plate structure. Packaging steps.

The surface of the plastic encapsulation layer 123 in contact with the front surface 1171 of the carrier board or the adhesive layer 121 is defined as the front surface 1231 of the plastic packaging layer. The side of the plastic encapsulation layer 123 facing away from the front surface 1171 of the carrier board or the adhesive layer 121 is defined as the back surface 1232 of the plastic encapsulation layer.

Preferably, the front surface 1231 of the plastic encapsulation layer and the rear surface 1232 of the plastic encapsulation layer are substantially flat and parallel to the front surface 1171 of the carrier board.

The plastic sealing layer 123 may use paste printing, injection molding, hot compression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic encapsulation layer 123 may be an organic composite material, a resin composite material, a polymer composite material, or a polymer composite material, such as epoxy resin with filler, ABF (Ajinomoto buildup film), or other polymers with suitable fillers.

In one embodiment, the plastic encapsulation layer 123 is formed by compression molding using an organic/inorganic composite material.

Preferably, the thermal expansion coefficient of the plastic encapsulation layer 123 is 3-10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is 5 ppm/K; in another preferred embodiment, the plastic encapsulation layer The thermal expansion coefficient of 123 is 7 ppm/K; in yet another preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is 10 ppm/K.

Preferably, the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic sealing layer 123 is selected to be 3~10 ppm/K and the thermal expansion coefficient of the protective layer 107 is selected to be the same or similar. During the heating and cooling of the plastic sealing process, the expansion and contraction between the protective layer 107 and the plastic sealing layer 123 The degree of consistency is the same, and the two materials are not easy to produce interface stress. The low thermal expansion coefficient makes the thermal expansion coefficients of the plastic encapsulation layer, the protective layer and the grains close, so that the interfaces of the plastic encapsulation layer 123, the protective layer 107 and the grain 113 are closely combined to avoid the generation of an interface Layer separation.

During the use of the packaged wafer, it is often necessary to undergo a cold and hot cycle. Because the thermal expansion coefficients of the protective layer 107, the plastic encapsulation layer 123 and the die 113 are similar, during the cold and hot cycle, the protective layer 107 and the plastic encapsulation layer 123 and the die 113 The interface fatigue is small, and the interface gap is not easy to occur between the protective layer 107, the plastic encapsulation layer 123 and the die 113, so that the service life of the chip is increased, and the applicable fields of the chip are wide.

The difference between the thermal expansion coefficients of the die 113 and the plastic encapsulation layer 123 can also cause warpage of the panel module after plastic encapsulation. Due to the occurrence of the warpage phenomenon, it is difficult to locate the die 113 in the panel module in the subsequent conductive layer formation process The precise location of the metal has a great influence on the formation process of the conductive layer.

In particular, in the large panel packaging process, due to the large size of the panel, even a slight panel warpage will cause the outer periphery of the panel to be far away from the center. Because of the change of position, in the large-scale panel packaging process, solving the warpage problem has become one of the keys of the whole process. The warpage problem even limits the enlargement of the panel size and becomes a technical barrier in large-size panel packaging.

The thermal expansion coefficients of the protective layer 107 and the plastic encapsulation layer 123 are limited to the range of 3-10 ppm/K, and it is preferable that the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can be effective To avoid the generation of warpage of the panel module, realize the packaging process using a large panel.

At the same time, during the plastic encapsulation process, the pressure of the plastic encapsulation will generate pressure on the back of the die 113, and this pressure will easily press the die 113 into the adhesive layer 121, thereby causing the die 113 to fall into the process of forming the plastic encapsulation layer 123 In the adhesive layer 121, after the plastic encapsulation layer 123 is formed, the crystal grain 113 and the front surface 1231 of the plastic encapsulation layer are not in the same plane. The surface of the crystal grain 113 protrudes beyond the front surface 1231 of the plastic encapsulation layer to form a stepped structure. During the formation of the conductive layer, the conductive trace 125 also correspondingly has a stepped structure, making the packaging structure unstable.

When the active surface 1131 of the die has a protective layer 107 with material properties, it can play a buffering role under the pressure of the plastic packaging to prevent the crystal 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a stepped structure on the front surface 1231 of the plastic packaging layer.

As shown in FIG. 9a, the thickness of the plastic encapsulation layer 123 can be reduced by grinding or polishing the back surface 1232 of the plastic encapsulation layer.

In one embodiment, as shown in FIG. 9b, the thickness of the plastic encapsulation layer 123 may be reduced to the back surface 1132 of the die 113, thereby exposing the back surface 1132 of the die. The packaged and molded wafer structure is shown in Figure 15b.

As shown in FIG. 10, the carrier board 117 is peeled off to expose the front surface 1231 of the plastic encapsulation layer and the protective layer 107.

In one embodiment, when the die 113 arranged on the carrier plate 117 has the protective layer opening 109, the carrier plate 117 is peeled off, and the protective layer opening 109 is also exposed.

In one embodiment, when the die 113 arranged on the carrier board 117 has not yet formed a protective layer opening on the protective layer 107, after the peeling of the carrier board 117 is still there The step of forming a protective layer opening on the protective layer 107 on the die 113 covered by the plastic encapsulation layer 123.

In one embodiment, when the die 113 arranged on the carrier board 117 is a die 113 having a conductive filled via 111, the conductive filled via 111 is also exposed.

After the carrier board 117 is separated, the structure of the plastic encapsulation layer 123 coated with the die 113 is defined as the panel module 150.

11 and 12 show one embodiment of the process of forming a patterned panel-level conductive layer on the die 113 in the plastic encapsulation layer 123.

When the protective layer 107 covering the surface of the die 113 in the plastic encapsulation layer 123 has not yet formed a conductive filled via 111, the protective layer opening 109 is filled with a conductive medium so that the protective layer opening 109 becomes a conductive filled via 111. At least a part of the conductive filled via 111 is electrically connected to the wafer conductive layer 106, and the protective layer surrounds the conductive filled via 111. The conductive medium can be gold, silver, copper, tin, aluminum, or other materials or a combination of materials, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating process, or other suitable metals A deposition process is formed in the protective layer opening 109 to form a conductive filled via 111.

The filling of the conductive medium may be the complete filling of the protective layer opening 109, or it may be that only a layer of conductive material is formed in the protective layer opening 109, which can be electrically connected to the panel-level conductive layer. Correspondingly, the conductive filled via 111 is understood as long as a conductive medium is provided in the opening of the protective layer, and the conductive medium can be electrically connected to the panel-level conductive layer. It is not necessary to completely fill the opening of the protective layer.

FIG. 11 shows that a conductive trace 125 is formed on the grain 113 in the plastic encapsulation layer 123; at least a part of the conductive trace 125 is formed on the surface of the protective layer 107 on the active surface 1131 of the grain, and At least a portion of the conductive filled vias 111 are electrically connected; in one embodiment, the conductive traces 125 extend along the surface of the protective layer 107 and the front surface of the plastic encapsulation layer 1231, and extend to the edge of the chip package when packaging is completed, and the package is molded The wafer structure is shown in Figure 15b. The conductive trace 125 extends to the edge of the package. At this time, the conductive trace 125 covers and connects the interface of the protective layer 107 and the plastic encapsulation layer 132, which increases the stability of the wafer structure after packaging.

The conductive trace 125 may be one or more layers of copper, gold, silver, tin, aluminum, or other materials or a combination thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating process , Or other suitable metal deposition process.

Preferably, the forming process of the conductive trace 125 and the filling process of the conductive filling via 111 are formed in the same metal layer forming process.

Of course, the forming process of the conductive trace 125 and the filling process of the conductive material of the conductive filling via 111 can also be performed in steps.

12 shows the formation of conductive studs 127 on the pads or connection points of the conductive traces 125; the shape of the conductive studs 127 may be round or other shapes such as ellipses, squares, lines, etc. . The conductive studs 127 may be one or more layers of copper, gold, silver, tin, aluminum and other materials or combinations thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating process , Or other suitable metal deposition process.

The panel-level conductive layer is composed of conductive traces 125 and/or conductive bumps 127, and the panel-level conductive layer may be one layer or multiple layers. The panel-level conductive layer may have a fan-out RDL function.

As shown in FIGS. 13a, 13b, and 13c, a dielectric layer 129 is formed on the panel-level conductive layer.

One or more dielectric layers 129 are formed on the surface of the panel-level conductive layer using suitable methods such as lamination, coating, spraying, printing, molding, and others.

The dielectric layer 129 may be BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide , Alumina, polymer matrix dielectric film, organic polymer film; can also be organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with filler, ABF, or have Other polymers with suitable fillers; other materials with similar insulation and structural properties. In a preferred embodiment, the secondary dielectric layer 129 is ABF. The dielectric layer 129 functions to protect the conductive layer and the insulation.

In one embodiment, the thickness applied by the dielectric layer 129 is thicker than the thickness of the panel-level conductive layer, and the panel-level conductive layer is exposed through the grinding process; in another embodiment, the thickness applied by the dielectric layer 133 and the panel-level The conductive layers have the same thickness, and the panel-level conductive layer is barely exposed after the dielectric layer 129 is applied.

In one embodiment, the steps of FIGS. 11 to 13c are repeated to form a multi-layer panel-level conductive layer on the grain active surface 1131 of the grain 113.

Return to the steps of FIGS. 11 to 13c again. In one embodiment, the steps of forming the panel-level conductive layer may be: Forming a conductive trace 125 on the grain active surface 1131 of the grain 113; Use suitable methods such as lamination, coating, spraying, printing, molding, and other methods to form one or more dielectric layers 129 on the surface of the conductive trace 125. The height of the dielectric layer 129 is higher than the height of the conductive trace 125. Trace 125 is completely enclosed in dielectric layer 129; and An opening is formed on the dielectric layer 129 at a position corresponding to the pad or connection point of the conductive trace 125, and a conductive stud 127 is formed in the opening.

In another embodiment, conductive bumps 127 may not be formed in the opening, so that the pads or connection points of the conductive traces 125 of the completed package are exposed from the opening.

In a preferred embodiment, after the step of applying the dielectric layer 129, the thickness of the outermost panel-level conductive layer is etched down to form a groove 131 on the outer surface of the dielectric layer 129. The chip structure of the package is shown in FIG. 15b As shown.

Optionally, as shown in FIG. 13c, multiple dies 113a and 113b, particularly two or more dies with different functions, can be packaged in a single packaging process, and two or more than two can be packaged in the figure. As a multi-chip package module, the patterned design of the conductive structures of multiple dies 113a and 113b is designed according to the electrical connection needs of the actual product. The packaged and molded wafer structure is shown in Figure 15d.

As shown in FIG. 14, the encapsulated monomer is cut and separated to form a packaged wafer, which can be cut by mechanical or laser.

15a, 15b, 15c, and 15d are schematic views of a chip packaging structure obtained according to a packaging method provided by an exemplary embodiment of the present disclosure. A chip packaging structure includes: at least one die 113, and the die 113 includes Grain active surface 1131 and grain back surface 1132; conductive structure formed on the side of the grain active surface 1131; protective layer 107 formed on the side of the grain active surface 1131; plastic encapsulation layer 123, the plastic encapsulation layer 123 is used to encapsulate the die 113; the dielectric layer 129.

In some embodiments, the conductive structure includes a wafer conductive layer 106, a conductive filled via 111 and a panel-level conductive layer 170; the conductive filled via 111 is formed in the protective layer 107.

In some embodiments, the die active surface 1131 includes an electrical connection point 103 and an insulating layer 105; a part or all of the wafer conductive layer 106 and a part or all of the electrical connection point 103 are electrically connected for A part or all of the electrical connection points 103 are drawn out from the die active surface 1131; the conductively filled via lower surface 111a and the wafer conductive layer 106 are electrically connected; the conductively filled via upper surface 111b and the panel The level conductive layer 170 is electrically connected.

In some embodiments, the panel-level conductive layer 170 includes conductive traces 125 and/or conductive bumps 127; the conductive bumps 127 are formed on pads or connection points of the conductive traces 125; the The dielectric layer 129 encapsulates the panel-level conductive layer 170; the panel-level conductive layer 170 is a layer.

Although not shown in the figure, the panel-level conductive layer may be multiple layers.

In some embodiments, the Young's modulus of the protective layer 107 is any one of the following numerical ranges or values: 1000~20000 MPa, 1000~10000 MPa, 4000~8000 MPa, 1000~7000 MPa, 4000~7000 MPa, 5500 MPa.

In some embodiments, the material of the protective layer 107 is an organic/inorganic composite material.

In some embodiments, the thickness of the protective layer 107 is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In some embodiments, the thermal expansion coefficient of the protective layer 107 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In some embodiments, the thermal expansion coefficient of the plastic encapsulation layer 123 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In some embodiments, the protective layer 107 and the plastic encapsulation layer 123 have the same or similar thermal expansion coefficients.

In some embodiments, the protective layer 107 includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

In some embodiments, the diameter of the inorganic filler particles is 1-2 μm.

In some embodiments, as shown in the enlarged view of FIG. 15a, the conductive filled via 111 has a conductive filled via lower surface 111a and a conductive filled via upper surface 111b, and the area of the conductive filled via lower surface 111a It is smaller than the area of the upper surface 111b of the conductive filled via.

In some embodiments, as shown in FIGS. 15a and 15b, at least a portion of the wafer conductive layer 106 interconnects and leads out a plurality of the electrical connection points 103 in at least a portion of the die active surface 1131 .

In some embodiments, as shown in FIG. 15c, at least a portion of the wafer conductive layer 106 leads at least a portion of the electrical connection point 103 on the active surface 1131 of the die to be separately extracted.

In some embodiments, as shown in a partially enlarged view in FIG. 15c, the contact area α2 of the single contact area of the wafer conductive layer 106 and the electrical connection point 103 is smaller than that of the wafer conductive layer 106 and the conductive The contact area β2 of the single contact area filling the through hole 111.

In some embodiments, as shown in FIG. 15b, at least a portion of the conductive trace 125 closest to the die active surface 1131 is formed on the front surface 1231 of the plastic encapsulation layer and extends to the edge of the package.

In some embodiments, as shown in FIG. 15b, the die back surface 1132 is exposed from the plastic encapsulation layer 123.

In some embodiments, as shown in FIG. 15b, the surface of the dielectric layer 129 has a groove at a position corresponding to the conductive layer.

In some embodiments, as shown in FIGS. 15 a, 15 b, and 15 c, the package structure includes a plurality of dies 113.

In some embodiments, as shown in FIG. 15d, the package structure includes a plurality of dies 113, and the plurality of dies 113 are electrically connected according to a product design.

Preferably, the plurality of dies 113 are dies with different functions to form a multi-chip module.

FIG. 16 shows a schematic diagram of a packaged wafer in use. During use, the packaged wafer is connected to a circuit board or substrate 161 by solder 160 and then connected to other circuit components.

When a groove 131 is formed on the surface of the dielectric layer 129 of the packaged chip, the solder 160 can be connected stably and not easily moved.

The specific embodiments described above are intended to further describe the technical solutions and technical effects of the present disclosure in detail, but those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the inventive idea of the present disclosure should be included in the protection scope of the present disclosure.

100‧‧‧ Wafer 1001‧‧‧wafer active surface 1002‧‧‧wafer back 103‧‧‧Electrical connection point 105‧‧‧Insulation 106‧‧‧wafer conductive layer 107‧‧‧Protective layer 109‧‧‧Protection layer opening 109a‧‧‧Lower surface of protective layer opening 109b‧‧‧The upper surface of the protective layer opening 109c‧‧‧Open side wall of protective layer 111‧‧‧Filled through hole 111a‧‧‧Lower surface of conductive filled via 111b‧‧‧Electrically filled via upper surface 113‧‧‧grain 113a‧‧‧grain 113b‧‧‧grain 1131‧‧‧ active surface 1132‧‧‧The back of the die 117‧‧‧ carrier board 1171‧‧‧Front of carrier board 1172‧‧‧Back of carrier board 121‧‧‧adhesive layer 123‧‧‧Plastic layer 1231‧‧‧Plastic layer front 1232‧‧‧Plastic back 125‧‧‧ conductive trace 127‧‧‧Conducting convex column 129‧‧‧dielectric layer 131‧‧‧groove 150‧‧‧Panel Module 160‧‧‧Solder 161‧‧‧ substrate 170‧‧‧Panel-level conductive layer

1 to 14 are flowcharts of a chip packaging method according to an exemplary embodiment of the present disclosure; FIG. 1 is a schematic diagram of a wafer according to an exemplary embodiment of the present disclosure; 2a and 2b are schematic diagrams of a wafer after forming a conductive layer of a wafer according to an exemplary embodiment of the present disclosure; 3 is a schematic diagram of a wafer after applying a protective layer according to an exemplary embodiment of the present disclosure; 4a and 4b are schematic diagrams of a wafer forming a protective layer opening according to an exemplary embodiment of the present disclosure; 5 is a schematic diagram of a wafer formed with conductive filled vias according to an exemplary embodiment of the present disclosure; 6 is a schematic diagram of cutting a wafer to form a die according to an exemplary embodiment of the present disclosure; 7a and 7b are schematic diagrams of mounting die on a carrier board according to an exemplary embodiment of the present disclosure; FIG. 7c is a schematic diagram of a die combination on a carrier board according to an exemplary embodiment of the present disclosure; 8 is a schematic diagram of forming a plastic encapsulation layer on a carrier board according to an exemplary embodiment of the present disclosure; 9a is a schematic diagram of reducing the thickness of a plastic encapsulation layer according to an exemplary embodiment of the present disclosure; 9b is a schematic diagram of thinning the plastic encapsulation layer to the exposed back side of the die according to an exemplary embodiment of the present disclosure; 10 is a schematic diagram of peeling off the carrier board and the adhesive layer according to an exemplary embodiment of the present disclosure; 11 is a schematic diagram of forming conductive filled vias and conductive traces on a panel module according to an exemplary embodiment of the present disclosure; 12 is a schematic diagram of forming conductive bumps on a panel module according to an exemplary embodiment of the present disclosure; 13a, 13b and 13c are schematic diagrams of forming a dielectric layer on a panel module according to an exemplary embodiment of the present disclosure; 14 is a schematic diagram of forming a packaged chip by dividing a panel module according to an exemplary embodiment of the present disclosure; 15a, 15b, 15c and 15d are schematic diagrams of a wafer packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure; 16 is a schematic diagram of a packaged wafer in use according to an exemplary embodiment of the present disclosure.

103‧‧‧Electrical connection point

105‧‧‧Insulation

106‧‧‧wafer conductive layer

107‧‧‧Protective layer

111‧‧‧Filled through hole

111a‧‧‧Lower surface of conductive filled via

111b‧‧‧Electrically filled via upper surface

113‧‧‧grain

1131‧‧‧ active surface

1132‧‧‧The back of the die

123‧‧‧Plastic layer

1231‧‧‧Plastic layer front

1232‧‧‧Plastic back

125‧‧‧ conductive trace

127‧‧‧Conducting convex column

129‧‧‧dielectric layer

170‧‧‧Panel-level conductive layer

Claims (19)

A chip packaging structure includes: At least one grain, the grain including a grain active surface and a grain back surface; A conductive structure formed on the side of the active surface of the grain; A protective layer formed on the side of the active surface of the crystal grain; A plastic encapsulation layer for encapsulating the die; and A dielectric layer. The chip packaging structure according to claim 1, the conductive structure includes a wafer conductive layer, a conductive filled via, and a panel-level conductive layer; the conductive filled via is formed in the protective layer. The chip packaging structure according to claim 2, wherein: The active surface of the grain includes an electrical connection point and an insulating layer; At least a portion of the wafer conductive layer and the electrical connection point are electrically connected for drawing the electrical connection point from the active surface of the die; At least a portion of the lower surface of the conductive filled via is electrically connected to the conductive layer of the wafer; and At least a portion of the upper surface of the conductive filled via is electrically connected to the panel-level conductive layer. According to the chip packaging structure of claim 3, at least a part of the wafer conductive layer interconnects and leads a plurality of the electrical connection points to each other. According to the chip packaging structure of claim 3, at least a part of the wafer conductive layer separates the electrical connection point. As described in claim 5, the contact area of the wafer conductive layer and the single contact area of the electrical connection point is smaller than the contact area of the wafer conductive layer and the single contact area of the conductive filled via. The chip packaging structure according to claim 3, wherein The panel-level conductive layer includes conductive traces and/or conductive bumps; The dielectric layer is wrapped around the panel-level conductive layer; and The panel-level conductive layer is one or more layers. According to the chip packaging structure of claim 7, at least a portion of the conductive trace closest to the active surface of the die is formed on the front surface of a plastic encapsulation layer and extends to the edge of a package body. According to the chip packaging structure of claim 3, the die back surface is exposed from the plastic encapsulation layer. As described in claim 3, the surface of the dielectric layer has a groove at a position corresponding to the panel-level conductive layer. The chip packaging structure according to any one of claims 1 to 10, the at least one die is a plurality of die, and the plurality of die are electrically connected according to a product design. The chip packaging structure according to any one of claims 1 to 10, the material of the protective layer is an organic/inorganic composite material. According to the chip packaging structure described in claim 12, the Young's modulus of the protective layer is any one of the following numerical ranges or values: 1000~20000 MPa, 1000~10000 MPa, 4000~8000 MPa, 5500 MPa. According to the chip packaging structure of claim 12, the thickness of the protective layer is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm. As described in claim 12, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K. According to the chip packaging structure described in claim 12, the thermal expansion coefficient of the plastic encapsulation layer is any one of the following numerical ranges or values: 3~10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K. According to the chip packaging structure of claim 12, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients. The wafer packaging structure according to claim 12, wherein the protective layer includes inorganic filler particles having a diameter of less than 3 μm or inorganic filler particles having a diameter of 1 to 2 μm. The chip packaging structure according to claim 12, the conductive filled via has a conductive filled via lower surface and a conductive filled via upper surface, the conductive filled via lower surface has a smaller area than the conductive filled via upper surface Area.

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