CN113725098B - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN113725098B
CN113725098B CN202010231971.2A CN202010231971A CN113725098B CN 113725098 B CN113725098 B CN 113725098B CN 202010231971 A CN202010231971 A CN 202010231971A CN 113725098 B CN113725098 B CN 113725098B
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die
layer
packaged
dielectric layer
encapsulation structure
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CN113725098A (en
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周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: providing an encapsulation structure encapsulating a first die to be packaged; forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged; forming a first dielectric layer, and fixing a second die to be packaged, the front surface of which is provided with a second protective layer, at a preset position on the first surface of the encapsulation structural member through the first dielectric layer; forming a second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure; a second dielectric layer is formed. The semiconductor packaging structure manufactured by the semiconductor packaging method has the advantages of small size and compact structure, and is suitable for small-sized light-weight electronic equipment.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor packaging method and a semiconductor packaging structure.
Background
Currently, in the packaging process, dies having different functions are often packaged in a package structure to form a specific function, which is called MCM (multi-chip module, chinese name). The MCM has the advantages of small volume, high reliability, high performance, multifunction and the like.
With miniaturization and weight reduction of electronic devices, chip packages having a compact structure and a small volume are increasingly favored in the market.
However, how to further reduce the volume of the chip package is a problem to be solved in the art.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, including:
providing an encapsulation structure member encapsulating a first die to be encapsulated, wherein a first protection layer is formed on the front surface of the first die to be encapsulated, and the first protection layer is exposed on the first surface of the encapsulation structure member;
forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged;
forming a first dielectric layer, wherein the first dielectric layer is formed on the first rewiring layer, the first surface of the encapsulation structure and the first protection layer of the first die to be packaged, and the second die to be packaged, the front surface of which is provided with a second protection layer, is fixed at a preset position on the first surface of the encapsulation structure through the first dielectric layer;
forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
And forming a second dielectric layer on a second protective layer formed on the second rewiring layer and the exposed first dielectric layer and the second die to be packaged.
Optionally, in forming a first dielectric layer, the first dielectric layer is formed on the first rewiring layer and the exposed first surface of the encapsulation structure and the first protective layer of the first die to be packaged, and the second die to be packaged with the second protective layer formed on the front surface is fixed in a predetermined position on the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
applying the first dielectric layer over the first rewiring layer and the exposed encapsulation structure and first protective layer of the first die to be packaged;
after preliminary heating the first dielectric layer, applying the second die to be packaged with the second protective layer formed on the front surface to a predetermined position on the first surface of the encapsulation structure through the first dielectric layer;
continuing to heat the first dielectric layer, the first dielectric layer being cured by heat, the second die to be packaged being cured to a predetermined location on the first surface of the encapsulation structure with the first dielectric layer.
Optionally, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees; the heating time is 1-4 hours, and the temperature is 190-200 ℃.
Optionally, in forming a first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method includes:
forming a first conductive trace on a first surface of an encapsulation structure encapsulating a first die to be packaged, the first conductive trace being electrically connected with a bond pad of a front side of the first die to be packaged;
a first conductive stud is formed on a side of the first conductive trace remote from the encapsulation structure.
Optionally, in forming a second rewiring layer on a side of the first dielectric layer away from the encapsulation structure, the semiconductor packaging method includes:
forming a second conductive trace on a surface of the first dielectric layer away from the encapsulation structure, wherein the second conductive trace is electrically connected with the first rewiring layer and a bonding pad on the front surface of the second die to be packaged;
and forming a second conductive convex column on one surface of the second conductive trace away from the first dielectric layer.
Optionally, in forming a second rewiring layer on a side of the first dielectric layer away from the encapsulation structure, the semiconductor packaging method includes:
The second conductive protruding columns are exposed on one surface of the second dielectric layer away from the first rewiring layer.
Optionally, before forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
forming a first protection layer on the front surface of a first die to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
mounting the first die to be packaged, the front surface of which is provided with the first protective layer, on a carrier plate, wherein the back surface of the first die to be packaged faces upwards, and the front surface of the first die to be packaged faces towards the carrier plate;
forming the encapsulation structural member by covering the first die to be encapsulated and the exposed carrier plate with an encapsulation layer;
and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first die to be packaged.
Optionally, in forming a first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method includes:
and filling a first conductive medium in the first protective layer opening.
Optionally, before the first die to be packaged with the first protective layer formed on the front surface is mounted on a carrier, the semiconductor packaging method includes:
And grinding the back surface of the first die to be packaged.
Optionally, before the second die to be packaged with the second protective layer formed on the front surface is fixed on the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
forming a second protection layer opening on the second protection layer, wherein the second protection layer opening is positioned at a welding pad of the second die to be packaged;
and filling a second conductive medium in the second protective layer opening so that the second conductive medium is electrically connected with the bonding pad on the front surface of the second die to be packaged.
Optionally, before the second die to be packaged with the second protective layer formed on the front surface is fixed on the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
and grinding the back surface of the second die to be packaged.
Another aspect of the present application provides a semiconductor package structure, including:
the packaging structure comprises a first surface and a second surface which are opposite, a plurality of first cavities are arranged in the first cavities, first bare chips with first protective layers formed on the front surfaces are positioned in the first cavities, the front surfaces of the first bare chips are exposed out of the first surface of the packaging structure, and the back surfaces of the first bare chips face to the bottoms of the first cavities;
A first rewiring layer located on the first surface of the encapsulation structure and the front side of the first die, the first rewiring layer being electrically connected with a bond pad of the front side of the first die;
a first dielectric layer formed on the first rewiring layer and the exposed first surface of the encapsulation structure and the first protection layer of the first bare chip, wherein the first dielectric layer is also provided with a plurality of second cavities which are concave, the second bare chip with the front surface provided with the second protection layer is positioned in the second cavities, and the back surface of the second bare chip faces to the bottom of the second cavities;
a second rewiring layer located on a side of the first dielectric layer away from the encapsulation structure, the second rewiring layer being electrically connected to both the first rewiring layer and the bonding pads on the front side of the second die;
and a second dielectric layer formed on the second rewiring layer and the exposed second protective layer of the first dielectric layer and the second die.
Optionally, the thickness of the second die is less than the thickness of the encapsulation structure.
Optionally, a side of the second protective layer remote from the second die is flush with a side of the first dielectric layer remote from the encapsulation structure.
According to the semiconductor packaging method and the semiconductor packaging structure, the first die to be packaged with a certain function is firstly routed through the mode of packaging and forming the conducting layer, and then the second die to be packaged is fixed on the first surface of the packaging structural member through the first dielectric layer, so that the space between the first die to be packaged and the second die to be packaged is reduced, the structure of the formed semiconductor packaging structure is compact, the beneficial effect of reducing the whole occupied space is achieved, and on the other hand, the second die is directly fixed on the first surface of the packaging structural member through the first dielectric layer, the first die is prevented from being fixed through the bonding layer, the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further achieved; the semiconductor packaging structure has the advantages of small size and compact structure, and is suitable for small-sized light-weight electronic equipment.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 2 (a) -2 (v) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by using the above-described semiconductor packaging method according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "a" or "an" and the like as used in the description and the claims do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper" and/or "lower" and the like are used for ease of description only and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
As shown in fig. 1, 2 (a) -2 (v) and 3, the present application provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: providing an encapsulation structure member encapsulating a first die to be encapsulated, wherein a first protection layer is formed on the front surface of the first die to be encapsulated, and the first protection layer is exposed on the first surface of the encapsulation structure member;
step 102: forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged;
step 103: forming a first dielectric layer, wherein the first dielectric layer is formed on the first rewiring layer, the first surface of the encapsulation structure and the first protection layer of the first die to be packaged, and the second die to be packaged, the front surface of which is provided with a second protection layer, is fixed at a preset position on the first surface of the encapsulation structure through the first dielectric layer;
step 104: forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
Step 105: and forming a second dielectric layer on a second protective layer formed on the second rewiring layer and the exposed first dielectric layer and the second die to be packaged.
According to the semiconductor packaging method and the semiconductor packaging structure, the first die to be packaged with a certain function is firstly routed once in a manner of packaging and forming the conducting layer, and then the second die to be packaged is fixed on the first surface of the packaging structural member through the first dielectric layer, so that the space between the first die to be packaged and the second die to be packaged is reduced, the structure of the formed semiconductor packaging structure is more compact, the beneficial effect of reducing the whole occupied space is achieved, and on the other hand, the second die is directly fixed on the first surface of the packaging structural member through the first dielectric layer, the first die is prevented from being fixed through the bonding layer, the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further achieved; the semiconductor packaging structure has the advantages of small size and compact structure, and is suitable for small-sized light-weight electronic equipment.
In this embodiment, in step 101, the semiconductor packaging method includes:
step 1011: forming a first protection layer on the front surface of a first die to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
step 1012: mounting the first die to be packaged, the front surface of which is provided with the first protective layer, on a carrier plate, wherein the back surface of the first die to be packaged faces upwards, and the front surface of the first die to be packaged faces towards the carrier plate;
step 1013: forming the encapsulation structural member by covering the first die to be encapsulated and the exposed carrier plate with an encapsulation layer;
step 1014: and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first die to be packaged.
In step 1011, a first protection layer is formed on the front surface of the first die to be packaged, and the first protection layer may be formed on the front surface of the first semiconductor wafer before the first semiconductor wafer is cut into a plurality of first dies to be packaged, and then the first semiconductor wafer is cut to obtain the first die to be packaged with the first protection layer formed on the front surface. It will be understood, of course, that the first semiconductor wafer may be cut into first dies to be packaged, and then a first protective layer may be formed on the front surface of each first die to be packaged, as the process allows, which is specifically selected according to the actual situation.
As shown in fig. 2 (a), the front surface of the first semiconductor wafer 100, that is, the front surface corresponding to the first die 201 to be packaged, has a first insulating layer 2011 and a first bonding pad 2012, and the first bonding pad 2012 is used for electrically connecting with the outside. The front side of the first die 201 to be packaged is the active side of the first die 201 to be packaged.
As shown in fig. 2 (b), a first protection layer 202 is formed on the front surface of the first semiconductor wafer 100, i.e., the front surface corresponding to the first die 201 to be packaged.
The first protective layer 202 is made of one or more of insulating materials such as polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like. Optionally, the material of the protective layer is selected to be insulating and capable of accommodating materials for chemical cleaning, polishing, etc. The first protective layer 202 may be formed on the first semiconductor wafer by Lamination (Coating), coating (Printing), printing (Printing), or the like. The temperature, pressure and time ranges are different according to the materials, and the curing conditions of different materials are different.
Next, as shown in fig. 2 (c), after the step of forming the first protective layer 202 is completed, the back surface of the first semiconductor wafer 100, that is, the back surface corresponding to the first die 201 to be packaged, is polished to thin the thickness of the first die 201 to be packaged, thereby thinning the thickness of the final overall packaging structure, and further realizing the beneficial effect of reducing the overall occupied space.
Then, as shown in fig. 2 (d), the first semiconductor wafer 100 with the first protection layer 202 formed thereon is cut along the scribe line, so as to obtain a plurality of first dies to be packaged 201 with the first protection layer 202 formed thereon. The cutting process may be mechanical cutting or laser cutting.
The first die 201 to be packaged with the first protective layer 202 is shown in fig. 2 (e), where the front surface of the first die 201 to be packaged still has the first insulating layer and the first bonding pad, but they are not labeled in the figure for convenience of subsequent process flow. The first die 201 to be packaged formed through the above steps is a die to be packaged having a specific function.
Next, as shown in fig. 2 (f), first protection layer openings 2021 are formed on the first protection layer 202 at positions corresponding to the bonding pads of the first die 201 to be packaged, and each first protection layer opening 2021 is at least corresponding to the bonding pads of the first die 201 to be packaged or the wires led out from the bonding pads, so that the bonding pads on the front surface of the first die 201 to be packaged or the wires led out from the bonding pads are exposed from the first protection layer opening 2021.
If the first protective layer 202 material is a laser reactive material, the first protective layer opening 2021 may be formed in a laser patterning manner; if the first protective layer 202 material is a photosensitive material, then the first protective layer opening 2021 may be formed using photolithographic patterning. The shape of the first protection layer opening 2021 may be round, but may be other shapes such as oval, square, line, etc.
In this embodiment, since the first protection layer opening 2021 is already formed on the first protection layer 202, at least the first protection layer opening 2021 can be directly seen when the first rewiring layer is subsequently formed, so that the first rewiring layer can be more accurately aligned when the first rewiring layer is formed.
Also, the steps of forming a second protective layer on the front side of the second die to be packaged and forming a second protective layer opening on the second protective layer are substantially the same as the steps of forming a first protective layer on the front side of the first die to be packaged and forming a first protective layer opening on the first protective layer. The specific content is as follows:
the second protection layer may be formed on the front surface of the second semiconductor wafer before dicing the second semiconductor wafer into a plurality of second dies to be packaged, and then dicing the second semiconductor wafer to obtain the second dies to be packaged with the second protection layer formed on the front surface. It will be understood, of course, that the second semiconductor wafer may be cut into second dies to be packaged, and then a second protective layer may be formed on the front surface of each second die to be packaged, as the process allows, and this is specifically selected according to the actual situation.
As shown in fig. 2 (g), the front surface of the second semiconductor wafer 100', i.e., the front surface corresponding to the second die 201' to be packaged, has a second insulating layer 2011' and a second pad 2012', and the second pad 2012' is for electrical connection with the outside. The front side of the second die 201 'to be packaged, i.e., the active side of the second die 201' to be packaged.
As shown in fig. 2 (h), a second protection layer 202' is formed on the front surface of the second semiconductor wafer 100', i.e., the front surface corresponding to the second die 201' to be packaged. The material of the second protection layer 202 'is the same as that of the first protection layer 202, and the description of the material of the first protection layer 202 is equally applicable to the material of the second protection layer 202', which will not be described again.
Next, as shown in fig. 2 (i), the back surface of the second semiconductor wafer 100', i.e., the back surface corresponding to the second die 201' to be packaged, is polished to thin the thickness of the second die 201' to be packaged, thereby thinning the thickness of the final overall package structure, and further realizing the beneficial effect of reducing the overall occupied space.
As shown in fig. 2 (j), the second semiconductor wafer 100 'is cut along the scribe lines to obtain a plurality of second dies 201' to be packaged. The cutting process may be mechanical cutting or laser cutting.
The structure of the formed second die 201 'to be packaged is shown in fig. 2 (k), in which the front surface of the second die 201' to be packaged still has the second insulating layer and the second bonding pad, but they are not labeled in the figure for convenience of subsequent process flow.
As shown in fig. 2 (l), second protection layer openings 2021' are formed on the second protection layer 202' at positions corresponding to the bonding pads of the second die 201' to be packaged, and each second protection layer opening 2021' is located at least corresponding to the bonding pads of the second die 201' to be packaged or the wires led out from the bonding pads, so that the bonding pads on the front surface of the second die 201' to be packaged or the wires led out from the bonding pads are exposed from the second protection layer opening 2021 '.
As shown in fig. 2 (m), the second protective layer opening 2021 'is filled with a second conductive medium 203' so that the second conductive medium 203 'is electrically connected to the bonding pad of the second die 201' to be packaged, and the second conductive medium 203 'forms a vertical connection structure in the second protective layer opening 2021' so that the bonding pad on the surface of the second die 201 'to be packaged is electrically connected to the second rewiring layer formed in a subsequent step through the connection structure in the second conductive medium 203'.
In some embodiments, the second conductive medium may not be filled in the second protection layer openings, so that after the second die to be packaged with the second protection layer is fixed at a predetermined position on the first surface of the encapsulation structure through the first dielectric layer, the plurality of second protection layer openings are still in a hollow state.
In step 1012, as shown in fig. 2 (n), the first die 201 to be packaged with the first protective layer 202 formed on the front surface is attached to the carrier 300 through an adhesive layer (not labeled in the figure), and the back surface of the first die 201 to be packaged faces upward, and the front surface faces the carrier 300.
The adhesive layer is used for bonding the first die to be packaged, and the adhesive layer can be made of a material which is easy to peel, so that the carrier plate and the first die to be packaged can be peeled off in a subsequent process, for example, a thermal separation material which can lose adhesiveness through heating can be used.
In other embodiments, the bonding layer may be a two-layer structure, where the thermally-separable material layer and the die attach layer are adhered to the carrier, and the thermally-separable material layer loses adhesion when heated, and is then peeled off from the carrier, and the die attach layer is an adhesive material layer and may be used to adhere the first die to be packaged. And after the first die to be packaged is peeled off from the carrier plate, the die attaching layer on the first die to be packaged can be removed by a chemical cleaning mode. In one embodiment, the adhesive layer may be formed on the carrier plate by lamination, printing, or the like.
As shown in fig. 2 (n), the first die 201 to be packaged is placed on the carrier 300 according to a predetermined arrangement position, and for convenience of illustration, only one first die 201 to be packaged is shown in the figure, and in fact, a plurality of first dies 201 to be packaged are arranged on the carrier 300 according to a predetermined position.
It can be understood that in the one-time packaging process, the number of the first die 201 to be packaged may be plural, that is, plural first dies 201 to be packaged are simultaneously mounted on the carrier 300, packaged, and then cut into plural packages after the packaging is completed; one package may include one or more first dies to be packaged 201, and the positions of the one or more first dies to be packaged 201 may be freely set according to the needs of an actual product.
In step 1013, as shown in fig. 2 (o), an encapsulation structure 200 is formed by covering the first die 201 to be encapsulated and the exposed carrier 300 with an encapsulation layer 204. The encapsulation structure 200 is a flat structure on which rewiring and packaging can continue after the carrier 300 is peeled off.
In one embodiment, the encapsulation layer 204 may be formed by laminating an epoxy film or ABF (Ajinomoto buildup film), or may be formed by injection molding (Injection molding), compression molding (Compression molding), or Transfer molding (Transfer molding) an epoxy compound.
When encapsulating with the encapsulation layer 204, the encapsulation material easily penetrates between the carrier 300 and the first die 201 to be encapsulated during this process, since the encapsulation layer requires high pressure molding at the time of molding. Through the embodiment of the application, a first protective layer 202 is formed outside the first die 201 to be packaged, the first protective layer 202 can prevent the encapsulation material from penetrating to the surface of the first die 201 to be packaged, and even if the encapsulation material penetrates, after being peeled off from the carrier plate, the surface of the first protective layer 202 can be directly processed by a chemical method or a grinding method, and the front surface of the first die 201 to be packaged cannot be directly contacted, so that the circuit structure of the front surface of the first die 201 to be packaged cannot be damaged.
The encapsulation structure 200 includes a first surface 2001 and a second surface 2002 disposed opposite to each other, and the second surface 2002 is disposed opposite to the carrier 300, substantially flat, and parallel to the surface of the carrier 300.
In other embodiments, the thickness of the encapsulation structure 200 may be reduced by grinding or polishing the second surface 2002. In an alternative embodiment, the thickness of the encapsulation structure 200 may be reduced to the back of the first die 201 to be packaged, and the overall volume of the final semiconductor package may be further reduced by reducing the thickness of the encapsulation structure 200.
In step 1014, as shown in fig. 2 (p), the carrier plate 300 is peeled off, exposing the first surface 2001 of the encapsulation structure 200 with the front side of the first die 201 to be packaged.
Since the adhesive layer between the carrier 300 and the first die 201 to be packaged is a thermal separation film, the adhesive layer can be reduced in viscosity after being heated by heating, so as to peel off the carrier 300. By peeling the carrier 300 by heating the adhesive layer, damage to the first die 201 to be packaged during peeling can be minimized. In other embodiments, the carrier plate 300 may also be peeled off directly mechanically.
After the carrier 300 is peeled off, the first surface 2001 of the encapsulation structure 200 facing the carrier 300, the front surface of the first die 201 to be packaged, is exposed. After the carrier 300 is peeled off, an encapsulation structure 200 is obtained that includes the first die 201 to be encapsulated, the first protective layer 202 covering the front surface of the first die 201 to be encapsulated, and the encapsulation layer 204 encapsulating the first die 201 to be encapsulated, as shown in fig. 2 (q). On the encapsulation structure 200 formed, rewiring or the like may be performed according to actual circumstances, so that the first die 201 to be packaged is electrically connected to the outside.
In the embodiment of the present application, after the carrier 300 is peeled off, the surfaces of the first protection layer 202 and the surface of the first protection layer 202 are exposed, and at this time, the die attach layer in the adhesive layer is still present on the surface of the first protection layer 202, and when removed by a chemical manner, the surface of the first protection layer 202 can also protect the surface of the first die 201 to be packaged from being damaged. After the bonding layer is completely removed, if the encapsulating material is permeated before, the surface can be leveled by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the first protective layer 202, the surface of the first die 201 to be packaged cannot be treated chemically or by polishing, so as not to damage the circuit on the front side of the first die 201 to be packaged.
In step 102, as shown in fig. 2 (r), a first rewiring layer 206 is formed on the first surface 2001 of the encapsulation structure 200, the first rewiring layer 206 being electrically connected with the pads of the front side of the first die 201 to be packaged. Specifically, the method comprises the following steps:
step 1021: forming a first conductive trace 2061 on the first surface 2001 of the encapsulation structure 200 encapsulating the first die 201 to be packaged, the first conductive trace 2061 being electrically connected to a bonding pad of the front side of the first die 201 to be packaged;
Step 1022: a first conductive stud 2062 is formed on a side of the first conductive trace 2061 remote from the encapsulation structure 200.
In step 1021, the first conductive trace 2061 is electrically connected to the pad of the first die 201 to be packaged through the first protection layer opening 2021.
In this case, since the first protective layer opening 2021 is already formed on the first protective layer 202, at least the protective layer opening 2021 can be directly seen when the first rewiring layer 206 is formed, and thus the first rewiring layer 206 can be more accurately aligned.
In forming the first conductive trace 2061, the first conductive medium 203 may be filled within the first protective layer opening 2021 of the first die 201 to be packaged at the same time, i.e., the first conductive trace and the first conductive medium are formed in the same conductive layer forming process. The first conductive medium 203 forms a vertical connection structure in the first protection layer opening 2021, such that the bonding pad on the surface of the first die 201 to be packaged is electrically connected to the first rewiring layer 206 through the connection structure in the first conductive medium 203.
In step 1022, the shape of the first conductive bump 2062 is preferably circular, but may be rectangular, square, or other shapes, and the first conductive bump 2062 is electrically connected to the first conductive trace 2061. Specifically, the first conductive stud 2062 may be formed on the first conductive trace 2061 by photolithography and electroplating.
In another embodiment, a first dielectric layer may be formed on the first surface 2001 of the encapsulation structure 200 and the exposed first protective layer 202 and the first conductive trace 2061 after forming the first conductive trace 2061, and the first dielectric layer has a first opening, and then forming a first conductive stud 2062 electrically connected with the first conductive trace 2061 in the first opening of the first dielectric layer. In this process, the first rewiring layer 206 includes the first conductive trace 2061 and the first conductive stud 2062.
In yet another embodiment, the first opening of the first conductive trace may also be left unfilled, i.e., the first conductive stud 2062 electrically connected to the first conductive trace 2061 is not formed, such that the bond pad or connection point of the first rewiring layer of the completed package is exposed from the first opening. In this process, the first rewiring layer 206 comprises only the first conductive trace 2061.
In step 103, as shown in fig. 2(s), a first dielectric layer 207 is formed, the first dielectric layer 207 is formed on the first rewiring layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protective layer 202 of the first die 201 to be packaged, and the second die 201 'to be packaged having the second protective layer 202' formed on the front side is fixed at a predetermined position on the first surface 2001 of the encapsulation structure 200 through the first dielectric layer 207. Specifically, the method comprises the following steps:
Step 1031: a first dielectric layer 207 is applied over the first rewiring layer 206 and the exposed first surface 2001 of the encapsulation structure 200 and the first protective layer 202 of the first die 201 to be packaged. The first dielectric layer 207 is made of an insulating material such as one or more of polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like. The first dielectric layer 207 may be formed by Lamination (Lamination), molding (Molding), or Printing (Printing), and preferably an epoxy compound is used.
Step 1031: after the first dielectric layer 207 is initially heated, a second die 201 'to be packaged having a second protective layer 202' formed on the front side is applied to a predetermined location on the first surface 2001 of the encapsulation structure 200 through the first dielectric layer 207. Since the viscosity of the primarily heated first dielectric layer 207 is first reduced and the first dielectric layer 207 at this time has a strong fluidity, the second die 201 'to be packaged is placed at a predetermined position on the first surface 2001 of the encapsulation structure 200, and the back surface of the second die 201' to be packaged is directed toward the first surface 2001 of the encapsulation structure 200, and the primarily heated first dielectric layer 207 originally between the first surface 2001 of the encapsulation structure 200 and the second die 201 'to be packaged can be squeezed away and around the second die 201' to be packaged by applying pressure.
Step 1033: continuing to heat the first dielectric layer 207, as the heating proceeds, the first dielectric layer 207 is cured by heat, and the second die 201' to be packaged is brought into close proximity with the first surface 2001 of the encapsulation structure 200 as the first dielectric layer 207 cures to a predetermined location on the first surface 2001 of the encapsulation structure 200.
It should be noted that the time and temperature of the preliminary heating are determined according to the specific kind of the material of the first dielectric layer 207, and general rules are as follows: the temperature of the preliminary heating is below the curing temperature of the material of the first dielectric layer 207.
The viscosity of the material of the first dielectric layer 207 decreases due to an increase in temperature, which increases the viscosity by cross-linking between molecules of the material of the first dielectric layer 207 when the temperature is increased above the curing temperature, which is chosen to be below and controllable below the curing temperature, according to the rheological characteristics of the material of the first dielectric layer 207 during curing.
After the second die 201 'to be encapsulated having the second protective layer 202' formed on the front surface is applied to the first surface 2001 of the encapsulation structure 200, the temperature may be raised to or above the curing temperature of the material of the first dielectric layer 207, the curing thermodynamic characteristics of the different materials being different, the specific heating time being determined from the curing thermodynamic data of the material, the heating temperature being a temperature above the curing temperature, the heating time being the time for the first dielectric layer 207 to fully cure corresponding to the heating temperature, generally the shorter the time required for the higher heating temperature for the material to fully crosslink, i.e. the shorter the curing time.
In this embodiment, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees. The heating time is 1-4 hours, and the temperature is 190-200 ℃.
As shown in fig. 2(s), a surface of the second protection layer 202 'away from the second die 201' to be packaged is flush with a surface of the first dielectric layer 207 away from the first die 201 to be packaged, so as to ensure that the connection is formed on a plane when the first rewiring layer 206 is formed.
As can be seen from the above, the step of fixing the second die 201' to be packaged to a predetermined position on the first surface 2001 of the encapsulation structure 200 and the step of forming the first dielectric layer 207 on the first surface 2001 of the encapsulation structure 200 are performed simultaneously.
In step 104, as shown in fig. 2 (t), a second rewiring layer 208 is formed on a side of the first dielectric layer 207 remote from the encapsulation structure 200, and the second rewiring layer 208 is electrically connected to both the first rewiring layer 206 and the pads of the front side of the second die 201' to be packaged. Specifically, the method comprises the following steps:
step 1041: forming a second conductive trace 2081 on a surface of the first dielectric layer 207 away from the encapsulation structure 200, wherein the second conductive trace 2081 is electrically connected to the first rewiring layer 206 and the bonding pad on the front surface of the second die 201' to be packaged;
Step 1042: a second conductive stud 2082 is formed on a side of the second conductive trace 2081 away from the first dielectric layer 207.
In step 1041, the second conductive trace 2081 is electrically connected to the pad on the front side of the second die 201 'to be packaged, and the second conductive trace 2081 is electrically connected to the pad of the second die 201' to be packaged through the second conductive medium 203 'in the second passivation layer opening 2021'.
In this embodiment, since the second conductive medium 203' is already formed in the second passivation layer opening 2021', at least the second conductive medium 203' can be directly seen when the second conductive trace 2081 is formed, and thus the second conductive trace 2081 can be more accurately aligned when formed.
In some embodiments, where the second conductive medium is not filled in the second protective layer opening before the second die to be packaged with the second protective layer formed on the front side is fixed to the first surface of the encapsulation structure by the first dielectric layer, the second conductive medium may be filled in the second protective layer opening of the second die to be packaged at the same time when the second conductive trace is formed, i.e., the second conductive trace and the second conductive medium are formed in the same conductive layer forming process.
In step 1042, the shape of the second conductive stud 2082 is preferably circular, but it can be rectangular, square, etc., and the second conductive stud 2082 is electrically connected to the second conductive trace 2081. Specifically, the second conductive stud 2082 may be formed on the second conductive trace 2081 by photolithography and electroplating.
In another embodiment, a second dielectric layer may be formed on the second conductive trace 2081 and the exposed second passivation layer 202' and the first dielectric layer after the second conductive trace 2081, and the second dielectric layer has a second opening, and then a second conductive stud 2082 electrically connected to the second conductive trace 2081 is formed in the second opening of the second dielectric layer. In this process, the second rewiring layer 208 includes the second conductive trace 2081 and the second conductive stud 2082.
In yet another embodiment, the second openings of the second conductive traces may also be left unfilled, i.e., the second conductive studs 2082 electrically connected to the second conductive traces 2081 are not formed, so that the pads or connection points of the second rewiring layer of the completed package are exposed from the second openings. In this process, the second rewiring layer 208 comprises only the second conductive trace 2081.
In step 105, as shown in fig. 2 (u), a second dielectric layer 209 is formed on the second protective layer 202 'formed on the second rewiring layer 208 and the exposed first dielectric layer 207 and second die 201' to be packaged.
The material of the second dielectric layer 209 is the same as that of the first dielectric layer 207, and will not be described again.
In order to expose the second conductive stud 2082 on a surface of the second dielectric layer 209 away from the first rewiring layer 206, the thickness of the second dielectric layer 209 may be the thickness of the surface of the second conductive stud 2082 that is just exposed; the second dielectric layer 209 may also cover all exposed surfaces of the first dielectric layer 207 and the second rewiring layer 208, and then be thinned to the surface of the second conductive stud 2082. In this process, the second rewiring layer 208 includes the second conductive trace 2081 and the second conductive stud 2082.
The first rewiring layer 206, the first dielectric layer 207, the second rewiring layer 208 and the second dielectric layer 209 all belong to a rewiring structure.
Further, in an embodiment, repeated rewiring may be performed on the front sides of the first die and the second die, such as a third rewiring layer or layers may be formed outside the second dielectric layer in the same manner to achieve a multi-layer rewiring structure of the product.
Next, as shown in fig. 2 (v), after the package of the rewiring structure is completed, the entire package structure is cut into a plurality of packages, that is, a plurality of semiconductor package structures, by laser or mechanical cutting. The structure of the semiconductor package formed is shown in fig. 3.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present application. The semiconductor package structure includes: an encapsulation structure 200 encapsulating a first die 201, a first rewiring layer 206, a first dielectric layer 207 with a second die 201' affixed thereto, a second rewiring layer 208, and a second dielectric layer 209. Wherein the first rewiring layer 206, the first dielectric layer 207, the second rewiring layer 208 and the second dielectric layer 209 all belong to a rewiring structure, that is, the second die 201 'is fixed on the first surface 2001 of the encapsulation structure 200 during the process of forming the rewiring structure on the first surface 2001 of the encapsulation structure 200, and the rewiring structure is electrically connected with both the first die 201 and the second die 201'.
The envelope structure 200 comprises opposing first and second surfaces 2001, 2002, the envelope structure 200 being provided with a plurality of first cavities recessed therein. A first die 201 with a first protective layer 202 formed on the front surface is located within the first cavity. The front side of the first die 201 is exposed at the first surface 2001 of the encapsulation structure 200, and the back side of the first die 201 faces the bottom of the first cavity.
The first rewiring layer 206 is located on the first surface 2001 of the encapsulation structure 200 and the front side of the first die 201, the first rewiring layer 206 being electrically connected with the pads of the front side of the first die 201. Specifically, the first rewiring layer 206 includes a first conductive trace 2061 and a first conductive stud 2062. A first conductive trace 2061 is formed on the first surface 2001 of the encapsulation structure 200, the first conductive trace 2061 being electrically connected with a bond pad of the front side of the first die 201, in particular, the first conductive trace 2061 being electrically connected with a bond pad of the first die 201 through the second conductive medium 203 in the first protective layer opening 2021. A first conductive stud 2062 is formed on a side of the first conductive trace 2061 remote from the encapsulation structure 200.
The first dielectric layer 207 is formed on the first rewiring layer 206 and the exposed first surface 2001 of the encapsulation structure 200 and the first protection layer 202 of the first die 201, the first dielectric layer 207 is further provided with a plurality of concave second cavities, the second die 201' with the second protection layer 202' formed on the front surface is located in the second cavities, and the back surface of the second die 201' faces the bottom of the second cavities.
The second rewiring layer 208 is located on a side of the first dielectric layer 207 remote from the encapsulation structure 200, and the second rewiring layer 208 is electrically connected to both the first rewiring layer 206 and the bonding pads on the front side of the second die 201'. Specifically, the second rewiring layer 208 includes a second conductive trace 2081 and a second conductive stud 2082. Second conductive trace 2081 is formed on a side of first dielectric layer 207 remote from encapsulation structure 200, second conductive trace 2081 is electrically connected to a pad on the front side of second die 201', and second conductive trace 2081 is electrically connected to a pad of second die 201' through second conductive medium 203 'in second cap opening 2021'. The first conductive stud 2062 is formed on a side of the second conductive trace 2081 remote from the first dielectric layer 207.
A second dielectric layer 209 is formed over the second rewiring layer 208 and the exposed first dielectric layer 207 and second protective layer 202 'of the second die 201'.
In this way, in the semiconductor packaging structure of the embodiment, the first die with a certain function is firstly routed once in a manner of packaging and forming the conductive layer, and then the second die is fixed on the first surface of the packaging structural member through the first dielectric layer, so that on one hand, the space between the first die and the second die is reduced, the structure of the formed semiconductor packaging structure is more compact, the beneficial effect of reducing the whole occupied space is realized, on the other hand, the second die is directly fixed on the first surface of the packaging structural member through the first dielectric layer, the first die is prevented from being fixed through the adhesive layer, and therefore the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further realized; the semiconductor packaging structure has the advantages of small size and compact structure, and is suitable for small-sized light-weight electronic equipment.
In another embodiment, the rewiring structure comprises a plurality of rewiring layers to achieve multi-layer rewiring of a product.
In this embodiment, the thickness H1 of the second die 201' is less than the thickness H1 of the encapsulation structure 200. Since the second die 201' is secured to the encapsulation structure 200 by the first dielectric layer 207 during fabrication, the thickness H1 of the second die 201' is set to be less than the thickness H1 of the encapsulation structure 200 to enable the encapsulation structure 200 to provide better support when the second die 201' is secured to the encapsulation structure 200 by the first dielectric layer 207. In addition, the occupied space of the whole packaging structure is reduced.
The side of the second protective layer 202 'remote from the second die 201' is flush with the side of the first dielectric layer 207 remote from the encapsulation structure 200 to provide a flat base surface for the next step in the fabrication process to form the second rewiring layer 208 to improve the performance of the final semiconductor package.
In this application, the apparatus embodiments and method embodiments may complement each other without conflict.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (14)

1. A method of packaging a semiconductor, comprising:
providing an encapsulation structure member encapsulating a first die to be encapsulated, wherein a first protection layer is formed on the front surface of the first die to be encapsulated, and the first protection layer is exposed on the first surface of the encapsulation structure member;
forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged;
forming a first dielectric layer, wherein the first dielectric layer is formed on the first rewiring layer, the first surface of the encapsulation structure and the first protection layer of the first die to be packaged, the second die to be packaged, the front surface of which is formed with a second protection layer, is fixed at a preset position on the first surface of the encapsulation structure through the first dielectric layer, and the first rewiring layer penetrates through the first dielectric layer;
forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
and forming a second dielectric layer on a second protective layer formed on the second rewiring layer and the exposed first dielectric layer and the second die to be packaged.
2. The semiconductor packaging method according to claim 1, wherein, in forming a first dielectric layer formed on the first rewiring layer and the exposed first surface of the encapsulation structure and a first protective layer of the first die to be packaged, and fixing a second die to be packaged having a second protective layer formed on a front surface thereof in a predetermined position on the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method comprises:
applying the first dielectric layer over the first rewiring layer and the exposed encapsulation structure and first protective layer of the first die to be packaged;
after preliminary heating the first dielectric layer, applying the second die to be packaged with the second protective layer formed on the front surface to a predetermined position on the first surface of the encapsulation structure through the first dielectric layer;
continuing to heat the first dielectric layer, the first dielectric layer being cured by heat, the second die to be packaged being cured to a predetermined location on the first surface of the encapsulation structure with the first dielectric layer.
3. The semiconductor packaging method according to claim 2, wherein the preliminary heating time is 30 seconds to 60 seconds and the temperature is 80 degrees to 120 degrees; the heating time is 1-4 hours, and the temperature is 190-200 ℃.
4. The semiconductor packaging method of claim 1, wherein in forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
forming a first conductive trace on a first surface of an encapsulation structure encapsulating a first die to be packaged, the first conductive trace being electrically connected with a bond pad of a front side of the first die to be packaged;
a first conductive stud is formed on a side of the first conductive trace remote from the encapsulation structure.
5. The semiconductor packaging method of claim 1, wherein in forming a second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure, the semiconductor packaging method comprises:
forming a second conductive trace on a surface of the first dielectric layer away from the encapsulation structure, wherein the second conductive trace is electrically connected with the first rewiring layer and a bonding pad on the front surface of the second die to be packaged;
and forming a second conductive convex column on one surface of the second conductive trace away from the first dielectric layer.
6. The semiconductor packaging method of claim 5, wherein in forming a second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure, the semiconductor packaging method comprises:
The second conductive protruding columns are exposed on one surface of the second dielectric layer away from the first rewiring layer.
7. The semiconductor packaging method of claim 1, wherein prior to forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
forming a first protection layer on the front surface of a first die to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
mounting the first die to be packaged, the front surface of which is provided with the first protective layer, on a carrier plate, wherein the back surface of the first die to be packaged faces upwards, and the front surface of the first die to be packaged faces towards the carrier plate;
forming the encapsulation structural member by covering the first die to be encapsulated and the exposed carrier plate with an encapsulation layer;
and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first die to be packaged.
8. The semiconductor packaging method of claim 7, wherein in forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
And filling a first conductive medium in the first protective layer opening.
9. The semiconductor packaging method according to claim 7, characterized in that before the first die to be packaged having the first protective layer formed on the front surface is mounted on a carrier, the semiconductor packaging method comprises:
and grinding the back surface of the first die to be packaged.
10. The semiconductor packaging method according to claim 1, wherein before the second die to be packaged having the second protective layer formed on the front surface is fixed on the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method comprises:
forming a second protection layer opening on the second protection layer, wherein the second protection layer opening is positioned at a welding pad of the second die to be packaged;
and filling a second conductive medium in the second protective layer opening so that the second conductive medium is electrically connected with the bonding pad on the front surface of the second die to be packaged.
11. The semiconductor packaging method according to claim 1, wherein before the second die to be packaged having the second protective layer formed on the front surface is fixed on the first surface of the encapsulating structure through the first dielectric layer, the semiconductor packaging method comprises:
And grinding the back surface of the second die to be packaged.
12. A semiconductor package structure, comprising:
the packaging structure comprises a first surface and a second surface which are opposite, a plurality of first cavities are arranged in the first cavities, first bare chips with first protective layers formed on the front surfaces are positioned in the first cavities, the front surfaces of the first bare chips are exposed out of the first surface of the packaging structure, and the back surfaces of the first bare chips face to the bottoms of the first cavities;
a first rewiring layer located on the first surface of the encapsulation structure and the front side of the first die, the first rewiring layer being electrically connected with a bond pad of the front side of the first die;
a first dielectric layer formed on the first rewiring layer and the exposed first surface of the encapsulation structure and the first protection layer of the first bare chip, wherein the first dielectric layer is also provided with a plurality of second cavities which are concave, the second bare chip with the front surface provided with the second protection layer is positioned in the second cavities, and the back surface of the second bare chip faces to the bottom of the second cavities; and the first rewiring layer penetrates through the first dielectric layer;
a second rewiring layer located on a side of the first dielectric layer away from the encapsulation structure, the second rewiring layer being electrically connected to both the first rewiring layer and the bonding pads on the front side of the second die;
And a second dielectric layer formed on the second rewiring layer and the exposed second protective layer of the first dielectric layer and the second die.
13. The semiconductor package according to claim 12, wherein a thickness of the second die is less than a thickness of the encapsulation structure.
14. The semiconductor package according to claim 12, wherein a side of the second protective layer remote from the second die is flush with a side of the first dielectric layer remote from the encapsulation structure.
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