TW201832297A - Package on package structure and manufacturing method thereof - Google Patents

Abstract

A package on package structure including a first package structure, an interposer layer, a thermal conductive layer, and a second package structure is provided. The first package structure includes a first chip and a first insulation encapsulation. The first insulation encapsulation encapsulates the first chip and exposes a top surface of the first chip. The interposer layer is disposed on the first package structure and is electrically connected to the first package structure. The heat conductive layer is sandwiched between the first package structure and the interposer layer. The thermal conductive layer covers at least part of the top surface of the first chip. The thermal conductive layer is directly in contact with the first chip and the interposer layer. The second package structure is disposed on the interposer layer and is electrically connected to the interposer layer. A manufacturing method of a package on package structure is also provided.

Description

Package stack structure and manufacturing method thereof

The present invention relates to a package stack structure and a method of fabricating the same, and more particularly to a package stack structure having a heat conductive layer and a method of fabricating the same.

In recent years, the integration of integrated circuits has been increasing. As package sizes become smaller and smaller, multi-wafer stacked semiconductor package structures, such as package on package (PoP) applications, are rapidly growing.

The stacked package stacks different chip package units on each other and sandwiches an interposer between the chip package units. For example, a memory chip package unit is stacked on an interposer and a logic chip package unit is stacked on the interposer. In the existing package stacking process, there is a gap between the interposer and the underlying package structure, so that the wafer in the package structure is exposed to air. However, since the convection phenomenon of the air is not easy to dissipate heat, the wafer is overheated and the wafer processing speed is slowed down. In addition, the gap between the interposer and the underlying encapsulation structure may cause the stacked package structure to easily cause joint cracking in the reliability test.

The invention provides a package stack structure and a manufacturing method thereof, which can effectively improve heat dissipation efficiency and prevent problems such as joint breakage.

The present invention provides a package stack structure including a first package structure, an interposer, a heat conductive layer, and a second package structure. The first package structure includes a first wafer and a first insulating sealing body. The first insulating sealing body seals the first wafer and exposes an upper surface of the first wafer. The interposer is disposed on the first package structure and electrically connected to the first package structure. The thermally conductive layer is sandwiched between the first package structure and the interposer and covers at least a portion of the upper surface of the first wafer. The thermally conductive layer is in direct contact with the first wafer and the interposer. The second package structure is disposed on the interposer and electrically connected to the interposer.

The present invention provides a method of fabricating a package stack construction that includes at least the following steps. First, a first package structure is formed, wherein the first package structure includes a first wafer and a first insulating sealing body, the first insulating sealing body sealing the first wafer and exposing an upper surface of the first wafer. Next, a thermally conductive layer is formed on at least a portion of the upper surface of the first wafer. And forming an interposer on the heat conducting layer and the first package structure, wherein the interposer is electrically connected to the first package structure, and the heat conductive layer is sandwiched between the first package structure and the interposer, and is coupled to the first chip and the interposer The layer is in direct contact. A second package structure is formed on the interposer, wherein the second package structure is electrically connected to the interposer.

Based on the above, by filling the heat conductive layer into the gap between the first package structure and the interposer, the thermal energy generated by the first wafer in the first package structure can be conducted and dissipated by the heat conduction layer, thereby greatly improving the package stack. The heat dissipation efficiency of the structure. In addition, since the heat conductive layer is in direct contact with the first wafer and the interposer, the heat conductive layer can disperse the stress received by the interposer conductive terminals during the reliability test, so that the problem of the package stack structure joint breakage can be prevented.

The above described features and advantages of the invention will be apparent from the following description.

1A through 1H are schematic cross-sectional views showing a manufacturing process of a package stack structure in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a first carrier 110 is provided. The first carrier 110 has a first surface S1 and a second surface S2 with respect to the first surface S1. The first carrier 110 includes a first core layer 112, a first wiring layer 114 on the first surface S1, a second wiring layer 116 on the second surface S2, and a plurality of vias 118. The first core layer 112 is an intermediate layer of the first carrier 110, and the material thereof includes, for example, glass, epoxy resin, polyimide (PI), Bismaleimide Triazine (Bismaleimide Triazine) ; BT) resin, FR4 or other suitable material. The first carrier 110 has an active area A and a peripheral area R surrounding the active area A. The first circuit layer 114 includes a plurality of pads 114a located in the active region A and a plurality of pads 114b located in the peripheral region R, and the second circuit layer 116 includes a plurality of pads 116a. The materials of the pads 114a, the pads 114b, and the pads 116a include, for example, copper, tin, gold, nickel, or other conductive materials. In addition, the method of forming the pads 114a, the pads 114b, and the pads 116a includes, for example, a photolithography process, however, the invention is not limited thereto. Other materials and methods suitable for forming pads 114a, pads 114b, and pads 116a can also be used in the present invention. The via hole 118 penetrates the first core layer 112 to electrically connect at least a portion of the pad 114a and the pad 114b to the pad 116a through the via hole 118. The material of the via hole 118 may be the same as or different from the material of the pad 114a, the pad 114b, and the pad 116a. In other words, the material of the via hole 118 includes, for example, copper, tin, gold, nickel, or other conductive material. It should be noted that FIG. 1A omits some circuit layers in the first carrier 110. In other embodiments, the first carrier 110 may include other circuit layers embedded in the first core layer 112 in addition to the first circuit layer 114 and the second circuit layer 116.

Referring to FIG. 1B, a plurality of first conductive terminals 120 are formed on the second surface S2 of the first carrier 110. The first conductive terminal 120 is electrically connected to the second circuit layer 116 of the first carrier 110 . Specifically, the first conductive terminal 120 is disposed corresponding to the pad 116a to be electrically connected to the pad 116a and at least a portion of the via hole 118. In some embodiments, the first conductive terminal 120 includes, for example, a solder ball, although the invention is not limited thereto. A conductive structure exhibiting other shapes or materials may also serve as the first conductive terminal 120. For example, in other embodiments, the first conductive terminal 120 is a conductive pillar or a conductive bump. In some embodiments, the first conductive terminal 120 can be formed by, for example, a ball placement and a reflow process.

Referring to FIG. 1C, a first wafer 130 and a plurality of conductive structures 140 are formed on the first surface S1 of the first carrier 110. The first wafer 130 is located within the active region A and the conductive structure 140 is located within the peripheral region R. In some embodiments, the first wafer 130 includes a plurality of first conductive bumps 132 , and the first wafer 130 is flip-chip and the first carrier 110 by the first conductive bumps 132 . The pads 114a are connected. For example, the first conductive bump 132 can be a copper stud bump, and the end surface of the first conductive bump 132 can be soldered to the pad 114a of the first carrier 110 using solder (not shown). In addition, in some embodiments, an underfill (not shown) is further included between the first wafer 130 and the first carrier 110 to seal the first conductive bump 132 and increase the first wafer 130 and The reliability of the bonding process of the first carrier 110. In some embodiments, the first wafer 130 is, for example, an Application-Specific Integrated Circuit (ASIC). For example, the first wafer 130 may be used to execute a logic application, but the invention is not limited thereto. In other embodiments, the first wafer 130 can also be other suitable active components.

The conductive structure 140 surrounds the first wafer 130. In some embodiments, the conductive structure 140 is disposed corresponding to the pad 114b, so the conductive structure 140 is electrically connected to the first circuit layer 114 of the first carrier 110 and at least a portion of the vias 118. In the present embodiment, as shown in FIG. 1C, the conductive structure 140 is elliptical, but the invention is not limited thereto. In other embodiments, the electrically conductive structure 140 can also be a cylinder, a sphere, or other geometric shape. In some embodiments, the conductive structures 140 may form a dense array on the first carrier 110 to meet the need for fine pitch routing in subsequent processes. The material of the conductive structure 140 includes copper, tin, gold, nickel or other conductive materials, and the conductive structure 140 may be a single layer or a multilayer structure. For example, the conductive structure 140 may be a single layer structure composed of copper, gold, nickel, or solder, or may be a multilayer structure composed of copper-solder, copper-nickel-solder, or the like. Although FIG. 1C illustrates that the height of the conductive structure 140 is greater than the height of the first wafer 130, the invention is not limited thereto. In other embodiments, the ratio between the height of the conductive structure 140 and the height of the first wafer 130 may be 1:1.

Referring to FIG. 1D, a first insulating sealing body 150 is formed on the first surface S1 of the first carrier 110 to seal the first wafer 130 and the conductive structure 140. In some embodiments, the first insulating sealing body 150 can be formed on the first carrier 110 by a molding process, and the first insulating sealing body 150 is, for example, an epoxy resin compound (EMC), a resin. (resin) or other suitable insulating material.

Referring to FIG. 1E, the first insulating sealing body 150 and the conductive structure 140 are ground until the upper surface T of the first wafer 130 is exposed. In this step, the manufacturing process of the first package structure 100 has been substantially completed. It should be noted that in some embodiments, after the upper surface T of the first wafer 130 is exposed, the first wafer 130 may be further polished to further thin the overall thickness of the first package structure 100. As described above, since the first wafer 130 is configured by flip chip, the active surface thereof faces the first carrier 110, so the upper surface T of the first wafer 130 is actually the inactive surface of the first wafer 130. . Therefore, even if a portion of the inactive surface is removed, the performance of the first wafer 130 is not affected. The method of grinding the first insulating sealing body 150 and the conductive structure 140 includes mechanical grinding, chemical-mechanical polishing (CMP), etching, or other suitable processes. In some embodiments, the grinding process can reduce the height of the electrically conductive structure 140 by about 50 to 100 [mu]m.

In some embodiments, since the conductive structure 140 is an elliptical or circular structure having a wide middle portion and a narrow top end and a bottom end, the conductive structure 140 is electrically conductive when the removed height is close to half the height of the complete conductive structure 140. The structure 140 can have a larger area exposed by the first insulating sealing body 150. It should be noted that although FIG. 1B and FIG. 1C illustrate that the first wafer 130 and the conductive structure 140 are formed on the first surface S1 of the first carrier 110 after the first conductive terminal 120 is formed, the present invention does not. Limited to this order. In other embodiments, after the first wafer 130 and the plurality of conductive structures 140 are formed (as shown in FIG. 1C ) or after the first insulating sealing body 150 and the conductive structure 140 (shown in FIG. 1E ) are ground. The first conductive terminal 120 is formed on the second surface S2 of the first carrier 110.

Referring to FIG. 1F, a thermally conductive layer 200 is formed on the active region A of the first package structure 100. In the present embodiment, the heat conductive layer 200 completely covers the upper surface T of the first wafer 130, and the sidewalls of the heat conductive layer 200 are aligned with the sidewalls of the first wafer 130. That is, the heat conductive layer 200 is only located in the active area A. Since there is no gap between the first wafer 130 and the first insulating sealing body 150, the heat conductive layer 200 does not come into contact with the side surface of the first wafer 130. In some embodiments, the material of the thermally conductive layer 200 includes a binder and a thermally conductive powder dispersed in the binder. The material of the binder includes an epoxy resin, an alkyd resin, an acrylic resin, a polyurethane resin, a phenol resin, a vinyl chloride-vinyl acetate copolymer resin, or a combination thereof. On the other hand, the thermally conductive powder is, for example, a metal, a diamond, a combination thereof or other material having a high thermal conductivity. In some embodiments, the thermally conductive layer 200 can be formed by methods such as spin coating, inkjet coating, or photolithography.

Referring to FIG. 1G, an interposer 300 is formed on the thermally conductive layer 200 and the first package structure 100. The heat conductive layer 200 is sandwiched between the first package structure 100 and the interposer 300 and is in direct contact with the first wafer 130 and the interposer 300. The interposer 300 includes an interposer substrate 310 and a plurality of interposer conductive terminals 320. The interposer substrate 310 includes an interposer core layer 312, a third circuit layer 314, a fourth circuit layer 316, and via holes 318. The third wiring layer 314 is located on one side of the interposer substrate 310, and the fourth wiring layer 316 is located on the other side of the interposer substrate 310. The third circuit layer 314 includes a plurality of pads 314a, and the fourth circuit layer 316 includes a plurality of pads 316a. The materials and forming methods of the pads 314a and the pads 316a are similar to those of the pads 114a, the pads 114b, and the pads 116a, and are not described herein. The via 318 penetrates the intermediate core layer 312 such that at least a portion of the pads 314a are electrically connected to the pads 316a through the vias 318. In some embodiments, the material of the via 318 may be the same as or different from the material of the pad 314a and the pad 316a.

The interposer conductive terminal 320 is disposed on the interposer substrate 310 and connected to at least a portion of the pads 316a. Specifically, the interposer conductive terminal 320 is disposed corresponding to the conductive structure 140 of the first package structure 100 such that the interposer 300 is electrically connected to the first package structure 100. In other words, the interposer conductive terminal 320 is disposed on the peripheral region R of the first package structure 100. The material and formation method of the interposer conductive terminal 320 are similar to the material and formation method of the first conductive terminal 120, and therefore will not be described herein. In some embodiments, the height H1 of the interposer conductive terminal 320 may be the same as the thickness H2 of the thermally conductive layer 200 such that the thermally conductive layer 200 is in direct contact with the first wafer 130 and the interposer 300. For example, in some embodiments, the thermal conductive layer 200 is in direct contact with the first wafer 130 and the pads 316a of the interposer 300. Therefore, the thermal energy emitted by the first wafer 130 during operation can be conducted through the pads 316a. Other heat dissipation structures or air are used to further improve heat dissipation efficiency. In addition, the heat conductive layer can disperse the stress received by the interposer conductive terminal 320 in the subsequent reliability test, so that the problem of joint breakage can be prevented.

Referring to FIG. 1H , a second package structure 400 is formed on the interposer 300 , and the second package structure 400 is electrically connected to the interposer 300 . The second package structure 400 is similar to the first package structure 100, so the materials and formation methods of the components in the second package structure 400 will not be described herein. The second package structure 400 and the first package structure 100 differ in that the second package structure 400 may not include the conductive structure 140 like the first package structure 100 and may not pass through the polishing process as the first package structure 100. Specifically, the second package structure 400 includes a second carrier 410, a second wafer 430, a second insulating sealing body 450, and a plurality of second conductive terminals 420. The second carrier 410 has a third surface S3 and a fourth surface S4 with respect to the third surface S3. The second wafer 430 is disposed on the third surface S3. The second insulating sealing body 450 is disposed on the third surface S3 and seals the second wafer 430. The plurality of second conductive terminals 420 are disposed on the fourth surface S4 and electrically connected to at least a portion of the pads 314 a of the interposer 300 .

The second carrier 410 includes a second core layer 412, a fifth wiring layer 414 at the third surface S3, a sixth wiring layer 416 at the fourth surface S4, and a plurality of vias 418. The fifth circuit layer 414 includes a plurality of pads 414a, and the sixth circuit layer 416 includes a plurality of pads 416a. The via 418 penetrates the second core layer 412 such that at least a portion of the pads 414a are electrically connected to the pads 416a through the vias 418. It should be noted that some circuit layers in the second carrier 410 are omitted in FIG. 1H. However, in other embodiments, in addition to the fifth circuit layer 414 and the sixth circuit layer 416, the second carrier 410 may also include other circuit layers embedded in the second core layer 412.

In some embodiments, the second wafer 430 includes a plurality of second conductive bumps 432, and the second wafer 430 is connected to the pads 414a of the second carrier 410 in a flip chip manner by the second conductive bumps 432. . In addition, in some embodiments, an underfill (not shown) is further included between the second wafer 430 and the second carrier 410 to seal the second conductive bump 432 and add the second wafer 430 and the second The reliability of the bonding process of the carrier 410. In some embodiments, the second wafer 430 is, for example, a specific functional integrated circuit similar to the first wafer 130, but the invention is not limited thereto. In other embodiments, the second wafer 430 can also be other suitable active components.

Based on the above, by filling the thermal conductive layer 200 into the gap between the first package structure 100 and the interposer 300, the thermal energy generated by the first wafer 130 in the first package structure 100 can be conducted and dissipated by the heat conduction layer 200. Therefore, the heat dissipation efficiency of the package stack structure 10 is greatly improved. In addition, since the heat conductive layer 200 is in direct contact with the first wafer 130 and the interposer 300, the heat conductive layer 200 can disperse the stress received by the interposer conductive terminal 320 during the reliability test, so that the package stack structure 10 can be prevented from being broken. The problem.

2 is a cross-sectional view showing a package stack structure in accordance with another embodiment of the present invention. It is to be noted that the embodiment of FIG. 2 follows the same elements and parts of the embodiment of FIG. 1 , wherein the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated. The package stack configuration 20 of FIG. 2 differs from the package stack configuration 10 of FIG. 1H in that the area of the thermally conductive layer 200A of the package stack construction 20 is greater than the area of the first wafer 130.

Referring to FIG. 2, in the embodiment, the area of the heat conductive layer 200A is larger than the area of the first wafer 130. In other words, the heat conductive layer 200A completely covers the upper surface T of the first wafer 130 and extends from the active area A to the peripheral area R to cover a portion of the upper surface of the first insulating sealing body 150. Since the upper surface of the first insulating sealing body 150 is coplanar with the upper surface of the first wafer 130, the heat conductive layer 200A may be formed flat on the first wafer 130 and the first insulating sealing body 150.

Based on the above, the thermal energy generated by the first wafer 130 in the first package structure 100 can be conducted and dissipated by the heat conductive layer 200 by filling the thermal conductive layer 200A into the gap between the first package structure 100 and the interposer 300. Therefore, the heat dissipation efficiency of the package stack structure 20 is greatly improved. In addition, since the heat conductive layer 200A is in direct contact with the first wafer 130 and the interposer 300, the heat conductive layer 200A can disperse the stress received by the interposer conductive terminal 320 during the reliability test, so that the package stack structure 20 can be prevented from being broken. The problem. In addition, since the area of the heat conductive layer 200A of the present embodiment is larger than the area of the first wafer 130, a better heat dissipation effect can be obtained.

3 is a cross-sectional view showing a package stack structure in accordance with still another embodiment of the present invention. It is to be noted that the embodiment of FIG. 3 follows the same elements and parts of the embodiment of FIG. 1 , wherein the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated. The package stack configuration 30 of FIG. 3 differs from the package stack configuration 10 of FIG. 1H in that the area of the thermally conductive layer 200B of the package stack configuration 30 is smaller than the area of the first wafer 130.

Referring to FIG. 3, in the embodiment, the area of the heat conductive layer 200B is smaller than the area of the first wafer 130. In other words, the thermally conductive layer 200B does not completely cover the first wafer 130 and exposes a portion of the upper surface T of the first wafer 130.

Based on the above, the thermal energy generated by the first wafer 130 in the first package structure 100 can be conducted and dissipated by the heat conduction layer 200 by filling the thermal conductive layer 200B into the gap between the first package structure 100 and the interposer 300. Therefore, the heat dissipation efficiency of the package stack structure 30 is greatly improved. In addition, since the heat conductive layer 200B is in direct contact with the first wafer 130 and the interposer 300, the heat conductive layer 200B can disperse the stress received by the interposer conductive terminal 320 during the reliability test, so that the package stack structure 30 can be prevented from being broken. The problem.

In summary, by filling the gap between the first package structure and the interposer, the thermal energy generated by the first wafer in the first package structure can be conducted and dissipated by the heat conduction layer, thereby greatly improving The heat dissipation efficiency of the package stack structure. In addition, since the heat conductive layer is in direct contact with the first wafer and the interposer, the heat conductive layer can disperse the stress received by the interposer conductive terminals during the reliability test, so that the problem of the package stack structure joint breakage can be prevented.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30‧‧‧ package stack construction

100‧‧‧First package structure

110‧‧‧ first carrier

112‧‧‧First core layer

114‧‧‧First line layer

116‧‧‧Second circuit layer

114a, 114b, 116a, 314a, 316a, 414a, 416a‧‧‧ pads

118, 318, 418‧‧ ‧ through holes

120‧‧‧First conductive terminal

130‧‧‧First chip

132‧‧‧First conductive bump

140‧‧‧Electrical structure

150‧‧‧First Insulation Seal

200, 200A, 200B‧‧‧ heat conduction layer

300‧‧‧Intermediary

310‧‧‧Interposer substrate

312‧‧‧Intermediary core

314‧‧‧ third circuit layer

316‧‧‧ fourth circuit layer

320‧‧‧Interposer conductive terminals

400‧‧‧Second package structure

410‧‧‧Second carrier

412‧‧‧ second core layer

414‧‧‧ fifth circuit layer

416‧‧‧ sixth circuit layer

420‧‧‧Interposer conductive terminals

430‧‧‧second chip

432‧‧‧Second conductive bump

450‧‧‧Second insulation seal

A‧‧‧active area

R‧‧‧ surrounding area

H1‧‧‧ Height

H2‧‧‧ thickness

T‧‧‧ upper surface

S1‧‧‧ first surface

S2‧‧‧ second surface

S3‧‧‧ third surface

S4‧‧‧ fourth surface

1A through 1H are schematic cross-sectional views showing a manufacturing process of a package stack structure in accordance with an embodiment of the present invention. 2 is a cross-sectional view showing a package stack structure in accordance with another embodiment of the present invention. 3 is a cross-sectional view showing a package stack structure in accordance with still another embodiment of the present invention.

Claims (10)

A package stacking structure comprising: a first package structure including a first wafer and a first insulating sealing body, wherein the first insulating sealing body seals the first wafer and exposes an upper surface of the first wafer; a layer disposed on the first package structure and electrically connected to the first package structure; a heat conductive layer sandwiched between the first package structure and the interposer, and covering the first layer At least a portion of the upper surface of the wafer, wherein the thermally conductive layer is in direct contact with the first wafer and the interposer; and a second encapsulation structure disposed on the interposer and electrically coupled to the interposer connection. The package stack structure of claim 1, wherein the first package structure further comprises: a first carrier having a first surface and a second surface opposite to the first surface, wherein the first a wafer and the first insulating sealing body are disposed on the first surface; a plurality of conductive structures disposed on the first surface and surrounding the first wafer, wherein the conductive structure is embedded in the first An insulating sealing body, wherein the first insulating sealing body exposes the conductive structure; and a plurality of first conductive terminals disposed on the second surface. The package stack structure of claim 2, wherein the interposer comprises: an interposer substrate; and a plurality of interposer conductive terminals disposed on the interposer substrate, wherein the interposer conductive terminals correspond to The conductive structure of the first package structure is disposed to be electrically connected to the first package structure. The package stack structure of claim 3, wherein the height of the interposer conductive terminal is the same as the thickness of the heat conductive layer. The package stack structure of claim 1, wherein the second package structure comprises: a second carrier having a third surface and a fourth surface opposite to the third surface; On the third surface; a second insulating sealing body disposed on the third surface and sealing the second wafer; and a plurality of second conductive terminals disposed on the fourth surface, and The interposer is electrically connected. The package stacking structure of claim 1, wherein the heat conductive layer comprises a binder and a heat conductive powder dispersed in the binder, wherein the binder material comprises an epoxy resin, An alkyd resin, an acrylic resin, a polyurethane resin, a phenol resin, a vinyl chloride-vinyl acetate copolymer resin, or a combination thereof, and the material of the heat conductive powder includes a metal, a diamond, or a combination thereof. The package stack construction of claim 1, wherein the thermally conductive layer completely covers the first wafer. A manufacturing method of a package stack structure, comprising: forming a first package structure, wherein the first package structure includes a first wafer and a first insulating sealing body, the first insulating sealing body sealing the first wafer and exposing An upper surface of the first wafer; a thermally conductive layer formed on at least a portion of the upper surface of the first wafer; an interposer formed on the thermally conductive layer and the first package structure, wherein the interposer The first package structure is electrically connected, and the heat conductive layer is sandwiched between the first package structure and the interposer and is in direct contact with the first wafer and the interposer; A second package structure is formed on the interposer, wherein the second package structure is electrically connected to the interposer. The manufacturing method of the package stacking structure of claim 8, wherein the forming the first package structure comprises: providing a first carrier, wherein the first carrier has a first surface and a second surface of the first surface; forming a plurality of first conductive terminals on the second surface; forming the first wafer and the plurality of conductive structures on the first surface, and the conductive structure surrounds a first wafer; sealing the first wafer and the conductive structure by the first insulating sealing body; and grinding the first insulating sealing body and the conductive structure until the first wafer is exposed Up to the upper surface. The method of manufacturing a package stack structure according to claim 8, wherein the method of forming the heat conductive layer comprises spin coating, inkjet coating, or photolithography.