TWI728434B - Chip packaging method - Google Patents
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- TWI728434B TWI728434B TW108130124A TW108130124A TWI728434B TW I728434 B TWI728434 B TW I728434B TW 108130124 A TW108130124 A TW 108130124A TW 108130124 A TW108130124 A TW 108130124A TW I728434 B TWI728434 B TW I728434B
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
Description
本公開涉及半導體技術領域,尤其涉及晶片封裝方法及封裝結構。 The present disclosure relates to the field of semiconductor technology, and in particular to chip packaging methods and packaging structures.
面板級封裝(panel-level package)即將晶圓切割分離出眾多晶粒,將所述晶粒排布粘貼在載板上,將眾多晶粒在同一工藝流程中同時封裝。面板級封裝作為近年來興起的技術受到廣泛關注,和傳統的晶圓級封裝(wafer-level package)相比,面板級封裝具有生產效率高,生產成本低,適於大規模生產的優勢。 Panel-level packaging is about cutting the wafer to separate many dies, arranging and pasting the dies on a carrier board, and encapsulating the many dies at the same time in the same process flow. Panel-level packaging has received widespread attention as a technology that has emerged in recent years. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production costs, and suitability for mass production.
然而,面板封裝在技術上存在眾多壁壘,例如面板的翹曲問題;面板上的晶粒對位精準度問題等。 However, there are many technical barriers to panel packaging, such as the problem of panel warpage and the accuracy of die alignment on the panel.
尤其是在當今電子設備小型輕量化的趨勢下,小型質薄的晶片日益受到市場青睞,然而利用大型面板封裝技術封裝小型質薄晶片的封裝工藝難度更加不容小覷。 Especially in the current trend of small and lightweight electronic equipment, small and thin chips are increasingly favored by the market. However, the difficulty of packaging small and thin chips using large-scale panel packaging technology cannot be underestimated.
本公開旨在提供一種半導體晶片封裝方法和晶片封裝結構,該封裝方法可以減小或消除面板封裝過程中的翹曲,降低面板上的晶粒精準度需求,減小面板封裝工藝的難度,並且使封裝後的晶片結構具有 耐久的使用週期,尤其適用於大型面板級封裝以及大電通量、薄型晶片的封裝。 The present disclosure aims to provide a semiconductor chip packaging method and a chip packaging structure, which can reduce or eliminate warpage in the panel packaging process, reduce the precision requirements of the die on the panel, and reduce the difficulty of the panel packaging process, and So that the packaged chip structure has Durable life cycle, especially suitable for large-scale panel-level packaging as well as high-flux, thin-chip packaging.
本公開提供一種晶片封裝結構,包括:至少一個晶粒;保護層,形成於所述晶粒活性面,且所述保護層內形成有導電填充通孔,至少一部分所述導電填充通孔和至少一部分所述電連接點電連接;塑封層,所述塑封層用於包封所述晶粒;導電層,至少部分形成於所述保護層表面,所述導電層和至少一部分所述導電填充通孔電連接;介電層,形成於導電層上。 The present disclosure provides a chip packaging structure, including: at least one die; a protective layer formed on the active surface of the die, and conductive filled through holes are formed in the protective layer, at least a part of the conductive filled through holes and at least A part of the electrical connection points are electrically connected; a plastic encapsulation layer, the plastic encapsulation layer is used to encapsulate the crystal grains; a conductive layer is formed at least partly on the surface of the protective layer, and the conductive layer and at least a part of the conductive filling are connected The hole is electrically connected; the dielectric layer is formed on the conductive layer.
在一個實施例中,所述保護層的楊氏模數為以下任一數值範圍或數值:1000~20000MPa、1000~10000MPa、4000~8000MPa、1000~7000MPa、4000~7000MPa、5500MPa。 In an embodiment, the Young's modulus of the protective layer is any of the following numerical ranges or values: 1000~20000MPa, 1000~10000MPa, 4000~8000MPa, 1000~7000MPa, 4000~7000MPa, 5500MPa.
在一個實施例中,所述保護層的材料為有機/無機複合材料。 In one embodiment, the material of the protective layer is an organic/inorganic composite material.
在另一個實施例中,所述保護層的厚度為以下任一數值範圍或數值:15~50μm、20~50μm、35μm、45μm、50μm。 In another embodiment, the thickness of the protective layer is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.
在又一個實施例中,所述保護層的熱膨脹係數為以下任一數值範圍或數值:3~10ppm/K、5ppm/K、7ppm/K、10ppm/K。 In another embodiment, the thermal expansion coefficient of the protective layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.
在一個優選實施例中,所述塑封層的熱膨脹係數為以下任一數值範圍或數值:3~10ppm/K、5ppm/K、7ppm/K、10ppm/K。 In a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.
在另一個優選實施例中,所述保護層和所述塑封層具有相同或相近的熱膨脹係數。 In another preferred embodiment, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients.
在又一個優選實施例中,所述保護層中包括無機填料顆粒,所述無機填料顆粒的直徑為小於3μm。 In another preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.
在一個有利實施例中,無機填料顆粒的直徑為1~2μm。 In an advantageous embodiment, the diameter of the inorganic filler particles is 1 to 2 μm.
在一個有利實施例中,所述導電填充通孔為導電介質填充保護層開口形成,所述導電填充通孔具有導電填充通孔下表面和導電填充通孔上表面,所述導電填充通孔下表面與所述導電填充通孔上表面的面積之比為60%~90%。 In an advantageous embodiment, the conductive filled through hole is formed by a conductive medium-filled protective layer opening, and the conductive filled through hole has a lower surface of the conductive filled through hole and an upper surface of the conductive filled through hole. The ratio of the surface area to the area of the upper surface of the conductive filled through hole is 60% to 90%.
在一個有利實施例中,所述導電填充通孔下表面和所述絕緣層之間具有空隙,和/或所述導電填充通孔下表面處於電連接點接近中央位置處。 In an advantageous embodiment, there is a gap between the lower surface of the conductive filled via and the insulating layer, and/or the lower surface of the conductive filled via is at a position close to the center of the electrical connection point.
在一個優選實施例中,所述保護層開口為雷射圖案化形成的保護層開口。 In a preferred embodiment, the protective layer opening is a protective layer opening formed by laser patterning.
在另一個優選實施例中,所述導電層包括導電跡線和/或導電凸柱;其中:最靠近所述晶粒活性面的導電跡線至少一部分形成於所述保護層表面,和所述導電填充通孔電連接;所述導電凸柱形成於所述導電跡線的焊墊或連接點上。 In another preferred embodiment, the conductive layer includes conductive traces and/or conductive bumps; wherein: at least a part of the conductive traces closest to the active surface of the die is formed on the surface of the protective layer, and The conductive filled via is electrically connected; the conductive bump is formed on the bonding pad or the connection point of the conductive trace.
在又一個優選實施例中,所述導電層為一層或多層。 In another preferred embodiment, the conductive layer is one or more layers.
在一個優選實施例中,所述電連接點上形成有導電覆蓋層。 In a preferred embodiment, a conductive covering layer is formed on the electrical connection point.
在一個有利實施例中,所述導電覆蓋層的厚度為2~3μm。 In an advantageous embodiment, the thickness of the conductive covering layer is 2 to 3 μm.
在一個有利實施例中,所述導電覆蓋層為Cu層。 In an advantageous embodiment, the conductive covering layer is a Cu layer.
在一個優選實施例中,最靠近所述晶粒活性面的所述導電跡線的至少一部分形成在塑封層正面並延伸至封裝體的邊緣。 In a preferred embodiment, at least a part of the conductive trace closest to the active surface of the die is formed on the front surface of the plastic encapsulation layer and extends to the edge of the package body.
在一個優選實施例中,所述晶粒背面從所述塑封層暴露。 In a preferred embodiment, the back surface of the die is exposed from the molding layer.
在一個優選實施例中,介電層的表面對應於所述導電層的位置處具有凹槽。 In a preferred embodiment, the surface of the dielectric layer has grooves at positions corresponding to the conductive layer.
在一個優選實施例中,所述至少一個晶粒為多個晶粒,所述多個晶粒之間根據產品設計進行電連接。 In a preferred embodiment, the at least one crystal grain is a plurality of crystal grains, and the plurality of crystal grains are electrically connected according to a product design.
在一個優選實施例中,所述多個晶粒為具有不同功能的晶粒,以形成多晶片模組。 In a preferred embodiment, the plurality of dies are dies with different functions to form a multi-chip module.
本公開提供一種晶片封裝方法,包括:在晶粒的晶粒活性面上形成保護層;將所述晶粒活性面上形成保護層的晶粒貼裝於載板上,所述晶粒活性面朝向所述載板,晶粒背面朝離所述載板;形成用於包封所述晶粒的塑封層;剝離所述載板露出所述保護層。 The present disclosure provides a chip packaging method, including: forming a protective layer on the active surface of the crystal grain; mounting the crystal grain with the protective layer formed on the active surface of the crystal grain on a carrier, and the active surface of the crystal grain Facing the carrier board, the back of the die faces away from the carrier board; forming a plastic encapsulation layer for encapsulating the die; peeling off the carrier board to expose the protective layer.
在一個實施例中,在晶粒活性面上形成保護層,包括:在晶圓的晶圓活性面上形成保護層,將形成有保護層的晶圓切割成多個具有保護層的晶粒。 In one embodiment, forming a protective layer on the active surface of the die includes: forming a protective layer on the active surface of the wafer of the wafer, and cutting the wafer on which the protective layer is formed into a plurality of crystal grains with the protective layer.
在一個實施例中,所述保護層的材料為有機/無機複合材料。 In one embodiment, the material of the protective layer is an organic/inorganic composite material.
在一個實施例中,所述保護層的楊氏模數為以下任一數值範圍或數值:1000~20000MPa、1000~10000MPa、4000~8000MPa、1000~7000MPa、4000~7000MPa、5500MPa。 In an embodiment, the Young's modulus of the protective layer is any of the following numerical ranges or values: 1000~20000MPa, 1000~10000MPa, 4000~8000MPa, 1000~7000MPa, 4000~7000MPa, 5500MPa.
在一個實施例中,所述保護層的厚度為以下任一數值範圍或數值:15~50μm、20~50μm、35μm、45μm、50μm。 In an embodiment, the thickness of the protective layer is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.
在另一個實施例中,所述保護層的熱膨脹係數為以下任一數值範圍或數值:3~10ppm/K、5ppm/K、7ppm/K、10ppm/K。 In another embodiment, the thermal expansion coefficient of the protective layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.
在一個實施例中,塑封層的熱膨脹係數為以下任一數值範圍或數值:3~10ppm/K、5ppm/K、7ppm/K、10ppm/K。 In an embodiment, the thermal expansion coefficient of the plastic encapsulation layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.
在又一個實施例中,所述保護層和所述塑封層具有相同或相近的熱膨脹係數。 In another embodiment, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients.
在一個優選實施例中,所述保護層中包括無機填料顆粒,所述無機填料顆粒的直徑為小於3μm或無機填料顆粒的直徑為1~2μm。 In a preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1 to 2 μm.
在另一個優選實施例中,還包括在所述保護層上形成保護層開口的步驟,所述保護層開口下表面與保護層開口上表面面積之比為60%~90%。 In another preferred embodiment, the method further includes the step of forming a protective layer opening on the protective layer, and the ratio of the area of the lower surface of the protective layer opening to the upper surface of the protective layer opening is 60% to 90%.
在一個優選實施例中,利用雷射圖案化形成保護層開口。 In a preferred embodiment, laser patterning is used to form the protective layer openings.
在又一個優選實施例中,還包括減薄塑封層背面裸露出所述晶粒背面的步驟。 In another preferred embodiment, the method further includes the step of thinning the back surface of the plastic encapsulation layer to expose the back surface of the die.
在一個優選實施例中,還包括通過金屬蝕刻在所述介電層上的所述導電層對應的位置處形成凹槽的步驟。 In a preferred embodiment, the method further includes a step of forming a groove at a position corresponding to the conductive layer on the dielectric layer by metal etching.
在一個優選實施例中,還包括對所述晶片和/或所述保護層表面進行電漿表面處理和/或化學促進改性劑處理的步驟。 In a preferred embodiment, the method further includes the step of performing plasma surface treatment and/or chemical promotion modifier treatment on the surface of the wafer and/or the protective layer.
在一個優選實施例中,還包括在晶片活性面上進行化學鍍工藝步驟,以在電連接點上形成導電覆蓋層。 In a preferred embodiment, it further includes an electroless plating process step on the active surface of the wafer to form a conductive covering layer on the electrical connection points.
100:晶圓 100: Wafer
1001:晶圓活性面 1001: Wafer active surface
1002:晶圓背面 1002: backside of wafer
103:電連接點 103: electrical connection point
105:絕緣層 105: insulating layer
107:保護層 107: Protective layer
109:保護層開口 109: Protective layer opening
109a:保護層開口下表面 109a: The lower surface of the protective layer opening
109b:保護層開口上表面 109b: The upper surface of the protective layer opening
109c:保護層開口側壁 109c: Sidewall of protective layer opening
111:導電填充通孔 111: Conductive filled vias
111a:導電填充通孔下表面 111a: Conductive filled via bottom surface
111b:導電填充通孔上表面 111b: Conductive filling the upper surface of the via
113:晶粒 113: Die
113a:晶粒 113a: Die
113b:晶粒 113b: Die
1131:晶粒活性面 1131: Active surface of crystal grain
1132:晶粒背面 1132: Die back
117:載板 117: Carrier Board
1171:載板正面 1171: Front of the carrier board
1172:載板背面 1172: back of the carrier board
121:粘接層 121: Adhesive layer
123:塑封層 123: Plastic layer
1231:塑封層正面 1231: front side of plastic encapsulation layer
1232:塑封層背面 1232: The back of the plastic layer
125:導電跡線 125: conductive trace
127:導電凸柱 127: conductive bump
129:介電層 129: Dielectric layer
131:凹槽 131: Groove
150:面板模組 150: Panel Module
160:焊料 160: Solder
161:基板 161: Substrate
圖1至圖12是根據本公開示例性實施例提出的晶片封裝方法的流程;圖1是根據本公開示例性實施例中半導體晶圓的示意圖; 圖2是根據本公開示例性實施例中施加保護層後的半導體晶圓的示意圖;圖3a是根據本公開示例性實施例中形成保護層開口的半導體晶圓的示意圖;圖3b是根據本公開示例性實施例中形成導電填充通孔的半導體晶圓的示意圖;圖4是根據本公開示例性實施例中切割半導體晶圓形成具有保護層的晶粒的示意圖;圖5a是根據本公開示例性實施例中載板上粘貼晶粒的示意圖;圖5b是根據本公開示例性實施例中載板上粘貼晶粒組合的示意圖;圖6是根據本公開示例性實施例中在載板上形成塑封層的示意圖;圖7a是根據本公開示例性實施例中減薄塑封層厚度的示意圖;圖7b是根據本公開示例性實施例中將塑封層減薄至裸露晶粒背面的示意圖;圖8是根據本公開示例性實施例中剝離載板和粘接層的示意圖;圖9是根據本公開示例性實施例中在面板模組上形成導電填充通孔和導電跡線的示意圖;圖10是根據本公開示例性實施例中在面板模組上形成導電凸柱的示意圖;圖11a和圖11b是根據本公開示例性實施例中在面板模組上形成介電層的示意圖; 圖12是根據本公開示例性實施例中切割面板模組形成封裝完成的晶片的示意圖;圖13a是根據本公開示例性實施例提供的利用上述封裝方法得到的晶片封裝結構的示意圖;圖13b是根據本公開示例性實施例提供的利用上述封裝方法得到的晶片封裝結構的示意圖;圖13c是根據本公開示例性實施例提供的利用上述封裝方法得到的晶片模組封裝結構的示意圖;圖14a是根據本公開示例性實施例中封裝晶片在使用時的示意圖;圖14b是根據本公開示例性實施例中封裝晶片模組在使用時的示意圖。 1 to 12 are flowcharts of a chip packaging method according to an exemplary embodiment of the present disclosure; FIG. 1 is a schematic diagram of a semiconductor wafer according to an exemplary embodiment of the present disclosure; FIG. 2 is a schematic diagram of a semiconductor wafer after a protective layer is applied according to an exemplary embodiment of the present disclosure; FIG. 3a is a schematic diagram of a semiconductor wafer with a protective layer opening formed according to an exemplary embodiment of the present disclosure; FIG. 3b is a schematic diagram according to the present disclosure A schematic diagram of a semiconductor wafer with conductive filled vias formed in an exemplary embodiment; FIG. 4 is a schematic diagram of cutting a semiconductor wafer to form a die with a protective layer in an exemplary embodiment of the present disclosure; FIG. 5a is an exemplary diagram according to the present disclosure A schematic diagram of die sticking on a carrier board in an embodiment; FIG. 5b is a schematic diagram of a die combination on a carrier board according to an exemplary embodiment of the present disclosure; FIG. 6 is a plastic package formed on a carrier board according to an exemplary embodiment of the present disclosure Fig. 7a is a schematic diagram of reducing the thickness of the plastic encapsulation layer according to an exemplary embodiment of the present disclosure; Fig. 7b is a schematic diagram of thinning the plastic encapsulation layer to the back of the exposed die according to an exemplary embodiment of the present disclosure; Fig. 8 is According to a schematic diagram of peeling off the carrier board and the adhesive layer in an exemplary embodiment of the present disclosure; FIG. 9 is a schematic diagram of forming conductive filled vias and conductive traces on a panel module according to an exemplary embodiment of the present disclosure; FIG. A schematic diagram of forming conductive bumps on a panel module in an exemplary embodiment of the present disclosure; FIGS. 11a and 11b are schematic diagrams of forming a dielectric layer on a panel module according to an exemplary embodiment of the present disclosure; FIG. 12 is a schematic diagram of cutting a panel module to form a packaged chip according to an exemplary embodiment of the present disclosure; FIG. 13a is a schematic diagram of a chip package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; FIG. 13b is A schematic diagram of a chip package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; FIG. 13c is a schematic diagram of a chip module package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; FIG. 14a is A schematic diagram of a packaged chip in use according to an exemplary embodiment of the present disclosure; FIG. 14b is a schematic diagram of a packaged chip module in use according to an exemplary embodiment of the present disclosure.
為使本公開的技術方案更加清楚,技術效果更加明晰,以下結合附圖對本公開的優選實施例給出詳細具體的描述和說明,不能理解為以下描述是本公開的唯一實現形式,或者是對本公開的限制。 In order to make the technical solutions of the present disclosure clearer and the technical effects more clear, detailed descriptions and explanations of preferred embodiments of the present disclosure are given below in conjunction with the accompanying drawings. It should not be understood that the following description is the only implementation form of the present disclosure, or is a reference to the present disclosure. Disclosure restrictions.
圖1至圖12是根據本公開示例性實施例提出的晶片封裝方法的流程。 1 to 12 are flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure.
如圖1所示,提供至少一個晶圓100,該晶圓100具有晶圓活性面1001和晶圓背面1002,所述晶圓100包括多個晶粒113,其中每一個晶粒的活性表面構成了晶圓活性面1001,所述晶圓100中每一個晶粒的活性面均通過摻雜、沉積、刻蝕等一系列工藝形成一系列主動部件和被動部件,主動部件包括二極體、三極管等,被動部件包括電壓器、電容器、電
阻器、電感器等,將這些主動部件和被動部件利用連接線連接形成功能電路,從而實現晶片的各種功能。所述晶圓活性面1001還包括用於將功能電路引出的電連接點103以及用於保護該電連接點103的絕緣層105。
As shown in FIG. 1, at least one
優選的,在晶圓活性面1001上進行化學鍍工藝步驟,以在電連接點103上形成導電覆蓋層。可選的,所述導電覆蓋層為一層或多層的Cu、Ni、Pd、Au、Cr;優選的,所述導電保護層為Cu層;所述導電保護層的厚度優選為2-3μm。導電覆蓋層並未在圖1中示出。所述導電覆蓋層能夠在後續的保護層開口形成步驟中保護晶圓活性面1001上的電連接點103免受雷射損害。
Preferably, an electroless plating process step is performed on the
如圖2所示,在所述晶圓活性面1001上施加保護層107。
As shown in FIG. 2, a
在一個實施例中,保護層採用層壓的方式施加到所述晶圓活性面1001上。
In one embodiment, the protective layer is applied to the
可選的,在所述晶圓活性面1001上施加所述保護層107的步驟前,對所述晶圓活性面1001和/或所述保護層107施加於所述晶圓100上的一面進行物理和/或化學處理,以使所述保護層107和所述晶圓100的之間的結合更為緊密。處理方法可選的為電漿表面處理使表面粗糙化增大粘接面積和/或化學促進改性劑處理,在所述晶圓100和所述保護層107之間引入促進改性基團,例如同時帶有親和有機和親和無機的基團的表面改性劑,增加有機/無機介面層之間的粘合力。
Optionally, before the step of applying the
所述保護層107可以用於保護晶粒活性面1131。在之後的塑封過程中,由於塑封壓力易於使在加熱條件下流動的塑封材料滲入晶粒113和載板117的縫隙中,破壞所述晶粒活性面1131上的電路,當所述
晶粒活性面1131具有保護層時,所述保護層107可以保護所述晶粒活性面1131不使塑封材料滲入從而保護所述晶粒活性面1131免受破壞。
The
所述保護層107的存在同時也可以使所述晶粒113和粘接層121之間的粘合作用更強,使在塑封過程中,塑封壓力不易導致所述晶粒113在所述載板117上發生位置移動。
The presence of the
在一個優選實施例中,所述保護層107的楊氏模數為1000~20000MPa的範圍內、更加優選的所述保護層107的楊氏模數為1000~10000MPa範圍內;進一步優選的所述保護層107的楊氏模數為1000~7000、4000~7000或4000~8000MPa;在最佳實施例中所述保護層107的楊氏模數為5500MPa。
In a preferred embodiment, the Young's modulus of the
在一個優選實施例中,所述保護層107的厚度為15~50μm的範圍內;更加優選的所述保護層的厚度為20~50μm的範圍內;在一個優選實施例中,所述保護層107的厚度為35μm;在另一個優選實施例中,所述保護層107的厚度為45μm;在再一個優選實施例中,所述保護層107的厚度為50μm。
In a preferred embodiment, the thickness of the
所述保護層107的楊氏模數數值範圍在1000-20000MPa時,一方面,所述保護層107質軟,具有良好的柔韌性和彈性;另一方面,所述保護層可以提供足夠的支撐作用力,使所述保護層107對其表面的導電層具有足夠的支撐。同時,所述保護層107的厚度在15-50μm時,保證了所述保護層107能夠提供足夠的緩衝和支撐。
When the Young's modulus of the
特別是在一些種類的晶片中,既需要使用薄型晶粒進行封裝,又需要導電層達到一定的厚度值以形成大的電通量,此時,選擇所述
保護層107的厚度範圍為15~50μm,所述保護層107楊氏模數的數值範圍為1000-10000MPa。質軟,柔韌性佳的所述保護層107可以在所述晶粒113和所述導電層之間形成緩衝層,以使在晶片的使用過程中,所述導電層不會過度壓迫所述晶粒113,防止厚重的導電層的壓力使所述晶粒113破碎。同時所述保護層107具有足夠的材料強度,所述保護層107可以對厚重的導電層提供足夠支撐。
Especially in some types of wafers, it is necessary to use thin dies for packaging, but also need the conductive layer to reach a certain thickness value to form a large electric flux. In this case, select the
The thickness of the
當所述保護層107的楊氏模數為1000-20000MPa時,特別是所述保護層107的楊氏模數為4000-8000MPa時,所述保護層107的厚度為20~50μm時,由於所述保護層107的材料特性,使所述保護層107能夠在之後的晶粒轉移過程中有效保護所述晶粒對抗晶粒轉移設備的頂針壓力。
When the Young's modulus of the
晶粒轉移過程是將切割分離後的晶粒113重新排布粘合在載板117的過程(reconstruction process),晶粒轉移過程需要使用晶粒轉移設備(bonder machine),晶粒轉移設備包括頂針,利用頂針將晶圓100上的晶粒113頂起,用吸頭(bonder head)吸起被頂起的晶粒113轉移並粘合到載板117上。
The die transfer process is a process of rearranging and bonding the cut and separated die 113 to the carrier 117 (reconstruction process). The die transfer process requires the use of a bonder machine, which includes a thimble , Using a thimble to lift up the
在頂針頂起晶粒113的過程中,晶粒113尤其是薄型晶粒113質脆,易於受到頂針的頂起壓力而破碎,有材料特性的保護層100在此工藝中可以保護質脆的晶粒113即使在較大的頂起壓力下,也可以保持晶粒113的完整。
In the process of pushing up the
在一個優選實施例中,所述保護層107為包括填料顆粒的有機/無機複合材料層。進一步的,所述填料顆粒為無機氧化物顆粒;進
一步的,所述填料顆粒為SiO2顆粒;在一個實施例中,所述保護層107中的填料顆粒,為兩種或兩種以上不同種類的無機氧化物顆粒,例如SiO2混合TiO2顆粒。優選的,所述保護層107中的填料顆粒,例如無機氧化物顆粒,例如SiO2顆粒,例如SiO2混合TiO2顆粒,為球型或類球型。在一個優選實施例中,所述保護層107中的填料顆粒,例如無機氧化物顆粒,例如SiO2顆粒,例如SiO2混合TiO2顆粒,的填充量為50%以上。
In a preferred embodiment, the
有機材料具有易操作易施加的優點,待封裝晶粒113為無機材料如矽材質,當保護層107單獨採用有機材料時,由於有機材料的材料學性質和無機材料的材料學性質之間的差異,會使封裝工藝難度大,影響封裝效果。採用在有機材料中添加無機顆粒的有機/無機複合材料,會使有機材料的材料學性能得到改性,使材料兼具有機材料和無機材料的特點。
Organic materials have the advantages of easy operation and application. The
在一個優選實施例中,當(T<Tg)時,所述保護層107的熱膨脹係數的範圍為3~10ppm/K;在一個優選實施例中,所述保護層107的熱膨脹係數為5ppm/K;在一個優選實施例中;所述保護層107的熱膨脹係數為7ppm/K;在一個優選實施例中,所述保護層107的熱膨脹係數為10ppm/K。
In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the
在接下來的塑封工藝中,施加有保護層107的晶粒113會在塑封過程的加熱和冷卻過程中相應的膨脹和收縮,當保護層107的熱膨脹係數在3~10ppm/K的範圍時,保護層107和晶粒113之間的膨脹收縮程度保持相對一致,保護層107和晶粒113的連接介面不易產生介面應力,
不易破壞保護層107和晶粒113之間的結合,使封裝後的晶片結構更加穩定。
In the next plastic packaging process, the
封裝完成的晶片在使用過程中,常常需要經歷冷熱循環,保護層107的熱膨脹係數範圍為3~10ppm/K和晶粒113具有相同或者相近的熱膨脹係數,在冷熱循環過程中,保護層107和晶粒113保持相對一致的膨脹和收縮程度,免於在保護層107和晶粒113之間的介面積累介面疲勞,使封裝後的晶片具有耐久性,延長晶片使用壽命。
The packaged chip often needs to undergo thermal and cold cycles during use. The thermal expansion coefficient of the
另一方面,保護層的熱膨脹係數過小,需使保護層107的複合材料中填充過多的填料顆粒,在進一步減小熱膨脹係數的同時也會增大材料的楊氏模數,使保護層材料的柔韌性減少,剛度過強,保護層107的緩衝作用欠佳。將保護層的熱膨脹係數限定為5-10ppm/k為最優。
On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill the composite material of the
在一個優選實施例中,所述保護層107中的填料顆粒,例如無機氧化物顆粒,例如SiO2顆粒的直徑為小於3μm,優選的所述保護層107中的填料顆粒,例如無機氧化物顆粒,例如SiO2顆粒的直徑為1~2μm之間。
In a preferred embodiment, the filler particles in the
控制填料顆粒的直徑尺寸為小於3μm,有利於雷射圖案化製程中在保護層107上形成具有較平滑側壁的保護層開口,從而在導電材料填充工藝中可以使材料填充充分,避免具有大尺寸凹凸的保護層開口側壁109c在有凸起遮擋的側壁後側導電材料無法填充,影響導電填充通孔111的導電性能。
Controlling the diameter size of the filler particles to be less than 3μm is beneficial to forming a protective layer opening with smoother sidewalls on the
同時,1~2μm的填充尺寸會使雷射圖案化的過程中,將小粒徑的填料暴露出來,使保護層開口側壁109c具有一定粗糙度,此具有
一定粗糙度的側壁會和導電材料的接觸面更大,接觸更加緊密,形成導電性能好的導電填充通孔111。
At the same time, the filling size of 1~2μm will expose the small particle size filler during the laser patterning process, so that the
以上所述填料的直徑尺寸為顆粒直徑的平均值。 The diameter of the filler described above is the average value of the particle diameter.
在一個優選實施例中,所述保護層107的抗拉強度的數值範圍為20~50MPa;在一個優選實施例中,所述保護層107的抗拉強度為37MPa。
In a preferred embodiment, the value range of the tensile strength of the
可選的,在所述晶圓活性面1001上施加所述保護層107流程後,對所述晶圓背面1002進行研磨減薄晶片至所需厚度。
Optionally, after the process of applying the
現代電子設備小型輕量化,晶片具有薄型化趨勢,在此步驟中,所述晶圓100有時會需要被減薄到很薄的厚度,然而,薄型晶圓100的加工和轉移難度大,研磨減薄過程工藝難度大,往往很難將晶圓100減薄到理想厚度。當晶圓100表面具有保護層107時,具有材料特性的保護層107會對晶圓100起到支撐作用,降低晶圓100的加工,轉移和減薄難度。
Modern electronic equipment is small and lightweight, and the wafer has a trend of thinning. In this step, the
如圖3a所示,在所述保護層107表面形成保護層開口109。
As shown in FIG. 3a, a
在所述保護層107與晶圓活性面1001上的電連接點103相對應的位置處形成保護層開口109,將晶圓活性面1001上的電連接點103暴露出來。
A
優選的,保護層開口109和晶圓活性面1001上的電連接點103之間一一對應。
Preferably, there is a one-to-one correspondence between the
可選的,至少一部分所述保護層開口109中的每一個所述保護層開口109對應多個所述電連接點103。
Optionally, each of at least a part of the
可選的,至少一部分所述電連接點103對應多個所述保護層開口109。
Optionally, at least a part of the electrical connection points 103 correspond to a plurality of the
可選的,至少一部分所述保護層開口109沒有對應的電連接點103,或者,至少一部分所述電連接點103沒有對應的保護層開口109。
Optionally, at least a part of the
優選的,採用雷射圖形化的方式形成所述保護層開口。 Preferably, the protective layer opening is formed in a laser patterning manner.
在雷射圖形化形成保護層開口109的工藝流程中,化學鍍工藝步驟中在電連接點103上形成的導電覆蓋層可以保護晶圓活性面1001上的電連接點103免受雷射損害。
In the process flow of forming the
優選的,如圖3a中的局部放大圖所示,所述保護層開口下表面109a和所述絕緣層105之間具有空隙,和/或所述保護層開口下表面109a處於電連接點103接近中央位置處。
Preferably, as shown in the partial enlarged view in FIG. 3a, there is a gap between the lower surface of the
在一優選實施例中,保護層開口109的形狀為,保護層開口上表面109b的面積比保護層開口下表面109a的面積大,保護層開口下表面109a與保護層開口上表面109b面積之比為60%~90%。
In a preferred embodiment, the shape of the
此時,保護層開口側壁109c的斜度可以使導電材料的填充容易進行,在填充過程中,導電材料會均勻連續形成在側壁上。
At this time, the slope of the
可選的,如圖3b所示,在所述保護層開口109中填充導電介質,使得所述保護層開口109成為導電填充通孔111,至少一部分所述導電填充通孔111與所述晶圓活性面1001上的電連接點103電連接。使得所述導電填充通孔111,將所述晶圓活性面1001上的電連接點103單一方面延伸至保護層表面,保護層圍繞形成在所述導電填充通孔111四周。
導電介質可以是金、銀、銅、錫、鋁等材料或其組合材料,也可以為其它合適的導電材料通過利用PVD、CVD、濺射、電解電鍍、無電極電鍍工藝,或者其它合適的金屬沉積工藝形成在保護層開口109形成導電填充通孔111。
Optionally, as shown in FIG. 3b, the
導電介質的填充可以為對保護層開口109的完全填充,也可以為只在保護層開口109中形成一層導電材料,能夠和導電層進行電連接即可。相應的,對導電填充通孔111的理解為只要使保護層開口109中具有導電介質,該導電介質能夠和導電層進行電連接即可,不必要是對保護層開口109完全填充形成。
The filling of the conductive medium may be a complete filling of the
通過預先在保護層107上形成保護層開口109和/或填入導電介質的方式,使得晶圓活性面1001上電連接點103的位置可以通過保護層開口109精準定位,且保護層開口109面積可以做的更小,開口之間的間距也能夠更小,這樣使得後續導電層形成步驟時,導電跡線可以更加緊密,不用擔心電連接點103的位置定位偏差的問題。
By pre-forming the protective layer opening 109 on the
如圖4所示,將施加過保護層107的晶圓100沿著切割道進行切割,得到多個形成有保護層的晶粒113,所述晶粒113具有晶粒活性面1131和晶粒背面1132。
As shown in FIG. 4, the
在一個實施例中,切割如圖2所示出的具有保護層107的晶圓100形成晶粒113。
In one embodiment, the
在一個實施例中,切割如圖3a所示出的具有保護層107和保護層開口109的晶圓100形成晶粒113。
In one embodiment, the
在一個實施例中,切割如圖3b所示出的具有保護層107和導電填充通孔111的晶圓100形成晶粒113。
In one embodiment, the
由於保護層107的材料特性,使得在晶圓100的切割工序中,分離出的晶粒113沒有毛刺和碎屑(die chip)。
Due to the material properties of the
在一個實施例中,在切割所述晶圓100分離出所述晶粒113步驟之前,還包括對施加有所述保護層107的晶圓100的具有保護層107的一面進行電漿表面處理,增大表面粗糙度,以使後續工藝中所述晶粒113在所述載板117上的粘合性增大,不易產生所述晶粒113在塑封壓力下的晶粒移動。
In one embodiment, before the step of dicing the
可以理解的是,在工藝允許的情況下,根據具體的實際情況可選擇的將所述晶圓100切割成待封裝晶粒113後,在每個待封裝晶粒113的晶粒活性面1131上形成保護層。
It can be understood that, if the process permits, the
如圖5a所示,提供一個載板117,所述載板117具有載板正面1171和載板背面1172,在所述載板正面1171的預設位置上排布分割好的所述晶粒113,所述晶粒活性面1131朝向所述載板117,所述晶粒背面1132朝離所述載板117排布。
As shown in FIG. 5a, a
載板117的形狀為:圓形、三邊形、四邊形或其它任何形狀,載板117的大小可以是小尺寸的晶圓基板,也可以是各種尺寸特別是大尺寸的矩形載板,載板117的材質可以是金屬、非金屬、塑膠、樹脂、玻璃、不銹鋼等。優選的,載板117為不銹鋼材質的四邊形大尺寸面板。
The shape of the
載板117具有載板正面1171和載板背面1172,載板正面1171優選的為一個平面。
The
在一個實施例中,利用粘接層121將晶粒113粘合並固定在載板117上。
In one embodiment, the
粘接層121可通過層壓、印刷、噴塗、塗敷等方式形成在載板正面1171上。為了便於在之後的流程中將載板117和背部塑封完成的晶粒113分離,粘接層121優選的採用易分離的材料,例如採用熱分離材料作為粘接層121。
The
優選的,可以在載板117上預先標識出晶粒113排布的位置,標識可採用雷射、機械刻圖等方式在載板117上形成,同時晶粒113上也設置有對位元標識,以在粘貼時與載板117上的粘貼位置瞄準對位。
Preferably, the position where the
可選的,如圖5b所示,在一次封裝過程中,可以將多個,特別是具有不同功能的多個晶粒113a和113b,圖中示出兩個,也可以為兩個以上,按照實際產品的需求排布在載板117上,並進行封裝,在完成封裝後,再切割成多個封裝體;由此一個封裝體包括多個所述晶粒113a和113b以形成多晶片模組(multi-chip module,MCM),而多個所述晶粒113a和113b的位置可以根據實際產品的需要進行自由設置。
Optionally, as shown in FIG. 5b, in one packaging process, multiple, especially multiple dies 113a and 113b with different functions, two or more than two are shown in the figure, according to The actual product requirements are arranged on the
排布在載板117的晶粒113的形式,可以為如圖2所示出的具有保護層107的晶圓100切割成的晶粒113。
The form of the die 113 arranged on the
也可以為如圖3a所示出的具有保護層107和保護層開口109的晶圓100切割成的晶粒113,在形成有所述保護層107和所述保護層開口109的所述晶粒113粘貼在所述載板117的粘接層121上之後,保護層開口109呈中空狀態。
It may also be a die 113 cut into a
還可以為如圖3b所示出的具有保護層107和導電填充通孔111的晶圓100切割成的晶粒113。
It can also be a die 113 cut into a
如圖6所示,形成塑封層123。
As shown in FIG. 6, a
在所述待封裝晶粒113的四周以及載板正面1171或粘接層121的裸露表面形成塑封層123。塑封層123用於將載板正面1171和待封裝晶粒113完全包封住,以重新構造一平板結構,以便在將載板117剝離後,能夠繼續在重新構造的該平板結構上進行接下來的封裝步驟。
A
將塑封層123與載板正面1171或粘接層121接觸的一面定義為塑封層正面1231。將塑封層123背離載板正面1171或粘接層121的一面定義為塑封層背面1232。
The side of the
優選的,所述塑封層正面1231和所述塑封層背面1232基本上呈平板狀,且與所述載板正面1171平行。
Preferably, the
在一實施例中,所述塑封層123採用有機/無機複合材料採用模壓成型的方式形成。
In one embodiment, the
優選的,所述塑封層123的熱膨脹係數為3~10ppm/K;在一個優選實施例中所述塑封層123的熱膨脹係數為5ppm/K;在另一個優選實施例中所述塑封層123的熱膨脹係數為7ppm/K;在再一個優選實施例中所述塑封層123的熱膨脹係數為10ppm/K。
Preferably, the thermal expansion coefficient of the
優選的,所述塑封層123和所述保護層107具有相同或相近的熱膨脹係數。
Preferably, the
將塑封層123的熱膨脹係數選定為3~10ppm/K且選定和保護層107具有相同或相近的熱膨脹係數,塑封流程的加熱和冷卻過程中,
保護層107,塑封層123之間的膨脹收縮程度保持一致,兩種材料不易產生介面應力,低的熱膨脹係數使塑封層、保護層和晶粒的熱膨脹係數接近,使塑封層123,保護層107以及晶粒113的介面結合緊密,避免產生介面層分離。
The thermal expansion coefficient of the
封裝完成的晶片在使用過程中,常常需要經歷冷熱循環,由於保護層107、塑封層123以及晶粒113的熱膨脹係數相近,在冷熱循環過程中,保護層107和塑封層123以及晶粒113的介面疲勞小,保護層107、塑封層123以及晶粒113之間不易出現介面間隙,使晶片的使用壽命增長,晶片的可應用領域廣泛。
The packaged chip often needs to undergo a thermal cycle during use. Since the thermal expansion coefficients of the
晶粒113和塑封層123熱膨脹係數的差異還會使塑封後的面板元件產生翹曲,由於翹曲現象的產生,使得後續的導電層形成工藝中,難以定位晶粒113在面板元件中的精確位置,對導電層形成工藝產生很大影響。
The difference in thermal expansion coefficient between the die 113 and the
特別的,在大面板封裝工藝中,由於面板的尺寸較大,即便是輕微的面板翹曲,也會使面板遠離中心的外部四周圍部分的晶粒相對於模塑成型之前,產生較大尺寸的位置變化,所以,在大型面板封裝工藝中,解決翹曲問題成為整個工藝的關鍵之一,翹曲問題甚至限制了面板尺寸的放大化發展,成為大尺寸面板封裝中的技術壁壘。 Especially, in the large panel packaging process, due to the large size of the panel, even a slight panel warpage will cause the crystal grains of the outer four peripheral parts of the panel far away from the center to have a larger size than before molding. Therefore, in the large-scale panel packaging process, solving the warpage problem becomes one of the keys to the entire process. The warpage problem even limits the enlargement of the panel size and becomes a technical barrier in the large-scale panel packaging process.
將所述保護層107和所述塑封層123的熱膨脹係數限定在3~10ppm/K的範圍內,且優選所述塑封層123和所述保護層107具有相同或相近的熱膨脹係數,可以有效避免面板元件翹曲的產生,實現採用大型面板的封裝工藝。
The thermal expansion coefficients of the
同時,在塑封過程中,由於塑封壓力會對所述晶粒113背部產生壓力,此壓力易於將所述晶粒113壓入粘接層121,從而使晶粒113在形成塑封層123過程中陷入粘接層121中,在塑封層123形成後,晶粒113和塑封層正面1231不處於同一平面,晶粒113的表面為突出在塑封層正面1231之外,形成一個臺階狀的結構,在後續導電層形成過程中,導電跡線125也相應的會出現臺階狀結構,使得封裝結構不穩定。
At the same time, during the molding process, due to the molding pressure exerting pressure on the back of the
當晶粒活性面1131有具有材料特性的保護層107時,可以在塑封壓力下起到緩衝作用,避免晶粒113陷入粘接層121中,從而避免塑封層正面1231臺階狀結構的產生。
When the
如圖7a所示,所述塑封層123的厚度可以通過對所述塑封層背面1232進行研磨或拋光來減薄。
As shown in FIG. 7a, the thickness of the
在一實施例中,如圖7b所示,所述塑封層123的厚度可減薄至晶粒113的晶粒背面1132,從而暴露出晶粒背面1132。封裝成型的晶片結構如圖13b所示。
In one embodiment, as shown in FIG. 7b, the thickness of the
如圖8所示,剝離載板117,露出所述塑封層正面1231和所述保護層107。
As shown in FIG. 8, the
在一個實施例中,當排布在所述載板117的所述晶粒113的形式為如圖3a所示出的具有保護層107和保護層開口109的晶粒113,剝離所述載板1172,還會露出所述保護層開口109。
In one embodiment, when the form of the die 113 arranged on the
在一個實施例中,當排布在所述載板117的所述晶粒113的形式為如圖2所示出的具有所述保護層107但還未在所述保護層107上形成保護層開口的晶圓100切割成的晶粒113時,在剝離完所述載板
117後還有在所述塑封層123包覆的晶粒113上的保護層107上形成保護層開口的步驟。
In one embodiment, when the
在一個實施例中,當排布在載板117的晶粒113的形式為如圖3b所示出的具有保護層107和導電填充通孔111的晶圓100切割成的晶粒113時,還會露出所述導電填充通孔111。
In one embodiment, when the form of the die 113 arranged on the
將載板117分離後的包覆有晶粒113的塑封層123結構定義為面板模組150。
The structure of the
圖9和圖10示出了在塑封層123中的晶粒113上形成導電填充通孔並圖案化導電層過程的實施例。
9 and 10 show an embodiment of the process of forming conductive filling vias on the
當包覆在塑封層123中晶粒113表面的保護層107還未形成導電填充通孔111時,在所述保護層開口109中填充導電介質,使得所述保護層開口109成為導電填充通孔111,所述導電填充通孔111與所述晶圓活性面1001上的電連接點103電連接。使得所述導電填充通孔111,將所述晶圓活性面1001上的電連接點103單一方面延伸至保護層表面,保護層圍繞形成在所述導電填充通孔111四周。導電介質可以是金、銀、銅、錫、鋁等材料或其組合材料,也可以為其它合適的導電材料通過利用PVD、CVD、濺鍍、電解電鍍、無電極電鍍工藝,或者其它合適的金屬沉積工藝形成在保護層開口109形成導電填充通孔111。
When the
導電介質的填充可以為對保護層開口109的完全填充,也可以為只在保護層開口109中形成一層導電材料,能夠和導電層進行電連接即可。相應的,對導電填充通孔111的理解為只要使保護層開口109
中具有導電介質,該導電介質能夠和導電層進行電連接即可,不必要是對保護層開口109完全填充形成。
The filling of the conductive medium may be a complete filling of the
在塑封層123中的晶粒113上形成導電跡線(trace)125;所述導電跡線125的至少一部分形成在所述晶粒活性面1131上的保護層107表面,和至少一部分的導電填充通孔111電連接;在一個實施例中,導電跡線125沿著保護層107的表面和塑封層正面1231延伸,並延伸到當封裝完成的晶片封裝體的邊緣,封裝成型的晶片結構如圖13b所示。導電跡線125延伸到封裝體的邊緣,此時導電跡線125將保護層107和塑封層123的界面包覆並連接起來,增加了封裝後晶片結構的穩定性。
A
導電跡線125可以是一層或多層的銅、金、銀、錫、鋁等材料或其組合材料,也可以為其它合適的導電材料通過利用PVD、CVD、濺射、電解電鍍、無電極電鍍工藝,或者其它合適的金屬沉積工藝形成。
The
優選的,導電填充通孔111和導電跡線125在同一導電層形成步驟中進行。
Preferably, the conductive filled via 111 and the
當然,也可以選擇的,先形成導電填充通孔111,再形成導電跡線125。
Of course, alternatively, the conductive filled via 111 is formed first, and then the
圖10示出了在導電跡線125的焊墊或連接點上形成導電凸柱(stud)127;導電凸柱127的形狀可以是圓的,也可以是其它形狀如橢圓形、方形、線形等。導電凸柱127可以是一層或多層的銅、金、銀、錫、鋁等材料或其組合材料,也可以為其它合適的導電材料通過利用PVD、CVD、濺射、電解電鍍、無電極電鍍工藝,或者其它合適的金屬沉積工藝形成。
Figure 10 shows that
導電層由導電跡線125和/或導電凸柱127構成,導電層可以為一層也可以為多層。導電層可以具有扇出再佈線(fan-out RDL)的功能。
The conductive layer is composed of
如圖11a和圖11b所示,在導電層上形成介電層129。
As shown in FIGS. 11a and 11b, a
使用層壓,塗覆、噴塗、印刷、模塑以及其它等適合方法在導電層表面形成一層或多層介電層129。
One or more
介電層129可以為BCB(苯並環丁烯)、PI(聚醯亞胺)、PBO(聚苯並惡唑)、ABF、二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁、聚合物基質介電膜、有機聚合物膜;也可以為有機複合材料、樹脂複合材料、高分子複合材料、聚合物複合材料,例如具有填充物的環氧樹脂、ABF、或具有合適填充物的其它聚合物;還可以為其它具有相似絕緣和結構特性的材料。在一個優選實施例中,介電層129為ABF。介電層129起到保護導電層和絕緣的作用。在一個實施例中,介電層129施加的厚度比導電層的厚度厚,通過研磨過程將導電層裸露出來;在另一個實施例中,介電層129施加的厚度和導電層的厚度相同,施加完介電層129之後導電層正好裸露出來。
The
在一個實施例中,重複圖9至圖11b的步驟,在晶粒113的晶粒活性面1131上形成多層導電層。
In one embodiment, the steps of FIG. 9 to FIG. 11 b are repeated to form a multi-layer conductive layer on the crystal grain
重新回到圖9至圖11b的步驟中。在一個實施例中,導電層的形成步驟可以為:在晶粒113的晶粒活性面1131上形成導電跡線125;
使用層壓、塗覆、噴塗、印刷、模塑以及其它等適合方法在導電跡線125表面形成一層或多層介電層129,介電層129的高度高於導電跡線125的高度,將導電跡線125完全包封於介電層129中;及在介電層129上與導電跡線125的焊墊或連接點對應的位置處形成開口,在開口內形成導電凸柱127。
Return to the steps in Figure 9 to Figure 11b. In one embodiment, the step of forming the conductive layer may be: forming
又一實施例中,開口內可不形成導電凸柱127,使完成後的封裝體的導電跡線125的焊墊或連接點從開口中露出。
In another embodiment, the
在一優選實施例中,在介電層129的施加步驟之後,蝕刻減薄最外層導電層厚度,以在介電層129的外表面形成凹槽131,封裝成型的晶片結構如圖13b所示。
In a preferred embodiment, after the application step of the
可選的,如圖11b所示,在一次封裝過程中,可以將多個,特別是具有不同功能的多個晶粒113a和113a,圖中示出兩個,也可以為兩個以上,封裝成為多晶片封裝模組,多個晶粒113a和113b的導電層的圖案化設計根據實際產品的電連接需要進行設計。封裝成型的晶片結構如圖13c所示。 Optionally, as shown in FIG. 11b, in one packaging process, multiple, especially multiple dies 113a and 113a with different functions can be assembled. Two or more than two dies are shown in the figure. As a multi-chip package module, the patterned design of the conductive layer of the multiple dies 113a and 113b is designed according to the electrical connection requirements of the actual product. The packaged wafer structure is shown in Figure 13c.
如圖12所示,切割分離出封裝單體形成封裝完成的晶片,可以利用機械或雷射進行切割。 As shown in Figure 12, the packaged monomer is cut and separated to form a packaged wafer, which can be cut by machine or laser.
圖13a、圖13b和圖13c是晶片封裝結構示意圖。 13a, 13b and 13c are schematic diagrams of the chip package structure.
圖13a是根據本公開示例性實施例提供的封裝方法得到的晶片封裝結構的示意圖。 FIG. 13a is a schematic diagram of a chip packaging structure obtained according to a packaging method provided by an exemplary embodiment of the present disclosure.
如圖所示,一種晶片封裝結構,包括:晶粒113,所述晶粒113包括晶粒活性面1131和晶粒背面1132,所述晶粒活性面1131包括
電連接點103和絕緣層105;保護層107,形成於所述晶粒活性面1131,且所述保護層107內形成有導電填充通孔111,至少一部分所述導電填充通孔111和至少一部分所述電連接點103電連接,用於將至少一部分所述電連接點103從所述晶粒活性面1131引出;塑封層123,所述塑封層123用於包封所述晶粒113;導電層,至少部分形成於所述保護層107表面,所述導電層和至少一部分所述導電填充通孔111電連接;介電層,形成於導電層125,127上。
As shown in the figure, a chip package structure includes: a
在一個實施例中,所述保護層107的楊氏模數為以下任一數值範圍或數值:1000~20000MPa、1000~10000MPa、4000~8000MPa、1000~7000MPa、4000~7000MPa、5500MPa。
In one embodiment, the Young's modulus of the
在一個實施例中,所述保護層107的材料為有機/無機複合材料。
In one embodiment, the material of the
在一個實施例中,所述保護層107的厚度為以下任一數值範圍或數值:15~50μm、20~50μm、35μm、45μm、50μm。
In an embodiment, the thickness of the
在一個實施例中,所述保護層107的熱膨脹係數為以下任一數值範圍或數值:3~10ppm/K、5ppm/K、7ppm/K、10ppm/K。
In one embodiment, the thermal expansion coefficient of the
在一個實施例中,所述塑封層123的熱膨脹係數為以下任一數值範圍或數值:3~10ppm/K、5ppm/K、7ppm/K、10ppm/K。
In one embodiment, the thermal expansion coefficient of the
在一個實施例中,所述保護層107和所述塑封層123具有相同或相近的熱膨脹係數。
In one embodiment, the
在一個實施例中,所述保護層107中包括無機填料顆粒,所述無機填料顆粒的直徑為小於3μm或無機填料顆粒的直徑為1~2μm。
In an embodiment, the
在一個實施例中,導電填充通孔下表面111a與導電填充通孔上表面111b面積之比為60%~90%。
In one embodiment, the ratio of the area of the
在一個實施例中,所述導電填充通孔111為導電介質填充保護層開口109形成。 In one embodiment, the conductive filled via 111 is formed by filling the protective layer opening 109 with a conductive medium.
在一個實施例中,所述電連接點103上形成有導電覆蓋層。
In one embodiment, a conductive covering layer is formed on the
在一個實施例中,如圖13a中的局部放大圖所示,所述導電填充通孔下表面111a和所述絕緣層105之間具有空隙。
In one embodiment, as shown in the partial enlarged view in FIG. 13a, there is a gap between the
在一個實施例中,如圖13a中的局部放大圖所示,所述導電填充通孔下表面111a處於電連接點103接近中央位置處。
In one embodiment, as shown in the partial enlarged view in FIG. 13a, the
在一個實施例中,所述導電層包括導電跡線125和/或導電凸柱127;其中:最靠近所述晶粒活性面1131的導電跡線125至少一部分形成於所述保護層107表面,和所述導電填充通孔111電連接。
In one embodiment, the conductive layer includes
所述導電凸柱127形成於所述導電跡線125的焊墊或連接點上。
The
所述導電層可以為一層也可以為多層。 The conductive layer may be one layer or multiple layers.
在一個實施例中,如圖13b所示,最靠近所述晶粒活性面1131的所述導電跡線125的至少一部分形成在塑封層正面1231並延伸至封裝體的邊緣。
In one embodiment, as shown in FIG. 13b, at least a part of the
在又一個實施例中,如圖13b所示,所述晶粒背面1132從所述塑封層123暴露。
In another embodiment, as shown in FIG. 13 b, the
在再一個實施例中,如圖13b所示,介電層129的表面對應於所述導電層的位置處具有凹槽。
In another embodiment, as shown in FIG. 13b, the surface of the
在一個實施例中,如圖13c所示,封裝結構包括多個晶粒113,所述多個晶粒113之間根據產品設計進行電連接。可選的,所述多個晶粒113為具有不同功能的晶粒,以形成多晶片模組。 In one embodiment, as shown in FIG. 13c, the package structure includes a plurality of dies 113, and the plurality of dies 113 are electrically connected according to the product design. Optionally, the plurality of dies 113 are dies with different functions to form a multi-chip module.
圖14a示出了封裝晶片在使用時的示意圖,在使用過程中通過焊料160將封裝晶片連接到電路板或基板161上,然後與其他電路元件進行連接。
Figure 14a shows a schematic diagram of the packaged chip in use. During use, the packaged chip is connected to the circuit board or
當所述封裝晶片的介電層129的表面上具有凹槽131時,可使焊料160連接穩定,不易移動。
When the surface of the
圖14b示出了封裝晶片模組在使用時的示意圖,在使用過程中通過焊料160將封裝晶片模組連接到電路板或基板161上,然後與其他電路元件進行連接。
Fig. 14b shows a schematic diagram of the packaged chip module in use. During use, the packaged chip module is connected to the circuit board or
以上所述的具體實施例,其目的是對本公開的技術方案和技術效果進行進一步的詳細說明,但是本領域技術人員將理解的是,以上所述具體實施例並不用於限制本公開,凡在本公開的發明思路之內所做的任何修改、等效置換、改進等,均應包含在本公開的保護範圍之內。 The specific embodiments described above are for the purpose of further describing the technical solutions and technical effects of the present disclosure. However, those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the inventive idea of the present disclosure shall be included in the protection scope of the present disclosure.
103:電連接點 103: electrical connection point
105:絕緣層 105: insulating layer
107:保護層 107: Protective layer
111:導電填充通孔 111: Conductive filled vias
113:晶粒 113: Die
1131:晶粒活性面 1131: Active surface of crystal grain
1132:晶粒背面 1132: Die back
123:塑封層 123: Plastic layer
1231:塑封層正面 1231: front side of plastic encapsulation layer
1232:塑封層背面 1232: The back of the plastic layer
125:導電跡線 125: conductive trace
127:導電凸柱 127: conductive bump
129:介電層 129: Dielectric layer
131:凹槽 131: Groove
140 140
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