CN113725100A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN113725100A
CN113725100A CN202010231981.6A CN202010231981A CN113725100A CN 113725100 A CN113725100 A CN 113725100A CN 202010231981 A CN202010231981 A CN 202010231981A CN 113725100 A CN113725100 A CN 113725100A
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layer
bare chip
packaged
forming
passive element
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CN202010231981.6A
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Chinese (zh)
Inventor
周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202010231981.6A priority Critical patent/CN113725100A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the steps of forming a first protective layer on the surface of a passive element with an electric connection key, and forming a first protective layer opening on the first protective layer; the first protective layer opening corresponds to the electrical connection key of the passive element. Forming a second protection layer on the front surface of the bare chip to be packaged, and forming a second protection layer opening on the second protection layer; the front surface of the bare chip to be packaged is provided with a welding pad, and the opening of the second protective layer corresponds to the welding pad on the front surface of the bare chip to be packaged. Mounting the passive element and the bare chip to be packaged on a carrier plate at intervals; the front surface of the bare chip to be packaged faces the carrier plate, and the surface of the passive element with the electric connection keys faces the carrier plate. And forming an encapsulating layer, wherein the encapsulating layer at least encapsulates the chip to be encapsulated and the passive element.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
At present, in a semiconductor packaging process, a die and a passive component, such as a capacitor, a resistor, an inductor, etc., are often required to be packaged in a package to perform a certain function. Such a packaging technology of a package body having a bare chip and a passive component has been attracting attention.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, comprising:
forming a first protective layer on the surface of the passive element with the electric connection key, and forming a first protective layer opening on the first protective layer; wherein the first protective layer opening corresponds to the electrical connection key of the passive component;
forming a second protection layer on the front surface of the bare chip to be packaged, and forming a second protection layer opening on the second protection layer; the front surface of the bare chip to be packaged is provided with a welding pad, and the opening of the second protective layer corresponds to the welding pad on the front surface of the bare chip to be packaged;
mounting the passive element and the bare chip to be packaged on a carrier plate at intervals; the front surface of the bare chip to be packaged faces the carrier plate, and the surface of the passive element with the electric connection keys faces the carrier plate;
and forming an encapsulating layer, wherein the encapsulating layer at least encapsulates the chip to be encapsulated and the passive element.
Optionally, after forming the second protective layer on the front surface of the die to be packaged, before mounting the die to be packaged on the carrier, the method includes:
and thinning the bare chip to be packaged by grinding the back surface of the bare chip to be packaged.
Optionally, after forming the encapsulation layer, the method comprises:
and stripping the carrier plate.
Optionally, after peeling off the carrier plate, the method includes:
filling a first conductive medium in the first protective layer opening to form a first electric connection part, filling a second conductive medium in the second protective layer opening to form a second electric connection part, and forming wiring layers on the surface of the first protective layer far away from the passive element and the surface of the second protective layer far away from the bare chip; the wiring layer is electrically connected with the electric connecting keys of the passive element through the first electric connecting parts and is electrically connected with the welding pads on the front surface of the bare chip through the second electric connecting parts.
Optionally, the first electrical connection portion, the second electrical connection portion, and the wiring layer are formed in the same conductive layer process; or the like, or, alternatively,
the first electrical connection portion and the second electrical connection portion are formed in the same conductive layer process, and the wiring layer is formed in another conductive layer process.
Optionally, after forming a first protection layer opening on the first protection layer and forming a second protection layer opening on the second protection layer, before the passive component and the die to be packaged are mounted on the carrier, the method includes:
and filling a second conductive medium in the second protective layer opening to form a second electric connection part which can be electrically connected with the welding pad on the front surface of the bare chip to be packaged.
Optionally, after forming the encapsulation layer, the semiconductor packaging method includes:
stripping the carrier plate;
and forming wiring layers on the surfaces of the first protection layer far away from the passive element and the second protection layer far away from the bare chip, wherein the wiring layers are electrically connected with the electric connection keys of the passive element and the bonding pads on the front surface of the bare chip.
Optionally, after forming the wiring layer, the method further includes:
and forming a third electric connection part on the surface of the wiring layer on the side far away from the bare chip and the passive element.
Optionally, after forming the third electrical connection, the method comprises:
and forming a dielectric layer on the wiring layer, wherein the dielectric layer can cover the exposed wiring layer, part of the third electric connection part and the exposed protective layer, and the surface of the third electric connection part, which is far away from the wiring layer, exposes the dielectric layer.
Another aspect of the present application provides a semiconductor package structure, including:
the encapsulating layer is provided with a plurality of first cavities and second cavities which are spaced and inwards concave;
a passive element located within the first cavity;
a die located within the second cavity with a back side of the die facing a bottom of the cavity;
the first protection layer is formed on the surface of the passive element with the electric connection keys, and a first protection layer opening is formed on the first protection layer and is positioned at the electric connection keys on the passive element;
the second protection layer opening is formed in the front surface of the bare chip and is formed at a welding pad of the bare chip;
and the wiring structure comprises a wiring layer and a third electric connection part positioned on the wiring layer, is positioned on the surface of one side of the first protective layer, which is far away from the passive element, and is positioned on the surface of one side of the second protective layer, which is far away from the bare chip, and is used for leading out a welding pad on the front surface of the bare chip and an electric connection key of the passive element.
In the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the first protective layer and the second protective layer are respectively formed on the surface of the passive element and the front surface of the bare chip in advance, and the first protective layer opening corresponding to the electrical connection key of the passive element and the second protective layer opening corresponding to the welding pad on the front surface of the bare chip are respectively formed on the first protective layer and the second protective layer opening, so that the electrical connection key on the passive element can be accurately positioned through the first protective layer opening and the welding pad on the front surface of the bare chip can be accurately positioned through the second protective layer opening before the subsequent panel-level packaging process. And the first and second protective layers can respectively protect the front surfaces of the passive element and the bare chip in the plastic packaging process so as to prevent the plastic packaging material from permeating into the front surfaces of the passive element and the bare chip to damage the front surfaces.
Drawings
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 2(a) -2(k) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In a semiconductor packaging process, a die and a passive component, such as a capacitor, a resistor, an inductor, etc., are often packaged in a package to perform a certain function. The application provides a semiconductor packaging method. In the packaging process, firstly, a first protective layer is formed on the surface of the passive element with the electric connection keys, and a first protective layer opening is formed on the first protective layer; the first protective layer opening corresponds to the electrical connection key of the passive element. Secondly, forming a second protection layer on the front surface of the bare chip to be packaged, and forming a second protection layer opening on the second protection layer; the front surface of the bare chip to be packaged is provided with a welding pad, and the opening of the second protective layer corresponds to the welding pad on the front surface of the bare chip to be packaged. Further, the passive element and the bare chip to be packaged are mounted on a carrier plate at intervals; the front surface of the bare chip to be packaged faces the carrier plate, and the surface of the passive element with the electric connection keys faces the carrier plate. And then, forming an encapsulating layer, wherein the encapsulating layer at least encapsulates the chip to be encapsulated and the passive element. In the foregoing embodiment of the present application, the first and second passivation layers are formed on the surface of the passive device and the front surface of the die in advance, and the first passivation layer opening corresponding to the electrical connection key of the passive device and the second passivation layer opening corresponding to the pad on the front surface of the die are formed on the first and second passivation layers, respectively, so that the electrical connection key on the passive device can be accurately positioned through the first passivation layer opening and the pad on the front surface of the die can be accurately positioned through the second passivation layer opening before the subsequent panel-level packaging process. And the first and second protective layers can respectively protect the front surfaces of the passive element and the bare chip in the plastic packaging process so as to prevent the plastic packaging material from permeating into the front surfaces of the passive element and the bare chip to damage the front surfaces.
As shown in fig. 1, 2(a) -2(k) and 3, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the semiconductor packaging method includes the following steps 101 to 107:
step 101: forming a first protective layer on the surface of the passive element with the electric connection key, and forming a first protective layer opening on the first protective layer; wherein the first protective layer opening corresponds to the electrical connection key of the passive component;
step 103: forming a second protection layer on the front surface of the bare chip to be packaged, and forming a second protection layer opening on the second protection layer; the front surface of the bare chip to be packaged is provided with a welding pad, and the opening of the second protective layer corresponds to the welding pad on the front surface of the bare chip to be packaged;
step 105: mounting the passive element and the bare chip to be packaged on a carrier plate at intervals; the front surface of the bare chip to be packaged faces the carrier plate, and the surface of the passive element with the electric connection keys faces the carrier plate;
step 107: and forming an encapsulating layer, wherein the encapsulating layer at least encapsulates the chip to be encapsulated and the passive element.
In step 101, as shown in fig. 2(a), a first passivation layer 302 is formed on the surface of the passive device 301 having the electrical connection keys. The first protective layer 302 is made of an insulating material. The material of the first protective layer 302 may include BCB benzocyclobutene, PI polyimide, PBO Polybenzoxazole (Polybenzoxazole), epoxy, abf (ajinomoto build film), polymer matrix dielectric film, organic polymer film, or other materials with similar insulating and structural properties. It may also be an organic/inorganic composite material such as a resin polymer to which inorganic particles are added. Alternatively, the first protective cap layer 302 is preferably selected to be compatible with chemical cleaning, polishing, and the like. The first protective layer 302 may be formed on the passive element 301 by Lamination (Coating), Coating (Coating), Printing (Printing), or the like.
After the first protective layer 302 is formed, a first protective layer opening 3021 is formed on the first protective layer 302. The first passivation opening 3021 corresponds to an electrical connection key (not shown) of the passive device 301, such that the electrical connection key of the passive device 301 is exposed from the first passivation opening 3021. For the material of the first protection layer 302 being a laser-reactive material, the first protection layer opening 3021 may be formed by laser patterning. For the material of the first protection layer 302 is a photosensitive material, a first protection layer opening 3021 can be formed by using a photolithography patterning method. The shape of the first protection layer opening 3021 may be round, but may also be other shapes such as oval, square, linear, etc.
In step 103, a second protection layer is formed on the front surface of the die to be packaged, where the second protection layer may be formed on the front surface of the semiconductor wafer before the semiconductor wafer is cut into a plurality of die to be packaged, and then the semiconductor wafer is cut to obtain the die to be packaged, where the second protection layer is formed on the front surface. It is understood that, when the process allows, the semiconductor wafer may be cut into the dies to be packaged, and then the second protective layer is formed on the front surface of each die to be packaged, which may be selected according to a specific application, and is not limited in this application.
As shown in fig. 2(b), the front surface of the semiconductor wafer 100, corresponding to the front surface of the die 201 to be packaged, has an insulating layer 2011 and pads 2012. The pad 2012 is used for electrical connection with the outside. The front side of the die 201 to be packaged is the active side of the die 201 to be packaged. A second protection layer 202 is formed on the front side of the semiconductor wafer 100, i.e., the front side corresponding to the die 201 to be packaged.
The second protective layer 202 is made of an insulating material. The material of the second protective layer may include BCB benzocyclobutene, PI polyimide, PBO Polybenzoxazole (Polybenzoxazole), epoxy, abf (ajinomoto build film), polymer matrix dielectric film, organic polymer film, or other materials having similar insulating and structural properties. It may also be an organic/inorganic composite material such as a resin polymer to which inorganic particles are added. Optionally, the second protection layer 202 is preferably selected from a material capable of accommodating chemical cleaning, polishing, and the like. The second protective layer 202 may be formed on the die 201 to be packaged by Lamination (Coating), Coating (Coating), Printing (Printing), or the like.
Further, after the second protection layer 202 is formed on the front side of the semiconductor wafer 100, the back side of the semiconductor wafer 100, that is, the back side corresponding to the die 201 to be packaged, may be ground to reduce the thickness of the die 201 to be packaged. Of course, in some embodiments, the back side of the die may not be thinned, which is not limited in this application and may be set according to the specific application environment.
Further, the semiconductor wafer 100 is cut along the dicing streets by using a cutting device, so as to obtain a plurality of dies 201 to be packaged. The cutting process can be mechanical cutting or laser cutting.
Further, a second passivation opening 2021 is formed on the second passivation layer 202. The second passivation opening 2021 at least corresponds to the pads or the lines led out from the pads on the front surface of the die 201 to be packaged, so that the pads or the lines led out from the pads on the front surface of the die 201 to be packaged are exposed from the second passivation opening 2021. Similarly, for the material of the second passivation layer 202 being a laser-reactive material, the second passivation layer opening 2021 can be formed by laser patterning. For the material of the second passivation layer 202 being a photosensitive material, the second passivation layer opening 2021 can be formed by photolithography patterning. The shape of the second passivation opening 2021 may be round, but may also be other shapes such as oval, square, line, etc.
For convenience of illustration of the subsequent process flow, the subsequent die 201 to be packaged may adopt the schematic structure diagram shown in fig. 2 (c). Note that in this fig. 2(c) and other subsequent figures, the front side of the die to be packaged still has the insulating layer and the bonding pads.
It should be further noted that step 101 and step 103 are not in chronological order. Step 101 and step 103 may be performed simultaneously. Step 101 may be performed before step 103, or may be performed after step 103, which is not limited in this application and may be set according to a specific application environment.
In step 105, as shown in fig. 2(d), the passive component 301 with the first passivation layer 302 formed in step 101 and the bare chip 201 with the second passivation layer 202 formed in step 103 are mounted on the carrier 200 at a predetermined arrangement position interval, the front surface of the bare chip 201 to be packaged faces the carrier 200, and the surface of the passive component 301 provided with the electrical connection keys also faces the carrier 200. Here, the arrangement position of the mounting passive component 301 and the arrangement position of the mounting die 201 may be spaced apart from each other. After the passive device 301 and the die 201 are mounted on the carrier 200, the first passivation opening 3021 and the second passivation opening 2021 are still hollow.
Alternatively, the passive element 301 with the first protective layer 302 may be attached to the carrier board by an adhesive layer (not shown). The adhesive layer is used to adhere the passive component 301 with the first passivation layer 302, and the adhesive layer may be made of a material that is easily peeled off, so that the carrier plate and the passive component 301 with the first passivation layer 302 can be peeled off in a subsequent process, for example, a thermal release material that can be heated to lose its adhesiveness can be used.
Alternatively, in other embodiments, the adhesive layer may have a two-layer structure, i.e., a thermal separation material layer and an adhesive layer, the thermal separation material layer is adhered to the carrier 200 and loses its adhesiveness when heated, so that the thermal separation material layer can be peeled off from the carrier 200, and the adhesive layer is an adhesive material layer and can be used for adhering the passive component 301 having the first protective layer 302. After the passive device 301 with the first passivation layer 302 is peeled off from the carrier 200, the adhesion layer thereon can be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier 200 by lamination, printing, or the like.
The die 201 with the second protection layer 202 can be mounted on the carrier board in the same way. Reference is made to the above description, which is not repeated herein.
It should be noted that, as shown in fig. 2(d), the passive component 301 (i.e. the passive component 301 with the first protective layer 302) and the die 201 to be packaged (the die 201 to be packaged with the second protective layer 202) are placed on the carrier board 200 according to a predetermined arrangement position, for convenience of expression, only one passive component 301 and one die 201 to be packaged are shown in the drawing, and actually, a plurality of dies 201 to be packaged and passive components 301 on the carrier board 200 are arranged according to a predetermined position. Optionally, the passive component 301 and the die 201 to be packaged are disposed on the carrier 200 at an interval.
It can be understood that, in one packaging process, the bare chip to be packaged and the passive component can be multiple, that is, a plurality of passive components with a first protection layer and bare chips to be packaged with a second protection layer are simultaneously mounted on the carrier, packaged, and cut into a plurality of packages after the packaging is completed; one package may include one or more passive components and one or more dies, and the positions of the one or more passive components and the one or more dies may be set according to the needs of an actual product.
In step 107, an encapsulation layer 204 is formed on the carrier 200, wherein the encapsulation layer is capable of encapsulating at least a portion of the chip to be packaged and at least a portion of the passive component. For example, the encapsulating layer 204 can encapsulate the surface of the passive component 301 away from the carrier, the back surface of the die 201 to be packaged, and the exposed carrier. For the carrier with the bonding layer, the encapsulation layer can cover the surface of the passive component 301 away from the carrier, the back surface of the die 201 to be packaged, and the exposed bonding layer. Of course, if the surface of the carrier 200 close to the die 201 and the passive component 301 still has an exposed area, the exposed area can also be covered by the encapsulating layer. As shown in fig. 2(e), the encapsulating layer 204 completely encapsulates the carrier 200, the passive component with the first passivation layer 302, and the die 201 with the second passivation layer 202 to reconstruct a flat plate structure, so that the re-wiring and packaging can be continued on the reconstructed flat plate structure after the carrier 200 is peeled off.
In one embodiment, the encapsulating layer 204 may be formed by laminating an epoxy resin film or an abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.
The upper surface 2041 of the encapsulating layer 204 away from the carrier 200 is substantially flat and parallel or substantially parallel to the surface of the carrier 200. The thickness of encapsulant layer 204 may be thinned by grinding or polishing surface 2041. In some alternative embodiments, the thickness of the encapsulation layer 204 may be thinned to the back side of the die 201.
When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material is easily penetrated between the carrier 200 and the die 201 or between the carrier 200 and the passive component 301 in the process. The first and second protection layers 302 and 202 are disposed to prevent the encapsulating material from penetrating the surface of the die 201 and the passive component, and not directly contacting the front surface of the die and the surface of the passive component having the electrical connection keys, so as not to damage the circuit structure and the passive component on the front surface of the die 201.
Further, in some embodiments, as shown in fig. 2(f), the carrier sheet 200 may be peeled off after the formation of the encapsulant layer 204. For the adhesive layer with the thermal decomposition film between the die 201 and the passive component 301 and the carrier 200, the adhesive layer can be reduced in viscosity after being heated by heating, so as to peel off the carrier 200. By peeling carrier board 200 by heating the adhesive layer, damage to die 201 and passive component 301 during the peeling process can be minimized. Of course, in other embodiments, the carrier board 200 can be directly and mechanically peeled off.
After the carrier 200 is peeled off, the lower surface of the encapsulating layer 204, the surface of the first passivation layer 302, the surface of the second passivation layer 202, the electrical connection keys of the passive device 301 at the first passivation layer opening 3021, and the bonding pads at the second passivation layer opening 2021, which originally face the carrier 200, may be exposed. Thus, after the carrier board 200 is peeled off, a plate-shaped structure including the die 201, the passive device 301, the first passivation layer 302, the second passivation layer 202, and the encapsulating layer 204 can be obtained. In the plate-like structure, except for the first passivation opening 3021 and the second passivation opening 2021, the surfaces of the components originally close to one side of the carrier 200 are in the same plane. On the formed plate-like structure, wiring may be performed as the case may be, so that the die 201 and the passive element 301 are electrically connected to the outside. Optionally, electrical connections between the passive components 301 of the dies 2012 can also be formed simultaneously.
Further, after the carrier board 200 is peeled off, a first conductive medium may be filled in the first protective layer opening 3021 to form a first electrical connection 2031, a second conductive medium may be filled in the second protective layer opening 2021 to form a second electrical connection 2032, and a wiring layer 206 having conductive traces may be formed on the surface of the first protective layer 302 away from the passive element 301 and the surface of the second protective layer 202 away from the die 201. The wiring layer 206 is formed on the surface of the first passivation layer 302, the surface of the second passivation layer 202, and the surface of the encapsulating layer 204 on the same side. The wiring layer 206 is electrically connected to the first electrical connection portion 2031 and the second electrical connection portion 2032. The wiring layer 206 is electrically connected to the electrical connection key of the passive device 301 through the first electrical connection portion 2031 and electrically connected to the bonding pad on the front surface of the die 201 through the second electrical connection portion 2032.
Optionally, in some embodiments, the first electrical connection 2031, the second electrical connection 2032, and the wiring layer 206 are formed in the same conductive layer process.
In other embodiments, the first electrical connection portion 2031, the second electrical connection portion 2032, and the wiring layer 206 may not be formed in the same conductive layer process. For example, as shown in fig. 2(g), in some embodiments, the first electrical connection portion 2031 and the second electrical connection portion 2032 are formed in the same conductive layer process. Thereafter, as shown in fig. 2(h), a wiring layer 206 is formed in another conductive layer process. Of course, the first electrical connection portion, the second electrical connection portion and the wiring layer may also be formed in different wiring layer processes, which is not limited in the present application and may be set according to a specific application environment.
After the first passivation opening 3021 and the second passivation opening 2021 are formed in step 101 and step 103, before step 105, a first conductive medium may be filled in the first passivation opening 3021 to form a first electrical connection portion 2031 capable of being electrically connected to the electrical connection key of the passive element 301, so that the electrical connection key of the passive element 301 is led out to the surface of the passivation layer 202; and filling a second conductive medium in the second protective layer opening 2022 and the second protective layer opening 2021 to form a second electrical connection portion 2032 capable of electrically connecting with the pad 2012 on the front surface of the die 201 to be packaged, so that the pad 2012 on the front surface of the die 201 to be packaged is led out to the surface of the protective layer 202.
Accordingly, after the encapsulating layer 204 is formed and the carrier board 200 is peeled off, the lower surface of the encapsulating layer 204 originally facing the carrier board 200, the surface of the first protection layer 302, the surface of the second protection layer 202, and the surfaces of the first electrical connection portion 2031 and the second electrical connection portion 2032 far away from the die 201 may be exposed. Thus, after the carrier 200 is peeled off, a flat plate structure including the die 201, the passive device 301, the first passivation layer 302, the second passivation layer 202, the first electrical connection portion 2031 disposed on the first passivation layer, the second electrical connection portion 2032 disposed on the second passivation layer 202, and the encapsulating layer 204 is obtained. On the formed flat plate structure, according to practical situations, the wiring layer 206 may be formed on the surface of the first protection layer 302 away from the passive element 301 and the surface of the second protection layer 202 away from the die 201, and the wiring layer 206 is electrically connected to the electrical connection keys of the passive element 301 and to the pads on the front surface of the die 201.
Accordingly, after the carrier board 200 is peeled off, the surfaces of the first protective layer 302 and the second protective layer 202 are exposed, and the passive component 301 and the die 201 are attached to the carrier board 200 through an adhesive layer having a thermal release material layer and an adhesive layer, which is also present on the surfaces of the first protective layer 302 and the second protective layer 202, and which can be removed by chemical means. The first protection layer 301 and the second protection layer 202 can also protect the passive element 301 and the surface of the die 201 from being damaged when the adhesion layer is removed by chemical means. After the adhesive layer is completely removed, if the encapsulating material is infiltrated in the prior art, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated. Without the first protective layer 302 and the second protective layer 202, the surfaces of the die 201 and the passive element 301 cannot be processed by chemical or grinding, so as to prevent the circuit on the front surface of the die 201 and the passive element 301 from being damaged.
Further, as shown in fig. 2(i), after the wiring layer 206 is formed, a third electrical connection portion 207 is formed on the surface of the wiring layer 206 on the side away from the die 201 and the passive element 301.
Further, as shown in fig. 2(j), a dielectric layer 208 is formed on the surfaces of the wiring layer 206 and the third electrical connection portion 207 to protect the wiring layer 206 and the third electrical connection portion 207. The dielectric layer 208 may be formed to a thickness such that the surface of the third electrical connection portion 207 is just exposed; the dielectric layer 208 may cover all exposed surfaces of the encapsulating layer 204, the first passivation layer 302, the second passivation layer 202, and the wiring layer 206, and then be thinned to the surface of the third electrical connection portion 207. In this embodiment, a combination of the wiring layer 206, the third electrical connection portion 207, and the dielectric layer 208 can be understood as a wiring structure.
The third electrical connection portion 207 is preferably circular, but may be other shapes such as a rectangle and a square, and the third electrical connection portion 207 is electrically connected to the wiring layer 206. Specifically, the third electrical connection portion 207 may be formed in the wiring layer 206 by photolithography and plating.
In another embodiment, after the wiring layer 206 is formed, the dielectric layer 208 is formed on the wiring layer 206 and the exposed first protective layer 302, the exposed second protective layer 202 and the exposed encapsulating layer 204, the dielectric layer 208 has a dielectric layer opening, and then the third electrical connection portion 207 electrically connected to the wiring layer 206 is formed in the dielectric layer opening of the dielectric layer 208. In this embodiment, a combination of the wiring layer 206, the third electrical connection portion 207, and the dielectric layer 208 can be understood as a wiring structure.
In yet another embodiment, the dielectric layer opening of the dielectric layer may not be filled, i.e. the third electrical connection portion 207 electrically connected to the wiring layer 206 is not formed, so that the pad or the connection point of the wiring layer of the completed package is exposed from the dielectric layer opening. In this embodiment, the combination of the wiring layer 206 and the dielectric layer 208 can be understood as a wiring structure.
In one embodiment, the dielectric layer 208 may be formed by Lamination (plating), Molding (Molding) or Printing (Printing), and preferably an epoxy compound is used.
Further, in some embodiments, repeated rewiring may be performed in addition to the wiring structure, such as one or more wiring layers may be formed outside the dielectric layer in the same manner to achieve multi-layer wiring of the product.
Further, after the package of the wiring structure is formed, as shown in fig. 2(k), the entire package structure is cut into a plurality of packages, i.e., semiconductor package structures, by laser or mechanical cutting, and the structure of the formed semiconductor package structure is shown in fig. 3.
In the semiconductor packaging method provided in the above embodiment, the first and second protection layers are formed on the surface of the passive device and the front surface of the bare chip in advance, and the first protection layer opening corresponding to the electrical connection key of the passive device and the second protection layer opening corresponding to the pad on the front surface of the bare chip are formed on the first and second protection layers, respectively, so that the electrical connection key on the passive device can be accurately positioned through the first protection layer opening and the pad on the front surface of the bare chip can be accurately positioned through the second protection layer opening before the subsequent panel-level packaging process. According to the arrangement mode, the areas of the first protective layer opening and the second protective layer opening can be smaller, and the distance between the protective layer openings can also be smaller, so that the conductive trace can be tighter in the subsequent forming process of the wiring structure, and the problem that the position of the welding pad can have positioning deviation and the like is not worried when the tighter conductive trace is arranged. And the first and second protective layers can respectively protect the front surfaces of the passive element and the bare chip in the plastic packaging process so as to prevent the plastic packaging material from permeating into the front surfaces of the passive element and the bare chip to damage the front surfaces of the passive element and the bare chip. In addition, the arrangement of the first protective layer and the second protective layer can perform the wiring process of the conductive trace without forming a layer of insulating material on the whole panel in the subsequent wiring process, so that the method has the advantages of material saving (especially for the whole large panel, the saved material is considerable), and small process difficulty, and avoids the problem of large process difficulty in forming the insulating layer on the whole large panel.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application. Referring to fig. 3 and as necessary in conjunction with fig. 2(a) -2(k), the semiconductor package structure includes:
the encapsulating layer 204 is provided with a plurality of first cavities and second cavities which are spaced and recessed.
A passive element 301 located within the first cavity.
A die 201 located in the second cavity, and a back side of the die 201 faces a bottom of the second cavity.
The first passivation layer 302 is formed on the surface of the passive device 301 having the electrical connection keys, and a first passivation opening 3021 is formed on the first passivation layer 302, and the first passivation opening 3021 is located at the electrical connection keys on the passive device 301.
The second passivation layer 202 is formed on the front surface of the die, and a second passivation layer opening 2021 is formed on the second passivation layer 202, wherein the second passivation layer opening 2021 is located at a pad of the die 201.
The wiring structure comprises a wiring layer 206 and a third electrical connection portion 207 positioned on the wiring layer 206, a surface positioned on one side of the first protection layer 302 away from the passive element 301 and a surface positioned on one side of the second protection layer 202 away from the bare chip 201, and is used for leading out a bonding pad on the front surface of the bare chip 201 and an electrical connection key of the passive element 301.
In the semiconductor package structure of the present embodiment, the first and second protection layers on the surface of the passive device and the front surface of the die can protect the passive device and the front surface of the die, respectively.
In some embodiments, the passive element 301 in the semiconductor package structure is smaller than the die 201.
In some embodiments, the wiring layer 206 is electrically connected to the passive element 301 through the first electrical connection portion 2031 in the first protective layer opening 3021, and is electrically connected to the die 201 through the second electrical connection portion 2032 in the second protective layer opening 2021.
Further, the wiring structure may further include a dielectric layer 208. The dielectric layer 208 is formed on the wiring layer 206 and the exposed first passivation layer 302, the exposed second passivation layer 202, and the exposed encapsulating layer 204, and has a dielectric layer opening. The dielectric layer opening is provided with a third electrical connection portion 207 electrically connected to the wiring layer 206.
In another embodiment, the wiring structure includes more wiring layers to achieve multi-layer wiring of the product.
In the present embodiment, each structural element of the semiconductor package structure can refer to the related description of the corresponding structural element in the semiconductor package method, which is not repeated herein.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (10)

1. A semiconductor packaging method, comprising:
forming a first protective layer on the surface of the passive element with the electric connection key, and forming a first protective layer opening on the first protective layer; wherein the first protective layer opening corresponds to the electrical connection key of the passive component;
forming a second protection layer on the front surface of the bare chip to be packaged, and forming a second protection layer opening on the second protection layer; the front surface of the bare chip to be packaged is provided with a welding pad, and the opening of the second protective layer corresponds to the welding pad on the front surface of the bare chip to be packaged;
mounting the passive element and the bare chip to be packaged on a carrier plate at intervals; the front surface of the bare chip to be packaged faces the carrier plate, and the surface of the passive element with the electric connection keys faces the carrier plate;
and forming an encapsulating layer, wherein the encapsulating layer at least encapsulates the chip to be encapsulated and the passive element.
2. The semiconductor packaging method according to claim 1, wherein after forming the second protective layer on the front surface of the die to be packaged, before mounting the die to be packaged on the carrier board, the method comprises:
and thinning the bare chip to be packaged by grinding the back surface of the bare chip to be packaged.
3. The semiconductor packaging method of claim 1, wherein after forming the encapsulation layer, the method comprises:
and stripping the carrier plate.
4. The semiconductor packaging method of claim 3, wherein after peeling the carrier plate, the method comprises:
filling a first conductive medium in the first protective layer opening to form a first electric connection part, filling a second conductive medium in the second protective layer opening to form a second electric connection part, and forming wiring layers on the surface of the first protective layer far away from the passive element and the surface of the second protective layer far away from the bare chip; the wiring layer is electrically connected with the electric connecting keys of the passive element through the first electric connecting parts and is electrically connected with the welding pads on the front surface of the bare chip through the second electric connecting parts.
5. The semiconductor packaging method according to claim 4, wherein the first electrical connection portion, the second electrical connection portion, and the wiring layer are formed in the same conductive layer process; or the like, or, alternatively,
the first electrical connection portion and the second electrical connection portion are formed in the same conductive layer process, and the wiring layer is formed in another conductive layer process.
6. The semiconductor packaging method according to claim 1, wherein after forming a first passivation opening in the first passivation layer and forming a second passivation opening in the second passivation layer, the method comprises, before mounting the passive component and the die to be packaged on a carrier board:
and filling a second conductive medium in the second protective layer opening to form a second electric connection part which can be electrically connected with the welding pad on the front surface of the bare chip to be packaged.
7. The semiconductor packaging method of claim 6, wherein after forming the encapsulation layer, the semiconductor packaging method comprises:
stripping the carrier plate;
and forming wiring layers on the surfaces of the first protection layer far away from the passive element and the second protection layer far away from the bare chip, wherein the wiring layers are electrically connected with the electric connection keys of the passive element and the bonding pads on the front surface of the bare chip.
8. The semiconductor packaging method according to claim 4, 5, or 7, wherein after forming the wiring layer, the method further comprises:
and forming a third electric connection part on the surface of the wiring layer on the side far away from the bare chip and the passive element.
9. The semiconductor packaging method of claim 8, wherein after forming the third electrical connection, the method comprises:
and forming a dielectric layer on the wiring layer, wherein the dielectric layer can cover the exposed wiring layer, part of the third electric connection part and the exposed protective layer, and the surface of the third electric connection part, which is far away from the wiring layer, exposes the dielectric layer.
10. A semiconductor package, comprising:
the encapsulating layer is provided with a plurality of first cavities and second cavities which are spaced and inwards concave;
a passive element located within the first cavity;
a die located within the second cavity with a back side of the die facing a bottom of the second cavity;
the first protection layer is formed on the surface of the passive element with the electric connection keys, and a first protection layer opening is formed on the first protection layer and is positioned at the electric connection keys on the passive element;
the second protection layer is formed on the front surface of the bare chip, and a second protection layer opening is formed on the second protection layer and is positioned at the welding pad of the bare chip;
and the wiring structure comprises a wiring layer and a third electric connection part positioned on the wiring layer, is positioned on the surface of one side of the first protective layer, which is far away from the passive element, and is positioned on the surface of one side of the second protective layer, which is far away from the bare chip, and is used for leading out a welding pad on the front surface of the bare chip and an electric connection key of the passive element.
CN202010231981.6A 2020-03-27 2020-03-27 Semiconductor packaging method and semiconductor packaging structure Pending CN113725100A (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201043107A (en) * 2009-05-27 2010-12-01 Chuan-Ling Hu Package structure to integrate surface mount elements
CN107240761A (en) * 2016-03-28 2017-10-10 矽品精密工业股份有限公司 electronic package
CN110729270A (en) * 2019-03-04 2020-01-24 Pep创新私人有限公司 Chip packaging method and packaging structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201043107A (en) * 2009-05-27 2010-12-01 Chuan-Ling Hu Package structure to integrate surface mount elements
CN107240761A (en) * 2016-03-28 2017-10-10 矽品精密工业股份有限公司 electronic package
CN110729270A (en) * 2019-03-04 2020-01-24 Pep创新私人有限公司 Chip packaging method and packaging structure

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