CN111668123B

CN111668123B - Semiconductor packaging method

Info

Publication number: CN111668123B
Application number: CN201910177323.0A
Authority: CN
Inventors: 周辉星
Original assignee: SIPLP Microelectronics Chongqing Ltd
Current assignee: SIPLP Microelectronics Chongqing Ltd
Priority date: 2019-03-08
Filing date: 2019-03-08
Publication date: 2022-04-26
Anticipated expiration: 2039-03-08
Also published as: CN111668123A

Abstract

The application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps: mounting a plurality of chips to be packaged on a carrier plate, so that a plurality of mounting areas on which the chips to be packaged are mounted and a blank area surrounding the mounting areas are formed on the carrier plate; placing a mold frame in the blank area on the carrier plate, wherein the mold frame is of a closed structure, a plurality of hollow areas are arranged in the mold frame, and the hollow areas correspond to the mounting areas one by one; and forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is filled in the hollow area of the mold frame, and the encapsulating layer is used for encapsulating the plurality of chips to be encapsulated.

Description

Semiconductor packaging method

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method.

Background

The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the method comprises the steps of firstly, adhering the front side of a bare chip on a carrier plate through an adhesive tape, carrying out hot-press plastic package, then peeling the carrier plate, carrying out rewiring process on the front side of the bare chip to form a rewiring structure, and packaging.

As shown in fig. 1(a) -1 (c), in the thermal compression molding process, the molding resin material 1 moves vertically and leftwards and rightwards in the mold cavity under the action of the upper pressure plate 2 of the molding press, so that the molding resin material 1 is uniformly distributed and tightly pressed and cured on the surface of the carrier plate 3 to form the encapsulating layer 4, however, the left and right movement of the molding resin material 1 forms a horizontal acting force F on the bare chips 5 arranged on the carrier plate 3 according to the predetermined positions, and the pressure in the thermal compression molding process is very high, and the viscosity of the adhesive tape 6 is reduced under the high temperature environment, so that the bonding positioning capability of the bare chips 5 is reduced, and therefore, the bare chips 5 are easily moved under the pressure of the molding resin material 1 to deviate from the predetermined bonding positions.

Due to the offset phenomenon of the bare chip 5, it is difficult to position the bare chip 5 at the precise position in the carrier board 3 in the subsequent wiring process, which greatly affects the wiring process and even makes the wiring process difficult.

In particular, in a large carrier, since the carrier 3 has a large size and the molding resin material 1 moves under pressure in a wider range, the die 5 is subjected to a larger force F, so that the die 5 is more easily displaced, as shown in fig. 1(a) to 1 (c).

Therefore, in the large-scale panel-level packaging process, it is very important to solve the problem of die movement during the compression molding process, and the problem is a key factor for further enlarging the size of the panel-level package.

Disclosure of Invention

One aspect of the present application provides a semiconductor packaging method, including:

mounting a plurality of chips to be packaged on a carrier plate, so that a plurality of mounting areas on which the chips to be packaged are mounted and a blank area surrounding the mounting areas are formed on the carrier plate;

placing a mold frame in the blank area on the carrier plate, wherein the mold frame is of a closed structure, a plurality of hollow areas are arranged in the mold frame, and the hollow areas correspond to the mounting areas one by one;

and forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is filled in the hollow area of the mold frame, and the encapsulating layer is used for encapsulating the plurality of chips to be encapsulated.

Optionally, the material of the mold frame is the same as the material of the encapsulating layer.

Optionally, the height of the encapsulating layer is less than or equal to the height of the mold frame.

Optionally, the mold frame includes a frame body and a connection beam disposed in the frame body, both ends of the connection beam are connected to the frame body, the frame body is located in the blank area surrounding the outer peripheries of the plurality of mounting areas, and the connection beam is located in the blank area between the adjacent mounting areas;

the packaging layer is filled in the hollow area surrounded by the frame body and the connecting beam, or the packaging layer is filled in the hollow area surrounded by the frame body and the connecting beam, and the connecting beam.

Optionally, the size and the size of the hollow area are matched with the size and the size of the outer periphery of the mounting area; the size and the dimension of the mould frame are matched with the size and the dimension of the carrier plate.

Optionally, the manufacturing method of the mold frame comprises:

hot-pressing to form a bare board;

and cutting the bare board, wherein the cut area corresponds to the mounting area on the carrier board.

Optionally, in the manufacturing method of the mold frame, the hot press molding device for hot press molding the bare board is the same as the hot press molding device for forming the encapsulating layer in the semiconductor packaging method.

Optionally, before the mounting the plurality of chips to be packaged on the carrier, the method further includes:

and forming a protective layer on the front surface of each chip to be packaged.

Optionally, after forming the encapsulation layer, the method comprises:

stripping the carrier plate to expose the front surfaces of the chips to be packaged;

and forming a rewiring structure on the front surface of the chip to be packaged, wherein the rewiring structure is used for leading out the welding pad on the front surface of the chip to be packaged.

Optionally, after the forming of the encapsulating layer and before the peeling of the carrier plate, the method comprises attaching a support plate on a first surface of the encapsulating layer away from the carrier plate; and

after forming a rewiring structure on the front side of the chip to be packaged, the method comprises stripping the supporting plate.

According to the semiconductor packaging method provided by the embodiment of the application, the mold frame is arranged in the blank area on the carrier plate, and the moving area of the packaging material of the packaging layer is reduced from the large-scale area of the whole carrier plate to the small area divided by the hollow area on the mold frame, so that the moving range of the packaging material is reduced, the acting force of the packaging material on the chip to be packaged is reduced, the chip to be packaged and the carrier plate are prevented from generating relative displacement, and the packaging success rate and the product yield are ensured.

Drawings

Fig. 1(a) is a schematic structural view of a die in the prior art when the die is subjected to a force of movement of a molding resin material.

Fig. 1(b) is a schematic layout diagram of dies on a carrier board in the prior art.

FIG. 1(c) is a schematic view of a partial cross-sectional structure taken along the A-A direction in FIG. 1 (b).

Fig. 2 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure.

Fig. 3(a) -3 (g) are process flow diagrams of a semiconductor packaging method in an exemplary embodiment according to the present disclosure.

Fig. 4(a) is a schematic front structure diagram of a bare board according to an exemplary embodiment of the present disclosure.

Fig. 4(b) is a schematic front structure diagram of a mold frame according to an exemplary embodiment of the present disclosure.

Fig. 4(c) is a schematic front structure view of a mold frame according to another exemplary embodiment of the present disclosure.

Fig. 4(d) is a schematic front structure view of a mold frame according to still another exemplary embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of a semiconductor package structure with a support plate according to an exemplary embodiment of the present disclosure.

Fig. 6 is a schematic diagram of providing a protective layer on a surface of a wafer and dicing the wafer according to an exemplary embodiment of the disclosure.

Fig. 7 is a schematic structural diagram of a semiconductor package structure provided with a protective layer opening on a protective layer according to an exemplary embodiment of the disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

In the packaging process, after the front surface of the chip to be packaged is attached to the carrier plate, when the back surface of the chip to be packaged is packaged, a packaging layer is usually formed in a high-pressure high-temperature forming mode, and in the process, the left and right movement of the packaging material can form horizontal acting force on the chip to be packaged which is arranged on the carrier plate according to a preset position, so that the chip deviates from the preset bonding position to influence the later wiring process.

According to various embodiments of the present disclosure, a semiconductor packaging method is provided. In the packaging process, a plurality of chips to be packaged are attached to a carrier plate, so that a plurality of attaching areas where the chips to be packaged are attached and a blank area surrounding the attaching areas are formed on the carrier plate; placing a mold frame in the blank area on the carrier plate, wherein the mold frame is of a closed structure, a plurality of hollow areas are arranged in the mold frame, and the hollow areas correspond to the mounting areas one by one; and packaging the chip to be packaged on the carrier plate, namely covering the carrier plate with the packaging material of the packaging layer, and filling the packaging material into the hollow area of the mold frame to form the packaging layer. According to the above embodiment of the disclosure, the moving area of the encapsulating material of the encapsulating layer is reduced from the large area of the whole carrier plate to the small area divided by the hollow-out area of the mold frame, so that the movable range of the encapsulating material is reduced, the acting force of the encapsulating material on the chip to be packaged is reduced, and the chip to be packaged is prevented from moving in the pressurizing process. Furthermore, the die frame is arranged on the blank area, so that the acting force of the horizontal movement of the encapsulating material on the chip to be packaged around the blank area is balanced left and right, and the chip to be packaged is not easy to displace.

As shown in fig. 2, fig. 3(a) -fig. 3(g), fig. 4(a) -fig. 4(d), fig. 5, fig. 6 and fig. 7, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.

Fig. 2 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the semiconductor packaging method includes the steps of:

step 101: mounting a plurality of chips to be packaged on a carrier plate, so that a plurality of mounting areas on which the chips to be packaged are mounted and a blank area surrounding the mounting areas are formed on the carrier plate;

step 102: placing a mold frame in the blank area on the carrier plate, wherein the mold frame is of a closed structure, a plurality of hollow areas are arranged in the mold frame, and the hollow areas correspond to the mounting areas one by one;

step 103: and forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is filled in the hollow area of the mold frame, and the encapsulating layer is used for encapsulating the plurality of chips to be encapsulated.

In an embodiment, the shape of the carrier 200 may include: a circle, a rectangle, or other shapes, and the shape of the carrier 200 in this embodiment is a rectangle. The carrier 200 may be a large-sized stainless steel plate, a polymer substrate, or the like. The front surface of the chip to be packaged faces the carrier plate.

In step 101, as shown in fig. 3(a), after the front surfaces of the chips 201 to be packaged are mounted on the carrier 200, four mounting areas 2001 where the chips 201 to be packaged are mounted and a blank area 2002 surrounding the mounting areas 2001 are formed on the carrier 200, that is, the blank area 2002 is formed at the outer periphery of each mounting area 2001. The shape and number of the mounting areas 200 are designed according to the layout of the chips 201 to be packaged on the whole carrier 200, and the shape of the mounting areas 200 may include: circular, rectangular, or other shapes, not limited herein; the number of mounting areas 200 may be two, three, five, or other values.

Fig. 3(b) is a structural view of fig. 3(a) from another angle. As shown in fig. 3(b), the chip 201 to be packaged may be attached to the carrier 200 through an adhesive layer 203. And the adhesive layer 203 may be made of a material that is easily peeled off so as to peel off the carrier board 200 and the chip 201 to be packaged that is packaged on the back side, for example, a thermal release material that can be heated to lose its adhesiveness. The dashed lines in fig. 3(a) and 3(b) do not exist, and the labeling is only for convenience of understanding the technical solution in the embodiment.

In other embodiments, the adhesive layer 203 may have a two-layer structure, i.e., a thermal separation material layer and a die attach layer, the thermal separation material layer is attached to the carrier 200 and loses its viscosity when heated, so that the thermal separation material layer can be peeled off from the carrier 200, and the die attach layer has a viscous material layer and can be used for attaching the die 201 to be packaged. After the packaged chip 201 is peeled off from the carrier 200, the chip adhesion layer thereon may be removed by chemical cleaning. In one embodiment, the adhesive layer 203 may be formed on the carrier 200 by lamination, printing, or the like.

In another embodiment, as shown in fig. 3(c), a bonding position of the chip 201 to be packaged is preset on the carrier board 200, and after the adhesive layer 203 is formed, the front surface of the chip 201 to be packaged is bonded at a predetermined position B of the carrier board 200 toward the carrier board 200. In an embodiment, before the adhesive layer 203 is formed, a bonding position of the chip to be packaged may be identified in advance on the carrier 200 by using laser, mechanical patterning, photolithography, and the like, and the chip 201 to be packaged is also provided with an alignment mark to align with the bonding position on the carrier 200 during bonding. It should be noted that the protective layer may be transparent under a certain light so as to be able to see the alignment mark disposed on the chip 201 to be packaged, and to be able to accurately attach the chip 201 to be packaged at the predetermined position B. It can be understood that, in one packaging process, a plurality of chips 201 to be packaged may be provided, that is, a plurality of chips 201 to be packaged are simultaneously mounted on the carrier 200, packaged, and cut into a plurality of packages after the packaging is completed; one package body may include one or more chips to be packaged, and the positions of the chips to be packaged may be freely set according to the needs of an actual product.

In step 102, as shown in fig. 3(d), the mold frame 300 is placed in the blank area 2002 on the carrier 200, the mold frame 300 is a closed structure, four hollow areas 3001 are disposed in the mold frame 300, and the hollow areas 3001 correspond to the mounting areas 2001 one by one. That is, the mold frame 300 divides an area inside the mold frame 300 into four small areas by the hollowed-out area 3001. The size and dimension of the hollowed-out area 3001 match the size and dimension of the outer periphery of the mounting area 2001. The size and dimensions of the mold frame 300 are matched with those of the carrier plate 200. In this way, the mold frame 300 protects the plurality of chips 201 to be packaged disposed within the mold frame 300.

Specifically, the mold frame 300 includes a frame body 301, and a connection beam 302 disposed in the frame body 301, both ends of the connection beam 302 are connected to the frame body 301, the frame body 301 is located in a blank area 2002 surrounding the outer peripheries of the plurality of mounting areas 2001, and the connection beam 302 is located in the blank area 2002 between the adjacent mounting areas 2001. The frame 301 and the connecting beam 302 surround to form a hollow area 3001.

Fig. 3(e) is a structural view of another angle of fig. 3 (d). In fig. 3(e), the front surface of the chip 201 to be packaged is attached to the carrier 200, and is attached to the carrier 200 to form a mounting area 2001, and the front surface of the chip 201 to be packaged is connected to the carrier 200 through the adhesive layer 203. The mold frame 300 is placed on a blank area 2002 formed on the carrier 200 around the mounting area 2001.

In the actual processing process, the placement position of the mold frame 300 may be pre-identified on the carrier 200 by using laser, mechanical patterning, photolithography, or the like. Meanwhile, the mold frame 300 is also provided with an alignment mark for aligning with the placement position of the carrier 200 during placement.

In addition, the blank area 2002 on the carrier 200 through the mold frame 300 can also increase the mechanical strength of the carrier 200 due to the frame structure of the mold frame 300, so that the carrier 200 is not easily deformed in the following packaging process, and adverse effects caused by deformation of each structure are effectively inhibited, thereby improving the product packaging effect. The widths of the frame body 301 and the connecting beam 302 of the mold frame 300 can be adjusted according to different requirements, and in this embodiment, the widths of the frame body 301 and the connecting beam 302 of the mold frame 300 are both less than 25 mm.

The shape of the mold frame 300 and its layout on the entire carrier 200 may be designed according to the specific size of the carrier 200 and the specific zoning arrangement of the carrier 200.

In step 103, as shown in fig. 3(f), an encapsulating layer 204 is formed on the back surface of the chip 201 to be packaged and the exposed carrier 200, and the encapsulating layer 204 is filled in the hollow area 3001 of the mold frame 300. Specifically, the encapsulating layer 204 is filled in the hollow area 3001 surrounded by the frame 301 and the connecting beam 302. In this way, the moving area of the encapsulating material of the encapsulating layer 204 is reduced from the large area of the whole carrier 200 to the small area divided by the hollow area 3001 of the mold frame 300, so that the movable range of the encapsulating material is reduced, the acting force of the encapsulating material on the chip 201 to be packaged is reduced, and the chip 201 to be packaged is prevented from moving in the pressurizing process.

In one embodiment, the height of the encapsulating layer 204 is equal to the height of the mold frame 300. Specifically, the height of the encapsulating layer 204 is equal to the height of the frame body 301 of the mold frame 300; the height of the encapsulating layer 204 is equal to the height of the connecting beams 302 of the mold frame 300. Thus, when the encapsulating layer 204 is filled into the hollow area 3001 surrounded by the frame body 301 and the connecting beam 302, the mold frame 300 can play a good role in blocking the movement of the encapsulating material. In other embodiments, the height of the encapsulating layer 204 may also be less than the height of the mold frame 300. Specifically, the height of the encapsulating layer 204 may also be less than the height of the frame 301 of the mold frame 300, and the height of the encapsulating layer 204 may also be less than the height of the connecting beam 302 of the mold frame 300, so that the mold frame 300 can also well block the movement of the encapsulating material.

The encapsulating layer 204 is used to completely encapsulate the carrier 200 and the chip 201 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 200 is peeled off, the re-wiring and packaging can be continued on the reconstructed flat plate structure.

The encapsulating layer 204 includes a first surface 2041 opposite to the carrier 200, and is substantially flat and parallel to the surface of the carrier 200. The thickness of the encapsulating layer 204 may be thinned by grinding or polishing the first surface 2041, and in an alternative embodiment, the height of the encapsulating layer 204 may be thinned to the back side of the chip 201 to be packaged.

As shown in fig. 3(g), after forming the encapsulating layer 204 in step 103, the method includes peeling off the carrier board to expose the front surfaces of the chips 201 to be packaged.

The carrier board 200 can be mechanically peeled off directly. If the adhesive layer 203 between the carrier 200 and the front surface of the chip 201 to be packaged has a thermal separation material, the thermal separation material on the adhesive layer 203 may be heated to reduce its viscosity, so as to peel off the carrier 200. After the carrier board 200 is peeled off, the lower surface of the encapsulating layer 203 facing the carrier board 200 and the front surface of the chip 201 to be packaged are exposed. After the carrier 200 is peeled off, a flat plate structure including the chip 201 to be packaged and the encapsulating layer 204 encapsulating the back surface of the chip 201 to be packaged is obtained. The flat plate structure thus formed may be subjected to rewiring or the like according to the actual situation.

In the disclosed embodiment, the mold frame 300 is made of the same material as the encapsulating layer 204. Thus, the mold frame 300 and the encapsulating layer 204 have the same thermal expansion coefficient and other physical and chemical properties.

Since the mold frame 300 and the encapsulating layer 204 are made of the same material during the formation of the encapsulating layer 204, they can be melted together at the end of the high pressure and high temperature forming process.

The encapsulating layer 204 may be formed by laminating an epoxy resin film or abf (ajinomoto build film), or may be formed by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.

Before the mold frame 300 is placed on the blank area 2002 on the carrier 200, the mold frame 300 may be fabricated in the same manner as the encapsulating layer 204 is formed. The same hot press molding equipment is adopted, the same hot press parameters as those of the packaging encapsulation layer 204 are adopted to prepare a blank bare board 303, and after the bare board 303 is cured, the bare board 303 is cut into a required shape. Specifically, the manufacturing method of the mold frame 300 includes:

a bare board 303 is hot press molded as shown in fig. 4 (a);

the bare board 303 is cut out, and the cut-out area corresponds to the mounting area 2001 on the carrier board 200.

When the mold frame 300 is manufactured, the cut-out area on the bare board 303 forms a hollow area 3001 in fig. 4(b), and the hollow area 3001 corresponds to the mounting area 2001 on the carrier 200, so as to divide the plastic packaging area of the whole carrier 200 into a plurality of small mounting areas 2001 by using the mold frame 300. The shape of the mold frame 300 and its layout on the entire carrier 200 may be designed according to the specific size of the carrier 200 and the specific zoning arrangement of the carrier 200. As shown in fig. 4(b), the number of mounting areas is four, and four hollow areas 3001 are correspondingly provided. In another embodiment, as shown in fig. 4(c), the number of mounting areas is six, and six hollow areas 3001 are correspondingly provided.

In another embodiment, as shown in fig. 4(d), the number of mounting areas is nine, and nine hollow areas 3001 are correspondingly disposed. In addition to the frame 301 and the connecting beam 30 forming the hollow area 3001, the connecting beam 302 and the connecting beam 302 also surround the hollow area 3001 in the middle area in the drawing.

In some embodiments, the semiconductor packaging method further comprises: before step 101, i.e. before the chip to be packaged is attached to the carrier, a protective layer may be formed on the front surface of the chip to be packaged. The protective layer may be formed on the front surface of the semiconductor wafer before the semiconductor wafer is cut into a plurality of chips to be packaged, and then the semiconductor wafer is cut to obtain the chips to be packaged with the protective layer formed on the front surface. It is understood that, when the process allows, the protective layer may be formed on the front surface of each chip to be packaged after the semiconductor wafer is cut into the chips to be packaged, which is selected according to the actual situation.

As shown in fig. 5, a protection layer 202 is formed on the front surface of the semiconductor wafer 100, i.e. the surface corresponding to the front surface of the to-be-packaged chip 201, and then the semiconductor wafer 100 with the protection layer 202 formed thereon is cut along the cutting streets to obtain a plurality of to-be-packaged chips 201 with protection layers formed thereon. The chip 201 to be packaged, which has the protection layer 202 formed on the front surface, can also be attached to the carrier 200 through the adhesive layer 203.

The protection layer 202 is made of an insulating material, such as polyimide, epoxy resin, abf (ajinomoto build film), pbo (polybenzoxazole), and the like. Alternatively, the material of the protective layer is selected to be insulating and capable of accommodating chemical cleaning, polishing, and the like. The protective layer may be formed on the semiconductor wafer by Lamination (Coating), Coating (Coating), Printing (Printing), and the like.

When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material is easy to penetrate between the carrier 200 and the chip 201 to be encapsulated in the process. By forming a protective layer 202 outside the chip 201 to be packaged, the protective layer 202 can prevent the encapsulating material from penetrating into the surface of the chip 201 to be packaged, and even if the encapsulating material penetrates into the surface, the surface of the protective layer 202 can be directly processed in a chemical mode or a grinding mode after being peeled off from the carrier plate, so that the surface can not directly contact with the front surface of the chip 201 to be packaged, and further the circuit structure on the front surface of the chip 201 to be packaged can not be damaged.

Further, after the carrier 200 is peeled off, the protection layer 202 is correspondingly exposed.

In the embodiment where the protection layer 202 is formed on the front surface of the chip 201 to be packaged, the carrier 200 may also be directly and mechanically peeled off. If the adhesive layer 203 between the carrier plate 200 and the protective layer 202 has a thermal release material, the thermal release material on the adhesive layer 203 can be heated to reduce its viscosity after being heated, so as to peel off the carrier plate 200. After the carrier board 200 is peeled off, the lower surface of the encapsulating layer 203 and the protective layer 202 facing the carrier board 200 are exposed. After the carrier 200 is peeled off, a flat plate structure including the chip 201 to be packaged, the protection layer 202 covering the front surface of the chip 201 to be packaged, and the encapsulating layer 204 encapsulating the back surface of the chip 201 to be packaged is obtained. The flat plate structure thus formed may be subjected to rewiring or the like according to the actual situation.

In the embodiment of the disclosure, after the carrier board 200 is peeled off, the surfaces of the protection layer 202 and the encapsulation layer 204 are exposed, and at this time, the chip adhesion layer in the adhesive layer 202 is also present on the surfaces of the protection layer 202 and the encapsulation layer 204, and when the chip adhesion layer is removed by a chemical method, the protection layer 202 can also protect the surface of the chip to be packaged from being damaged; after the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; if the protective layer is not provided, the surface of the chip to be packaged cannot be processed in a chemical mode or a grinding mode so as to avoid damaging a circuit on the front surface of the chip to be packaged.

Next, as shown in fig. 6, in an embodiment in which a protection layer 202 is formed on the front surface of the chip 201 to be packaged, after the carrier 200 is peeled off, a protection layer opening 2021 may be formed on the protection layer 202 at a position corresponding to a plurality of pads of the chip 201 to be packaged, where each protection layer opening 2021 is at least correspondingly located on a pad of the chip 201 to be packaged or a line led out from the pad, so that the pad on the front surface of the chip 201 to be packaged or the line led out from the pad is exposed from the protection layer opening 2021. If the material of the protective layer is a laser-reactive material, the protective layer can be opened by forming one protective layer opening 2021 at a time by laser patterning; if the passivation layer is made of a photosensitive material, a plurality of passivation openings 2021 may be formed at a time by photolithography and patterning. The shape of the passivation opening 2021 may be round, but may also be other shapes such as oval, square, linear, etc.

Further, after the protective layer opening 2021 is formed, re-wiring may be performed on the protective layer 202 of the chip 201 to be packaged, that is, a re-wiring structure is formed. The front surface of the chip 201 to be packaged is provided with bonding pads of a circuit inside the chip, and the bonding pads can be led out by re-wiring on the front surface of the chip 201 to be packaged. The rewiring structure includes: the first redistribution layer is formed on the passivation layer 202 and the exposed encapsulation layer 204, and is electrically connected to the pads of the chip 201 through the passivation layer opening 2021.

The redistribution layer may further include a front side encapsulation layer formed on the first redistribution layer and the exposed passivation layer 202 and the exposed encapsulation layer 204, and the front side encapsulation layer has an opening. A conductive pillar electrically connected to the first redistribution layer is disposed in the opening to lead out a pad on the front surface of the chip 201.

Further, in an embodiment, the re-wiring may be repeated on the front side of the chip 201, for example, a second re-wiring layer or more re-wiring layers may be formed outside the front side encapsulation layer in the same manner to achieve multi-layer re-wiring of the product.

It should be noted that, when the chip 201 to be packaged is packaged, the rewiring may be performed on the front surface of the chip 201 to be packaged after the carrier 200 is peeled off, so as to form a rewiring structure. Of course, the rewiring structure may also be formed by rewiring the front surface of the chip 201 to be packaged before the chip 201 to be packaged is attached to the carrier 200. The re-routing structure may also include one or more re-routing layers. In the embodiment where the front surface of the chip 201 to be packaged is provided with or without a protective layer, the rewiring may be performed before the chip 201 to be packaged is attached to the carrier. The related operations of the specific rewiring can refer to the related descriptions above, and are not described herein.

Further, in the case that a plurality of chips 201 to be packaged are packaged together, after the packaging is completed, the whole package structure may be cut into a plurality of packages by laser or mechanical cutting, so as to form a package structure with a single chip.

In some embodiments, after the step 103 and before the carrier sheet 200 is peeled off, the packaging method further comprises attaching a support plate 205 on the encapsulating layer 204 away from the first surface 2041 of the carrier sheet.

The support plate is attached to at least a portion of the first surface of the envelope layer. As shown in fig. 7, in an embodiment, the supporting board 205 is mounted on the first surface 2041 of the encapsulating layer 204, and the supporting board 205 covers the entire area of the first surface 2041 of the encapsulating layer 204.

The material strength of the supporting plate 205 is greater than that of the encapsulating layer 204, so that the supporting plate 205 can effectively improve and ensure the mechanical strength of the encapsulating structure in the encapsulating process, and effectively inhibit adverse effects caused by deformation of each structure, thereby improving the product encapsulating effect.

Accordingly, in the present embodiment, the carrier 200 may be peeled off after the supporting board 205 is mounted, so as to expose the front surfaces of the chips 201 to be packaged.

Subsequently, after forming the rewiring structure on the front surface of the chip 201 to be packaged, the semiconductor packaging method further includes peeling the support plate 205. Can effectively improve and guarantee packaging structure's among the encapsulation process mechanical strength through setting up the backup pad, effectively restrain the adverse effect that each structural deformation brought to improve the effect of product encapsulation.

In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor packaging method, comprising:

forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is filled in the hollow area of the mold frame, and the encapsulating layer is used for encapsulating the plurality of chips to be encapsulated;

the height of the encapsulating layer is less than or equal to that of the mold frame;

the material of the mould frame is the same as that of the encapsulating layer, and at the end of the high-temperature high-pressure forming process, the mould frame and the encapsulating layer are fused into a whole.

2. The semiconductor packaging method according to claim 1, wherein the mold frame includes a frame body, and a connection beam provided in the frame body, both ends of the connection beam being connected to the frame body, the frame body being located in the empty space around the outer peripheries of the mounting areas, the connection beam being located in the empty space between the adjacent mounting areas;

3. The semiconductor packaging method according to claim 1, wherein the size and the dimension of the hollow area match with the size and the dimension of the outer periphery of the mounting area; the size and the dimension of the mould frame are matched with the size and the dimension of the carrier plate.

4. The semiconductor packaging method of claim 1, wherein the manufacturing method of the mold frame is:

hot-pressing to form a bare board;

5. The semiconductor packaging method according to claim 4, wherein the thermal compression molding equipment for the thermal compression molding of the bare board in the manufacturing method of the mold frame is the same as the thermal compression molding equipment for forming the encapsulating layer in the semiconductor packaging method.

6. The semiconductor packaging method according to claim 1, wherein before the mounting the plurality of chips to be packaged on the carrier, the method further comprises:

7. The semiconductor packaging method of any one of claims 1-6, wherein after forming the encapsulation layer, the method comprises:

8. The method of claim 7, wherein after the forming the encapsulation layer and before the peeling the carrier, the method comprises attaching a support plate to a first surface of the encapsulation layer remote from the carrier; and