CN111668111B - Semiconductor packaging method - Google Patents

Semiconductor packaging method Download PDF

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Publication number
CN111668111B
CN111668111B CN201910176974.8A CN201910176974A CN111668111B CN 111668111 B CN111668111 B CN 111668111B CN 201910176974 A CN201910176974 A CN 201910176974A CN 111668111 B CN111668111 B CN 111668111B
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chip
packaged
layer
front surface
carrier plate
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CN111668111A (en
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周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/811—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/81101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a bump connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method, which comprises the following steps: the front surface of the chip to be packaged is attached to the carrier plate, so that an attaching area where the chip to be packaged is attached and a blank area surrounding the attaching area are formed on the carrier plate; placing two conductive blocks in a blank area on the carrier plate, wherein the two conductive blocks are oppositely arranged on two sides of the mounting area; forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the chip to be encapsulated and the conductive blocks; stripping the carrier plate to expose the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer; forming a metal structure on the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer; arranging a plurality of clamps on the front surface of each conductive block, wherein the clamps on the two conductive blocks are arranged in a one-to-one correspondence manner; and carrying out an electroplating process, forming a trace structure after patterning the metal structure, wherein the trace structure is used for leading out a welding pad on the front side of the chip to be packaged.

Description

Semiconductor packaging method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the method comprises the steps of firstly, bonding the front surface of a bare chip on a carrier plate through an adhesive tape, carrying out hot-press plastic package, then stripping the carrier plate, forming a trace structure on the front surface of the bare chip, and carrying out packaging.
When the trace structure is formed by adopting an electroplating process, copper blocks are respectively arranged on the left side and the right side of the structure to be electroplated to serve as electrodes, a clamp is arranged on each copper block, the copper block on the left side is electrically connected with the clamp on the left side, the copper block on the right side is electrically connected with the clamp on the right side, and current enters the copper blocks through the clamps and then enters the area to be electroplated to carry out the electroplating process. However, since only one jig is provided on the copper block as an electrode, only point contact can be made between the jig and the copper block, and current cannot flow uniformly from the jig on the left side to the jig on the right side, that is, current does not flow uniformly over the entire area to be plated, resulting in a low quality of a formed trace structure. In addition, the point contact current formed by the single clamp is also liable to damage the copper block as an electrode.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, comprising:
mounting the front surface of a chip to be packaged on a carrier plate to form a mounting area on which the chip to be packaged is mounted and a blank area surrounding the mounting area on the carrier plate;
placing two conductive blocks on the blank area on the carrier plate, wherein the two conductive blocks are oppositely arranged on two sides of the mounting area;
forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the chip to be encapsulated and the conductive blocks;
stripping the carrier plate to expose the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer;
forming a metal structure on the front surface of the chip to be packaged, the front surface of the conductive block and the first surface of the encapsulating layer;
arranging a plurality of clamps on the front surface of each conductive block, wherein the clamps on the two conductive blocks are arranged in a one-to-one correspondence manner;
and carrying out an electroplating process, wherein a trace structure is formed after the metal structure is patterned, and the trace structure is used for leading out a welding pad on the front side of the chip to be packaged.
Optionally, a plurality of the clamps on the front surface of the same conductive block are arranged at equal intervals.
Optionally, after the providing the plurality of jigs and before the performing the electroplating process, the method includes: the metal structure is provided with an insulating frame, the insulating frame is a closed frame structure surrounding the chip to be packaged, and the insulating frame is located between the chip to be packaged and the clamp.
Optionally, the insulating frame is made of rubber.
Optionally, the conductive block is made of copper.
Optionally, the metal structure includes a seed layer and a metal layer, and the seed layer is formed on the front surface of the chip to be packaged, the front surface of the conductive block, and the first surface of the encapsulating layer; the metal layer is formed on the seed layer.
Optionally, before the chip to be packaged is mounted on the carrier, the method further includes:
and forming a protective layer on the front surface of each chip to be packaged.
Optionally, after the forming of the encapsulating layer and before the peeling of the carrier plate, the method comprises:
and a supporting layer is pasted on the second surface of the encapsulating layer far away from the carrier plate.
Optionally, after forming the trace structure on the front side of the chip to be packaged, the method includes:
and stripping the supporting layer.
According to the semiconductor packaging method provided by the embodiment of the application, the plurality of corresponding clamps are arranged on the two conductive blocks, so that one surface contact is formed between the clamps and the conductive blocks, current can uniformly flow from the clamps to the conductive blocks and then further enters the structure to be electroplated, the uniform flow of the current in the whole region to be electroplated is ensured, the quality of the formed trace structure is ensured, and the packaging success rate and the product yield are ensured.
Drawings
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 2(a) -2 (n) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic diagram of providing a protective layer on a surface of a wafer and dicing the wafer according to an exemplary embodiment of the disclosure.
Fig. 4 is a schematic structural diagram of a semiconductor package structure having a support layer according to an exemplary embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
According to various embodiments of the present disclosure, a semiconductor packaging method is provided. In the packaging process, the front surface of a chip to be packaged is attached to a carrier plate, and the front surface of the chip to be packaged is attached to the carrier plate, so that a mounting area where the chip to be packaged is mounted and a blank area surrounding the mounting area are formed on the carrier plate;
placing two conductive blocks on the blank area on the carrier plate, wherein the two conductive blocks are oppositely arranged on two sides of the mounting area; forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the chip to be encapsulated and the conductive blocks; stripping the carrier plate to expose the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer; forming a metal structure on the front surface of the chip to be packaged, the front surface of the conductive block and the first surface of the encapsulating layer; arranging a plurality of clamps on the front surface of each conductive block, wherein the clamps on the two conductive blocks are arranged in a one-to-one correspondence manner; and carrying out an electroplating process, wherein a trace structure is formed after the metal structure is patterned, and the trace structure is used for leading out a welding pad on the front side of the chip to be packaged. According to the above embodiment of the present disclosure, the plurality of corresponding clamps are disposed on the two conductive blocks, so that a surface contact is formed between the clamp and the conductive block, and a current can uniformly flow from the clamp to the conductive block, and then further enter the structure to be plated, so as to ensure uniform flow of the current in the whole region to be plated, thereby ensuring the quality of the formed trace structure, and ensuring the success rate of packaging and the yield of products.
As shown in fig. 1, 2(a) -2 (n), 3 and 4, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: mounting the front surface of a chip to be packaged on a carrier plate to form a mounting area on which the chip to be packaged is mounted and a blank area surrounding the mounting area on the carrier plate;
step 102: placing two conductive blocks on the blank area on the carrier plate, wherein the two conductive blocks are oppositely arranged on two sides of the mounting area;
step 103: forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the chip to be encapsulated and the conductive blocks;
step 104: stripping the carrier plate to expose the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer;
step 105: forming a metal structure on the front surface of the chip to be packaged, the front surface of the conductive block and the first surface of the encapsulating layer;
step 106: arranging a plurality of clamps on the front surface of each conductive block, wherein the clamps on the two conductive blocks are arranged in a one-to-one correspondence manner;
step 107: and carrying out an electroplating process, wherein a trace structure is formed after the metal structure is patterned, and the trace structure is used for leading out a welding pad on the front side of the chip to be packaged.
In this embodiment, before step 101, that is, before the chip to be packaged is mounted on the carrier, a protection layer may be formed on the front surface of the chip to be packaged. The protective layer may be formed on the front surface of the semiconductor wafer before the semiconductor wafer is cut into a plurality of chips to be packaged, and then the semiconductor wafer is cut to obtain the chips to be packaged with the protective layer formed on the front surface. It is understood that, when the process allows, the protective layer may be formed on the front surface of each chip to be packaged after the semiconductor wafer is cut into the chips to be packaged, which is selected according to the actual situation.
As shown in fig. 2(a), a protection layer 202 is formed on the front surface of the semiconductor wafer 100, i.e. the surface corresponding to the front surface of the to-be-packaged chip 201, and then the semiconductor wafer 100 on which the protection layer 202 is formed is cut along the cutting streets a to obtain a plurality of to-be-packaged chips 201 on which the protection layer 202 is formed.
The protection layer 202 is made of an insulating material, such as polyimide, epoxy resin, abf (ajinomoto build film), pbo (polybenzoxazole), and the like. Alternatively, the material of the protective layer is selected to be insulating and capable of accommodating chemical cleaning, polishing, and the like. The protective layer may be formed on the semiconductor wafer by Lamination (Coating), Coating (Coating), Printing (Printing), and the like.
In step 101, as shown in fig. 2(b), after the front surface of the chip 201 to be packaged is mounted on the carrier 200, a mounting area 2001 where the chip 201 to be packaged is mounted and a blank area 2002 surrounding the mounting area 2001 are formed on the carrier 200. The shape of the mounting area 200 is designed according to the layout of the chip 201 to be packaged on the whole carrier 200, and the shape of the mounting area 200 may include: circular, rectangular, or other shapes, and are not limited herein. The number of mounting areas 200 is not limited herein.
Fig. 2(c) is a schematic view of the structure of fig. 2(b) at another angle. As shown in fig. 2(c), the chip 201 to be packaged, which has the protection layer 202 formed on the front surface, can be attached to the carrier 200 through the adhesive layer 203. And the adhesive layer 203 may be made of a material that is easily peeled off so as to peel off the carrier board 200 and the chip 201 to be packaged that is packaged on the back side, for example, a thermal release material that can be heated to lose its adhesiveness. The dashed lines in fig. 2(b) and 2(c) do not exist, and the labeling is only for convenience of understanding the technical solution in the embodiment.
In other embodiments, the adhesive layer 203 may have a two-layer structure, i.e., a thermal separation material layer and a die attach layer, the thermal separation material layer is attached to the carrier 200 and loses its viscosity when heated, so that the thermal separation material layer can be peeled off from the carrier 200, and the die attach layer has a viscous material layer and can be used for attaching the die 201 to be packaged. After the packaged chip 201 is peeled off from the carrier 200, the chip adhesion layer thereon may be removed by chemical cleaning. In one embodiment, the adhesive layer 203 may be formed on the carrier 200 by lamination, printing, or the like.
In another embodiment, as shown in fig. 2(d), a bonding position of the chip 201 to be packaged is preset on the carrier board 200, and after the adhesive layer 203 is formed, the front surface of the chip 201 to be packaged is bonded at a predetermined position B of the carrier board 200 toward the carrier board 200. In an embodiment, before the adhesive layer 203 is formed, a bonding position of the chip to be packaged may be identified in advance on the carrier 200 by using laser, mechanical patterning, photolithography, and the like, and the chip 201 to be packaged is also provided with an alignment mark to align with the bonding position on the carrier 200 during bonding. It should be noted that the protective layer may be transparent under a certain light so as to be able to see the alignment mark disposed on the chip 201 to be packaged, and to be able to accurately attach the chip 201 to be packaged at the predetermined position B. It can be understood that, in one packaging process, a plurality of chips 201 to be packaged may be provided, that is, the chips 201 to be packaged are simultaneously mounted on the carrier 200, packaged, and cut into a plurality of packages after the packaging is completed; one package body may include one or more chips to be packaged, and the positions of the chips to be packaged may be freely set according to the needs of an actual product.
In step 102, as shown in fig. 2(e), two conductive blocks 300 are placed in the blank area 2002 on the carrier 200, and the two conductive blocks 300 are oppositely disposed on two sides of the mounting area 2001. The material of the conductive block 300 is copper, but is not limited to copper, and may be other metal materials or materials with conductive properties.
Fig. 2(f) is a schematic structural view of fig. 2(e) at another angle. In fig. 2(f), the chip 201 to be packaged, which has the protective layer 202 formed on the front surface, is attached to the carrier 200, and is attached to the carrier 200 to form the attachment area 2001, and the front surface of the chip 201 to be packaged and the carrier 200 are connected by the adhesive layer 203. The conductive blocks 300 are disposed in the blank area 2002 of the carrier 200, and the two conductive blocks 300 are oppositely disposed on two sides of the mounting area 2001.
In the actual processing process, the placing positions of the conductive bumps 300 can be identified in advance on the carrier 200 by using laser, mechanical patterning, photolithography, and the like. Meanwhile, the conductive block 300 is also provided with an alignment mark for aligning with the placement position on the carrier 200 during placement.
In addition, the blank area 2002 for placing the conductive block 300 on the carrier 200 can also increase the mechanical strength of the carrier 200, so that the carrier 200 is not easily deformed in the following packaging process, and adverse effects caused by deformation of various structures are effectively inhibited, thereby improving the product packaging effect. The width of the conductive block 300 can be adjusted according to different requirements. The shape of the conductive block 300 and its layout on the whole carrier 200 can be designed according to the specific size of the carrier 200 and the specific partition arrangement of the carrier 200.
In step 103, as shown in fig. 2(g), an encapsulating layer 204 is formed on the back surface of the chip 201 to be packaged, the back surfaces of the conductive bumps 300, and the exposed carrier 200, and the encapsulating layer 204 is used to completely encapsulate the carrier 200 and the chip 201 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 200 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure.
The encapsulating layer 204 includes a first surface 2041 adjacent to the carrier 200 and a second surface 2042 opposite to the first surface 2041, and the encapsulating layer 204 is substantially flat and parallel to the surface of the carrier 200. Specifically, the first surface 2041 of the encapsulating layer 204 is connected with the adhesive layer 203 on the carrier board 200. The thickness of the encapsulating layer 204 may be thinned by grinding or polishing the second surface 2042, and in an alternative embodiment, the height of the encapsulating layer 204 may be thinned to the back side of the chip 201 to be packaged.
In step 104, as shown in fig. 2(h), after the encapsulating layer 204 is formed, the carrier board 200 is peeled off to expose the protection layer 202 on the front surface of the chip 201 to be packaged, the front surfaces of the conductive bumps 300, and the first surface 2041 of the encapsulating layer 204.
The carrier board 200 can be mechanically peeled off directly. If the adhesive layer 203 has a thermal release material, the thermal release material on the adhesive layer 203 can be heated to reduce its viscosity after being heated, so as to peel off the carrier sheet 200. After the carrier board 200 is peeled off, the first surface 2041 of the encapsulating layer 203 facing the carrier board 200, the protective layer 202 of the front surface of the chip 201 to be packaged, and the front surfaces of the conductive bumps 300 are exposed. After the carrier board 200 is peeled off, a flat plate structure including the chip 201 to be packaged, the conductive block 300, and the encapsulating layer 204 encapsulating the back surfaces of the chip 201 to be packaged and the conductive block 300 is obtained.
In the embodiment of the present disclosure, the encapsulating layer 204 may be formed by laminating an epoxy resin film or abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.
When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material is easy to penetrate between the carrier 200 and the chip 201 to be encapsulated in the process. By forming a protective layer 202 on the front surface of the chip 201 to be packaged, the protective layer 202 can prevent the encapsulating material from penetrating into the surface of the chip 201 to be packaged, and even if the encapsulating material penetrates into the surface, the surface of the protective layer 202 can be directly processed in a chemical manner or a grinding manner after being peeled off from the carrier plate, so that the surface of the chip 201 to be packaged can not be directly contacted, and the circuit structure on the front surface of the chip 201 to be packaged can not be damaged.
In addition, after the carrier board 200 is peeled off, the surfaces of the protection layer 202 and the encapsulation layer 204 are exposed, and at this time, the chip adhesion layer in the adhesive layer 202 is also present on the first surfaces 2041 of the protection layer 202 and the encapsulation layer 204, and when the chip adhesion layer is removed by a chemical method, the protection layer 202 can also protect the surface of the chip to be packaged from being damaged; after the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; if the protective layer is not provided, the surface of the chip to be packaged cannot be processed in a chemical mode or a grinding mode so as to avoid damaging a circuit on the front surface of the chip to be packaged.
Next, as shown in fig. 2(i), in an embodiment in which a protection layer 202 is formed on the front surface of the chip 201 to be packaged, after the carrier 200 is peeled off, the whole flat plate structure to be plated is turned over, and protection layer openings 2021 are formed on the protection layer 202 at positions corresponding to the pads of the chip 201 to be packaged, where each protection layer opening 2021 is at least correspondingly located on the pad of the chip 201 to be packaged or a line led out from the pad, so that the pad on the front surface of the chip 201 to be packaged or the line led out from the pad is exposed from the protection layer opening 2021. If the material of the protective layer is a laser-reactive material, the protective layer can be opened by forming one protective layer opening 2021 at a time by laser patterning; if the passivation layer is made of a photosensitive material, a plurality of passivation openings 2021 may be formed at a time by photolithography and patterning. The shape of the passivation opening 2021 may be round, but may also be other shapes such as oval, square, linear, etc.
In step 105, as shown in fig. 2(j), after forming the passivation opening 2021, a metal structure 400 is formed on the front surface of the chip 201 to be packaged, the front surfaces of the conductive bumps 300, and the first surface 2041 of the encapsulating layer 204. The metal structure 400 includes a seed layer 401 and a metal layer 402, wherein the seed layer 401 is formed on the front surface of the chip 201 to be packaged, the front surfaces of the conductive blocks 300, and the first surface 2041 of the encapsulating layer 204. A metal layer 402 is formed on the seed layer 401.
As shown in fig. 2(k), in step 106, a plurality of jigs 500 are disposed on the front surface of each conductive block 300, and the jigs 500 on two conductive blocks 300 are disposed in a one-to-one correspondence. The plurality of jigs 500 positioned on the front surface of the same conductive block 300 are arranged at equal intervals. In the present disclosure, by providing a plurality of corresponding jigs 500 at each of two conductive blocks 300, one-sided contact is formed between the jigs 500 and the conductive blocks 300; allowing current to flow uniformly from the jig 500 to the conductive block 300 and then further into the interior of the planar structure to be plated ensures uniform flow of current throughout the area to be plated, thereby ensuring the quality of the resulting trace structure. In addition, the current path through the contact of the surface enters the conductive block as an electrode, which can also prolong the life of the conductive block. The arrangement of the plurality of jigs 500 at equidistant intervals can further ensure uniform flow of current throughout the area to be plated. In the present embodiment, the number of the jigs 500 on each conductive block 300 is five, but is not limited to five, and more than two jigs 500 may be provided according to design requirements.
Next, in an embodiment, as shown in fig. 2(k), the method further includes: an insulating frame 600 is disposed on the metal structure 400, the insulating frame 600 is a closed frame structure disposed around the chip 201 to be packaged, and the insulating frame 600 is disposed between the chip 201 to be packaged and the fixture 500. In this way, the chip 201 to be packaged and the fixture 500 can be insulated by the insulating frame 600, and current can be ensured to enter the interior of the flat plate structure to be electroplated only through the conductive block 300. In the present embodiment, the insulating frame is made of rubber, but is not limited thereto, and may be made of other materials having an insulating function.
In step 107, as shown in fig. 2(l), an electroplating process is performed, and after the metal structure 400 is patterned, a trace structure 700 is formed, where the trace structure 700 is used to lead out a pad on the front side of the chip 201 to be packaged. The front surface of the chip 201 to be packaged has pads of the internal circuit of the chip, and the pads can be led out by forming the trace structure 700 on the front surface of the chip 201 to be packaged. Fig. 2(m) is a schematic view of the structure at another angle in fig. 2 (l).
Fig. 2(n) is an enlarged schematic view of a portion C in fig. 2 (m). As can be seen in fig. 2(n), the current I may flow uniformly from the jig 500 to the conductive block 300 and then further into the interior of the flat plate structure to be plated.
In another embodiment, the trace structure may include: the first redistribution layer is formed on the passivation layer 202 and the exposed encapsulation layer 204, and is electrically connected to the pad of the chip 201 to be packaged through the passivation layer opening 2021. In yet another embodiment, the trace structure may further include a front-side first encapsulation layer formed on the first redistribution layer and the exposed passivation layer 202 and encapsulation layer 204, and the front-side first encapsulation layer has an opening. A conductive pillar electrically connected to the first redistribution layer is disposed in the opening to lead out a pad on the front surface of the chip 201 to be packaged.
Further, in an embodiment, the trace structure may be repeatedly formed on the front surface of the chip 201 to be packaged, for example, a second re-wiring layer or more re-wiring layers may be formed outside the front surface first packaging layer in the same manner, so as to realize a multi-layer trace structure of the product.
It should be noted that, when the chip 201 to be packaged is packaged, a trace structure may be formed on the front surface of the chip 201 to be packaged after the carrier 200 is peeled off. Of course, the trace structure may also be formed on the front surface of the chip 201 to be packaged before the chip 201 to be packaged is attached to the carrier 200. The trace structure may also include one or more re-routing layers. In the embodiment where the front surface of the chip 201 to be packaged is provided with or without a protective layer, the trace structure may be formed before the chip 201 to be packaged is attached to the carrier. The operations related to the specific formation of the trace structure can refer to the above description, and are not repeated herein.
Further, in the case that the chips 201 to be packaged are packaged together, after the packaging is completed, the whole package structure may be cut into a plurality of packages by laser or mechanical cutting, so as to form a package structure with a single chip.
As shown in fig. 3, in another embodiment, a passivation opening 2021 is formed on the passivation layer at a position corresponding to a pad of the plurality of chips to be packaged, which may be performed before the wafer on which the passivation layer is formed is cut into the plurality of chips to be packaged. The detailed configuration of the passivation opening 2021 can refer to the related descriptions above, and will not be described herein. After the chip to be packaged formed with the protective layer 202 is adhered to the adhesive layer 203 of the carrier 200, the plurality of protective layer openings 2021 are in a hollow state.
In another embodiment, after forming the protective layer opening on the protective layer at a position corresponding to the pads of the chips to be packaged, the method further includes: and filling a conductive medium in the opening of the protective layer, so that the conductive medium is electrically connected with the welding pad of the chip to be packaged. The conductive medium forms a vertical connecting structure in the opening of the protective layer, so that the welding pad on the surface of the chip is extended to the surface of the protective layer in a single way, and the protective layer can surround and form the periphery of the connecting structure.
In some embodiments, after forming the encapsulating layer 204 and before peeling the carrier sheet 200, the packaging method further comprises attaching a support layer 205 on the encapsulating layer 204 away from the second surface 2042 of the carrier sheet.
The support layer is attached to at least a portion of the second surface 2042 of the encapsulation layer. As shown in fig. 4, in one embodiment, the support layer 205 is attached on the second surface 2042 of the encapsulating layer 204, and the support layer 205 covers the entire area of the second surface 2042 of the encapsulating layer 204.
The material strength of the supporting layer 205 is greater than that of the encapsulating layer 204, so that the supporting layer 205 can effectively improve and ensure the mechanical strength of the encapsulating structure in the encapsulating process, and effectively inhibit adverse effects caused by deformation of each structure, thereby improving the product encapsulating effect.
Accordingly, in this embodiment, the carrier 200 may be peeled off after the supporting layer 205 is mounted, so as to expose the front surface of the chip 201 to be packaged.
Subsequently, after the trace structure is formed on the front side of the chip 201 to be packaged, the semiconductor packaging method further includes peeling off the supporting layer 205. Through setting up the supporting layer and can effectively improve and guarantee packaging structure's among the encapsulation process mechanical strength, effectively restrain the adverse effect that each structure warp and bring to improve the effect of product encapsulation.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (9)

1. A semiconductor packaging method, comprising:
mounting the front surface of a chip to be packaged on a carrier plate to form a mounting area on which the chip to be packaged is mounted and a blank area surrounding the mounting area on the carrier plate;
placing two conductive blocks on the blank area on the carrier plate, wherein the two conductive blocks are oppositely arranged on two sides of the mounting area;
forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the chip to be encapsulated and the conductive blocks;
stripping the carrier plate to expose the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer;
forming a metal structure on the front surface of the chip to be packaged, the front surface of the conductive block and the first surface of the encapsulating layer;
arranging a plurality of clamps on the front surface of each conductive block, wherein the clamps on the two conductive blocks are arranged in a one-to-one correspondence manner;
and carrying out an electroplating process, wherein a trace structure is formed after the metal structure is patterned, and the trace structure is used for leading out a welding pad on the front side of the chip to be packaged.
2. The semiconductor packaging method according to claim 1, wherein a plurality of the clips located on the front surface of the same conductive block are arranged at equal intervals.
3. The semiconductor packaging method according to claim 1, wherein after the providing the plurality of jigs and before the performing the plating process, the method comprises: the metal structure is provided with an insulating frame, the insulating frame is a closed frame structure surrounding the chip to be packaged, and the insulating frame is located between the chip to be packaged and the clamp.
4. The semiconductor packaging method according to claim 3, wherein a material of the insulating frame is rubber.
5. The semiconductor packaging method according to claim 1, wherein a material of the conductive block is copper.
6. The semiconductor packaging method according to claim 1, wherein the metal structure comprises a seed layer and a metal layer, the seed layer is formed on the front surface of the chip to be packaged, the front surfaces of the conductive blocks and the first surface of the encapsulating layer; the metal layer is formed on the seed layer.
7. The semiconductor packaging method according to claim 1, further comprising, before the mounting the chip to be packaged on the carrier:
and forming a protective layer on the front surface of each chip to be packaged.
8. The semiconductor packaging method according to any one of claims 1 to 7, wherein after the forming of the encapsulation layer and before the peeling of the carrier plate, the method comprises:
and a supporting layer is pasted on the second surface of the encapsulating layer far away from the carrier plate.
9. The semiconductor packaging method of claim 8, wherein after forming the trace structure on the front side of the chip to be packaged, the method comprises:
and stripping the supporting layer.
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