CN111599694B - Semiconductor packaging method - Google Patents
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- CN111599694B CN111599694B CN201911398945.2A CN201911398945A CN111599694B CN 111599694 B CN111599694 B CN 111599694B CN 201911398945 A CN201911398945 A CN 201911398945A CN 111599694 B CN111599694 B CN 111599694B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 92
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- 238000005538 encapsulation Methods 0.000 claims abstract description 47
- 238000003466 welding Methods 0.000 claims abstract description 16
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- 238000001746 injection moulding Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/279—Methods of manufacturing layer connectors involving a specific sequence of method steps
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Abstract
The application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps: encapsulating at least one chip by adopting a first encapsulating layer, wherein the front surface of the chip is exposed to obtain an encapsulating structure, and the front surface of the chip is provided with a welding pad; providing a first carrier and a first carrier fixing part, wherein the first carrier fixing part is arranged to enable a first side surface of the first carrier and a second side surface opposite to the first side surface to be at least partially exposed; respectively mounting the encapsulation structure on the first side surface and the second side surface of the first carrier plate, wherein the front surface of the chip deviates from the first carrier plate; forming a first rewiring layer on one side of each of the two encapsulation structures, which is far away from the first carrier plate, wherein the first rewiring layer on the same side of the first carrier plate is electrically connected with the welding pad; and removing the first carrier plate.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and in particular, to a semiconductor packaging method.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the method comprises the steps of firstly bonding the front side of a bare chip on a substrate through an adhesive tape, carrying out hot-press plastic package, peeling off the substrate, then forming a rewiring structure on the front side of the bare chip, and carrying out packaging. The existing semiconductor packaging technology has the problem of low packaging efficiency.
Disclosure of Invention
The embodiment of the application provides a semiconductor packaging method, which comprises the following steps:
encapsulating at least one chip by adopting a first encapsulating layer, wherein the front surface of the chip is exposed to obtain an encapsulating structure, and the front surface of the chip is provided with a welding pad;
providing a first carrier and a first carrier fixing part, wherein the first carrier fixing part is arranged to enable a first side surface of the first carrier and a second side surface opposite to the first side surface to be at least partially exposed;
respectively mounting the encapsulation structure on the first side surface and the second side surface of the first carrier plate, wherein the front surface of the chip deviates from the first carrier plate;
forming a first rewiring layer on one side of each of the two encapsulation structures, which is far away from the first carrier plate, and electrically connecting the first rewiring layer on the same side of the first carrier plate with the welding pad;
and removing the first carrier plate.
In one embodiment, the encapsulating at least one chip with an encapsulation layer includes:
attaching at least one chip to be packaged on a second carrier plate, wherein the surface of the chip close to the second carrier plate is a front surface, and a plurality of welding pads are arranged on the front surface of the chip;
forming a first encapsulating layer, wherein the first encapsulating layer covers the second carrier plate and encapsulates the at least one chip to be encapsulated;
and stripping the second carrier plate to expose the front surface of the chip.
In one embodiment, the mounting of the at least one chip to be packaged on the second carrier includes:
forming a first bonding layer on the second carrier plate;
and the chip is attached to the preset position of the second carrier plate through the first adhesive layer.
In one embodiment, after the encapsulating at least one chip with the first encapsulation layer, the semiconductor packaging method further includes:
forming a protective film layer on the packaging structure, wherein the protective film layer covers the front side of the chip;
after the encapsulating structures are respectively mounted on the first side surface and the second side surface of the first carrier, the semiconductor packaging method further includes:
and removing the protective film layer.
In one embodiment, the mounting of one of the encapsulation structures on the first side and the second side of the first carrier respectively includes:
forming a second bonding layer on the first side surface and the second side surface of the first carrier plate respectively;
one of the encapsulating structures is attached to the first side by a second adhesive layer on the first side and the other encapsulating structure is attached to the second side by a second adhesive layer on the second side.
In one embodiment, after the forming of the first redistribution layer at the same time at a side of the two encapsulation structures facing away from the first carrier, the semiconductor packaging method further includes:
and forming second encapsulation layers on the two first rewiring layers respectively, wherein the second encapsulation layers encapsulate the first rewiring layers and the exposed first encapsulation layers, and the first encapsulation layers and the second encapsulation layers are positioned on the same side of the first carrier plate.
In one embodiment, the redistribution layer includes at least one conductive structure, the conductive structure includes a first conductive layer and a second conductive layer located on a side of the first conductive layer away from the first carrier, and the conductive structure located on the same side of the first carrier is electrically connected to a pad of the chip; the forming a first redistribution layer on one side of the two encapsulation structures away from the first carrier simultaneously includes:
forming a conductive film layer on one side of the two encapsulation structures, which is far away from the first carrier plate, and covering the encapsulation structures, which are positioned on the same side of the first carrier plate, with the conductive film layer;
forming insulating layers on the two sides of the conductive film layers, which are far away from the first carrier plate, and forming through holes corresponding to the welding pads on the same side of the first carrier plate on the two insulating layers;
simultaneously forming a second conductive layer in the through holes of the two insulating layers;
and removing the conductive film layer between the insulating layer and the first carrier plate and the insulating layer, wherein the reserved conductive film layer between the second conductive layer and the first carrier plate is the first conductive layer.
In one embodiment, the redistribution layer includes at least one conductive structure, and the conductive structure on the same side of the first carrier is electrically connected to a pad of the chip;
before the first redistribution layer is formed on one side of the two encapsulation structures away from the first carrier plate at the same time, the semiconductor packaging method further includes:
forming a second packaging layer on one side of the two packaging structures, which is far away from the first carrier plate, wherein a contact hole is formed in the second packaging layer, and the contact hole exposes out of a welding pad of the chip;
the forming a rewiring layer on one side of each of the two encapsulating structures, which is away from the first carrier plate, comprises:
and forming a conductive structure in the contact holes of the two second packaging layers at the same time, wherein the surface of the conductive structure is exposed out of the second packaging layer which is positioned at the same side of the first carrier plate as the conductive structure.
In one embodiment, before the removing the first carrier, the semiconductor packaging method further includes:
and forming a second rewiring layer on the two first rewiring layers at the same time, wherein the second rewiring layer positioned on the same side of the first carrier plate is electrically connected with the first rewiring layer.
In one embodiment, after the removing the first carrier, the semiconductor packaging method further includes:
and forming second rewiring layers on the two first rewiring layers respectively, wherein the second rewiring layers are electrically connected with the adjacent first rewiring layers.
The embodiment of the application achieves the main technical effects that:
in the semiconductor packaging method provided by the embodiment of the application, the packaging structures are formed first, one packaging structure is respectively mounted on two opposite sides of the first carrier, and then the first rewiring layer is formed on the two packaging structures at the same time. Because the first rewiring layers on the two encapsulation structures are formed simultaneously, compared with a scheme that only one rewiring layer is formed on one encapsulation structure at a time, the semiconductor packaging method and the semiconductor packaging device can save packaging time, improve rewiring efficiency and further improve semiconductor packaging efficiency.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method provided by an embodiment of the present application;
fig. 2 is a schematic structural diagram of an intermediate structure obtained by a semiconductor packaging method provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 4 is a schematic structural diagram of yet another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 6 is a schematic view illustrating a first carrier disposed on a first carrier fixing portion according to an embodiment of the present disclosure;
fig. 7 is another schematic view illustrating a first carrier disposed on a first carrier fixing portion according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 9 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 10 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 11 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 12 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 13 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 14 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 15 is a schematic structural diagram of another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 16 is a schematic structural diagram of yet another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 17 is a schematic structural diagram of yet another intermediate structure obtained by the semiconductor packaging method provided in the embodiment of the present application;
fig. 18 is a schematic structural diagram of a semiconductor package obtained by the semiconductor packaging method according to the embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 150.
In step 110, at least one chip is encapsulated by using a first encapsulation layer, and the front surface of the chip is exposed to obtain an encapsulation structure, wherein the front surface of the chip is provided with a bonding pad.
In one embodiment, the chip to be packaged can be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with an insulating layer and a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the deviation of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness. The welding pad of the chip to be packaged is formed by a conductive electrode which is led out from the internal circuit of the chip to the surface of the chip. The welding pad is prepared on the conductive electrode of the chip, and the conductive electrode of the chip is led out.
In one embodiment, step 110 of encapsulating the at least one chip with the first encapsulation layer may be accomplished by steps 111 to 113 as follows.
In step 111, at least one chip to be packaged is mounted on a second carrier, the surface of the chip close to the second carrier is a front surface, and the front surface of the chip is provided with a plurality of bonding pads.
In one embodiment, the step 111 of mounting at least one chip to be packaged on the second carrier can be completed by the following steps 1111 and 1112.
In step 1111, a first adhesive layer is formed on the second carrier.
By the step 1111, an intermediate structure as shown in fig. 2 can be obtained, and the first adhesive layer 102 can cover the surface of the second carrier 101. The material of the first adhesive layer 102 may be a peeling material to facilitate peeling the second carrier 101 from the chip to be packaged.
In one embodiment, the second carrier 101 is a rigid carrier, such as a glass carrier, or a stainless steel carrier. When the second carrier 101 is a hard carrier, the supporting effect is better.
In step 1112, the chip is attached to a predetermined position of the second carrier through the first adhesive layer.
The structure shown in fig. 3 can be obtained through step 1112. The pad 11 of the chip 10 is in direct contact with the first adhesive layer 102. Fig. 3 only illustrates the second carrier 101 with one chip 10 mounted thereon, and in other embodiments, two or more chips 10 may be mounted on the second carrier 101.
In step 112, a first encapsulating layer is formed, and the first encapsulating layer covers the second carrier and encapsulates the at least one chip to be encapsulated.
The structure shown in fig. 4 can be obtained through step 112.
In one embodiment, before forming the first encapsulant layer, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the chip 10 and the first carrier 101, so that the first encapsulant layer 20 and the chip 10 to be packaged can be more closely connected to the first carrier 101 without delamination or cracking.
In one embodiment, the first encapsulant layer 20 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.
In step 113, the second carrier is peeled off to expose the front surface of the chip.
In the embodiment shown in fig. 4, the first carrier 101 and the chip 10 to be packaged are bonded by the first adhesive layer 102, and when the first adhesive layer 102 is made of a thermal separation material, the first adhesive layer 102 may be heated to reduce its viscosity, so as to peel off the first carrier 101. After the encapsulation structure is peeled off from the first carrier 101, the front surface of the chip 10 to be packaged is exposed. In other embodiments, the first carrier plate 101 may be mechanically peeled off directly from the first encapsulant layer 20 and the chip 10 to be packaged. An encapsulated structure as shown in fig. 5 may be obtained through step 113.
In step 120, a first carrier and a first carrier fixing portion are provided, where the first carrier fixing portion is configured to expose at least a portion of a first side surface of the first carrier and a second side surface opposite to the first side surface.
The first carrier may be a rigid carrier, such as a glass carrier, or a stainless steel carrier.
In one embodiment, referring to fig. 6, after the first carrier plate 103 is placed on the first carrier plate fixing portion 105, the first side surface 1031 of the first carrier plate 103 faces upward, the second side surface 1032 of the first carrier plate 103 faces downward, an edge portion of the second side surface 1032 contacts with the first carrier plate fixing portion 105, and most of the second side surface 1032 is exposed.
In another embodiment, referring to fig. 7, after the first carrier 103 is disposed on the first carrier fixing portion 105, a side surface of the first carrier 103 between the first side surface 1031 and the second side surface is all contacted with the first carrier fixing portion 105, and both the first side surface 1031 and a second side surface opposite to the first side surface 1031 are all exposed.
In step 130, the encapsulation structures are respectively mounted on the first side surface and the second side surface of the first carrier, and the front surface of the chip is away from the first carrier.
Prior to step 130, the semiconductor packaging method may further include: a protective film layer 30 is formed on the encapsulation structure, and the protective film layer 30 covers the front surface of the chip 10.
The protective film 30 may have some adhesive properties so that it can be directly adhered to the envelope structure. The structure shown in fig. 8 can be obtained through step 120. In the process of attaching the encapsulating structure to the first carrier plate, the encapsulating structure needs to be pressed. The protective film 30 can protect the bonding pads 11 on the front surface of the chip 10 and prevent the bonding pads 11 of the chip 10 from being damaged when the encapsulation structure is pressed.
In one embodiment, the step 130 of attaching one encapsulating structure to the first side and the second side of the first carrier respectively may be implemented by the following steps 131 and 132.
In step 131, second adhesive layers are formed on the first side and the second side of the first carrier, respectively.
The second adhesive layer on the first side and the second adhesive layer on the second side can be formed simultaneously, thereby being beneficial to improving the packaging efficiency of the semiconductor.
In step 132, one of the encapsulating structures is attached to the first side by a second adhesive layer on the first side and the other encapsulating structure is attached to the second side by a second adhesive layer on the second side.
In this step, the encapsulating structure may be pressed against the second adhesive layer 104, so that the encapsulating structure is attached to the first carrier 103 via the second adhesive layer 104, which may make the encapsulating structure more firmly bonded to the first carrier 103. By this step an intermediate structure as shown in fig. 9 is obtained.
In one embodiment, the material of the second adhesive layer 104 formed on the first side and the second side of the first carrier 103 may be resin. When the resin is heated, the viscosity is reduced, and when the first carrier 103 needs to be peeled off later, the peeling of the encapsulation structure and the first carrier 103 can be realized by changing the temperature of the resin, so that the operation is convenient.
In one embodiment, if the encapsulating structure is formed with the protective film 30, after the step 130 of respectively attaching one encapsulating structure to the first side and the second side of the first carrier, the semiconductor packaging method further includes: and removing the protective film layer. After the protective film layer 30 is removed, the pad 11 of the chip 10 is exposed, resulting in an intermediate structure as shown in fig. 10.
In step 140, a first redistribution layer is simultaneously formed on a side of the two encapsulation structures away from the first carrier, and the first redistribution layer on the same side of the first carrier is electrically connected to the pad.
In one embodiment, the redistribution layer includes at least one conductive structure, the conductive structure located on the same side of the first carrier is electrically connected to a pad of the chip, and the conductive structure can lead out the pad of the chip. The conductive structure may be a pillar, such as a cylinder, or a cube.
In one embodiment, the conductive structure includes a first conductive layer and a second conductive layer located on a side of the first conductive layer facing away from the first carrier. In other embodiments, the conductive structure may include only one conductive layer.
In one embodiment, the semiconductor packaging method may further include: and forming a second packaging layer, wherein the second packaging layer packages the first rewiring layer and the exposed packaging structure, which are positioned on the same side of the first carrier plate, with the second packaging layer. The second encapsulant layer may be formed after step 140 or may be formed before step 140. As will be described in detail below.
In a first embodiment, a second encapsulant layer is formed after step 140. That is, the conductive structure 60 is formed first, and then the second encapsulant layer 70 is formed.
In this embodiment, if the conductive structure includes a first conductive layer and a second conductive layer, the step 140 of forming a first redistribution layer on both sides of the encapsulation structure away from the first carrier can be formed as follows in steps 141 to 142.
In step 141, a conductive film layer is simultaneously formed on one side of each of the two encapsulation structures away from the first carrier, and the conductive film layer covers the encapsulation structure located on the same side of the first carrier as the conductive film layer.
In one embodiment, the conductive film layer may be formed by a sputtering process.
An intermediate structure as shown in fig. 11 may be obtained through step 141. Referring to fig. 11, the conductive film layers 40 on both sides of the first carrier 101 cover the sides of the adjacent encapsulation structures away from the first carrier 103. The material of the conductive film layer 40 may be metal.
In step 142, insulating layers are simultaneously formed on the two conductive film layers on the sides departing from the first carrier plate, and through holes corresponding to the pads on the same side of the first carrier plate are formed on the two insulating layers.
In this step, first, the insulating layers 50 are formed on the sides of the two conductive film layers 40 facing away from the first carrier plate 103, respectively, resulting in the intermediate structure shown in fig. 12.
Then, through holes 501 corresponding to the pads 11 of the insulating layer located on the same side of the first carrier are respectively opened on the two insulating layers 50. The through hole 501 corresponds to the pad 11, which means that the through hole 501 is opposite to the pad 11 in the lamination direction of the film layers. By this step an intermediate structure as shown in fig. 13 is obtained. In the process of forming the through hole, the conductive film layer 40 can protect the bonding pad 11 on the front surface of the chip 10 and prevent damage to the bonding pad 11 of the chip 10.
In one embodiment, the insulating layer 50 may be a photosensitive film layer, and the via 501 may be formed on the photosensitive film layer through an exposure and development process.
In step 143, a second conductive layer is simultaneously formed in the vias of both of the insulating layers.
An intermediate structure as shown in fig. 14 may be obtained through step 143.
In one embodiment, the second conductive layer 62 may be formed in the through holes 501 of the two insulating layers 50 by an electroplating process. The material of the second conductive layer 62 may be metal.
In step 144, the conductive film layer between the insulating layer and the first carrier and the insulating layer are removed, and the remaining conductive film layer between the second conductive layer and the first carrier is the first conductive layer.
An intermediate structure as shown in fig. 15 may be obtained through step 144. The conductive structure 60 includes a first conductive layer 61 and a second conductive layer 62 located on a side of the first conductive layer 61 away from the first carrier board 103. The orthographic projection of the first conductive layer 61 on the first carrier plate 103 and the orthographic projection of the second conductive layer 62 on the first carrier plate 103 can coincide.
In one embodiment, the portion of the conductive film layer 40 between the first carrier 103 and the insulating layer 50 may be removed by cleaning. The cleaning method may be, for example, acid cleaning, alkali cleaning, or ion cleaning.
After step 140, the semiconductor packaging method further includes: and simultaneously forming a second encapsulating layer on the two first rewiring layers, wherein the second encapsulating layer encapsulates the adjacent first rewiring layers and the exposed first encapsulating layer.
In one embodiment, the second encapsulant layer 70 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.
In this step, the second encapsulant layer 70 formed on the two first redistribution layers may cover the exposed chip 10, the exposed first encapsulant layer 20 and the conductive structure 60 on the same side of the first carrier as the second encapsulant layer 70, and the thickness of the second encapsulant layer 70 is greater than that of the conductive structure 60, so as to obtain an intermediate structure as shown in fig. 16. Thereafter, the second encapsulant layer 70 is polished to expose the surface of the conductive structure 60 to the second encapsulant layer 70.
In one embodiment, the second encapsulant layer 70 may be polished before the first carrier 103 is removed. In other embodiments, the first carrier 103 may be removed first, so as to obtain the intermediate structure shown in fig. 17; the second encapsulant layer 70 is then polished to obtain the semiconductor package structure shown in fig. 18.
In a second embodiment, the second encapsulant layer is formed before step 140. That is, the second encapsulant layer 70 is formed first, and then the conductive structure 60 is formed.
In this embodiment, the step of forming the second encapsulant layer may be achieved by:
and simultaneously forming a second packaging layer on one side of the two packaging structures, which is far away from the first carrier plate, wherein a contact hole is formed in the second packaging layer, and the contact hole exposes the welding pad of the chip, which is positioned on the same side of the first carrier plate as the contact hole.
The forming a rewiring layer on one side of each of the two encapsulating structures, which is away from the first carrier plate, comprises: and forming a conductive structure in the contact holes of the two second packaging layers at the same time, wherein the surface of the conductive structure is exposed out of the second packaging layer which is positioned at the same side of the first carrier plate as the conductive structure.
In this embodiment, the second encapsulant layer 70 is formed first, a contact hole is formed in the second encapsulant layer 70, and then the conductive structure 60 is formed in the contact hole, so that the manufacturing process is relatively simple.
In step 150, the first carrier is removed.
In one embodiment, when the encapsulated structure is attached to the first carrier 103 by the second adhesive layer 104, the second adhesive layer 104 can be heated to reduce its viscosity, and then the encapsulated structure is peeled off from the first carrier.
In one embodiment, before the step 150 of removing the first carrier board, the semiconductor packaging method further includes: and forming a second rewiring layer on the two first rewiring layers at the same time, wherein the second rewiring layer positioned on the same side of the first carrier plate is electrically connected with the first rewiring layer.
The second redistribution layer may include a plurality of conductive pillars electrically connected to the conductive structure of the adjacent first redistribution layer. In this way, a multi-layer package structure can be realized.
In the step, the second rewiring layer is formed on the two first rewiring layers at the same time, so that the packaging time is saved, and the packaging efficiency is improved.
In another embodiment, after removing the first carrier, the semiconductor packaging method further includes: and forming second rewiring layers on the two first rewiring layers respectively, wherein the second rewiring layers are electrically connected with the adjacent first rewiring layers. The second redistribution layer may include a plurality of conductive pillars electrically connected to the conductive structures of the adjacent first redistribution layer. In this way, a multi-layer package structure can be realized.
In the semiconductor packaging method provided by the embodiment of the application, the packaging structures are formed first, one packaging structure is respectively mounted on two opposite sides of the first carrier, and then the first rewiring layer is formed on the two packaging structures at the same time. Because the first rewiring layers on the two encapsulation structures are formed simultaneously, compared with a scheme that only one rewiring layer is formed on one encapsulation structure at a time, the semiconductor packaging method and the semiconductor packaging device can save packaging time, improve rewiring efficiency and further improve semiconductor packaging efficiency.
In the present application, the apparatus embodiments and the method embodiments may complement each other without conflict. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:
encapsulating at least one chip by adopting a first encapsulating layer, wherein the front surface of the chip is exposed to obtain an encapsulating structure, and the front surface of the chip is provided with a welding pad;
providing a first carrier plate and a first carrier plate fixing part, wherein the first carrier plate fixing part is arranged to enable a first side surface of the first carrier plate and a second side surface opposite to the first side surface to be completely exposed, and one side surface of the first carrier plate between the first side surface and the second side surface is completely contacted with the first carrier plate fixing part;
respectively mounting the encapsulation structures on the first side surface and the second side surface of the first carrier plate, wherein the front surfaces of the chips are deviated from the first carrier plate;
forming a first rewiring layer on one side of each of the two encapsulation structures, which is far away from the first carrier plate, and electrically connecting the first rewiring layer on the same side of the first carrier plate with the welding pad;
and removing the first carrier plate.
2. The semiconductor packaging method of claim 1, wherein encapsulating at least one chip with an encapsulation layer comprises:
attaching at least one chip to be packaged on a second carrier plate, wherein the surface of the chip close to the second carrier plate is a front surface, and a plurality of welding pads are arranged on the front surface of the chip;
forming a first encapsulating layer, wherein the first encapsulating layer covers the second carrier plate and encapsulates the at least one chip to be encapsulated;
and stripping the second carrier plate to expose the front surface of the chip.
3. The semiconductor packaging method of claim 2, wherein the mounting of the at least one chip to be packaged on the second carrier comprises:
forming a first bonding layer on the second carrier plate;
and the chip is attached to the preset position of the second carrier plate through the first adhesive layer.
4. The semiconductor packaging method according to claim 1, wherein after the encapsulating the at least one chip with the first encapsulating layer, the semiconductor packaging method further comprises:
forming a protective film layer on the packaging structure, wherein the protective film layer covers the front side of the chip;
after the encapsulating structures are respectively mounted on the first side surface and the second side surface of the first carrier, the semiconductor packaging method further includes:
and removing the protective film layer.
5. The semiconductor packaging method of claim 1, wherein the attaching one of the encapsulating structures on the first side and the second side of the first carrier respectively comprises:
forming a second bonding layer on the first side surface and the second side surface of the first carrier plate respectively;
one of the encapsulating structures is attached to the first side by a second adhesive layer on the first side and the other encapsulating structure is attached to the second side by a second adhesive layer on the second side.
6. The semiconductor packaging method according to claim 1, wherein after the forming of the first redistribution layer on the side of the two encapsulation structures facing away from the first carrier, the semiconductor packaging method further comprises:
and forming second encapsulation layers on the two first rewiring layers respectively, wherein the second encapsulation layers encapsulate the first rewiring layers and the exposed first encapsulation layers, and the first encapsulation layers and the second encapsulation layers are positioned on the same side of the first carrier plate.
7. The semiconductor packaging method according to claim 6, wherein the redistribution layer comprises at least one conductive structure, the conductive structure comprises a first conductive layer and a second conductive layer located on a side of the first conductive layer away from the first carrier plate, and the conductive structure located on the same side of the first carrier plate is electrically connected to a pad of the chip; the forming a first redistribution layer on one side of each of the two encapsulation structures away from the first carrier plate at the same time includes:
forming a conductive film layer on one side of the two encapsulation structures, which is far away from the first carrier plate, wherein the conductive film layer covers the encapsulation structures which are positioned on the same side of the first carrier plate as the conductive film layer;
forming insulating layers on the two sides of the conductive film layers, which are far away from the first carrier plate, and forming through holes corresponding to the welding pads on the same side of the first carrier plate on the two insulating layers;
simultaneously forming a second conductive layer in the through holes of the two insulating layers;
and removing the conductive film layer between the insulating layer and the first carrier plate and the insulating layer, wherein the reserved conductive film layer between the second conductive layer and the first carrier plate is the first conductive layer.
8. The semiconductor packaging method according to claim 1, wherein the rewiring layer comprises at least one conductive structure, and the conductive structures on the same side of the first carrier plate are electrically connected with bonding pads of the chip;
before the first redistribution layer is formed on one side of the two encapsulation structures away from the first carrier plate at the same time, the semiconductor packaging method further includes:
forming a second encapsulating layer on one side of the two encapsulating structures, which is far away from the first carrier plate, wherein a contact hole is formed in the second encapsulating layer, and the contact hole exposes the welding pad of the chip;
the forming a rewiring layer on one side of each of the two encapsulating structures, which is away from the first carrier plate, comprises:
and forming a conductive structure in the contact holes of the two second packaging layers at the same time, wherein the surface of the conductive structure is exposed out of the second packaging layer which is positioned at the same side of the first carrier plate as the conductive structure.
9. The semiconductor packaging method according to claim 1, wherein before the removing the first carrier, the semiconductor packaging method further comprises:
and forming a second rewiring layer on the two first rewiring layers at the same time, wherein the second rewiring layer positioned on the same side of the first carrier plate is electrically connected with the first rewiring layer.
10. The semiconductor packaging method according to claim 1, wherein after the removing the first carrier plate, the semiconductor packaging method further comprises:
and forming second rewiring layers on the two first rewiring layers respectively, wherein the second rewiring layers are electrically connected with the adjacent first rewiring layers.
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| CN105097720B (en) * | 2015-06-30 | 2017-12-08 | 通富微电子股份有限公司 | The forming method of encapsulating structure |
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| CN110459510A (en) * | 2019-08-08 | 2019-11-15 | 广东芯华微电子技术有限公司 | Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof |
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| CN105244341A (en) * | 2015-09-01 | 2016-01-13 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device FOWLP packaging structure and manufacturing method thereof |
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