CN110459510A - Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof - Google Patents
Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof Download PDFInfo
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- CN110459510A CN110459510A CN201910731239.9A CN201910731239A CN110459510A CN 110459510 A CN110459510 A CN 110459510A CN 201910731239 A CN201910731239 A CN 201910731239A CN 110459510 A CN110459510 A CN 110459510A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Details Of Aerials (AREA)
Abstract
The present invention discloses a kind of big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof.Wherein, big plate fan-out-type two-sided antenna encapsulating structure includes: support plate；Several semiconductor chips, the back side are attached at the two sides of support plate；Encapsulated layer is located at support plate two sides and covers semiconductor chip, and semiconductor chip front exposes to encapsulated layer；Transport layer, wiring layer and antenna stack are respectively positioned on encapsulated layer, and the front electric connection of the side of transport layer and encapsulated layer and semiconductor chip, the other side and wiring layer and antenna stack are electrically connected, and wiring layer has pad area and non-pad area；Solder mask on encapsulated layer and covers antenna stack and non-pad area；Metal coupling is welded with the pad area of wiring layer.Small in size shared by antenna stack of the invention, encapsulating structure connection and reasonable arrangement can be improved the integration performance of antenna packages structure and the efficiency of antenna, and will not cause surface warp because of difference in material properties, it is ensured that precision, yield rate and welding stability when production.
Description
Technical field
The present invention relates to fan-out package technical fields, and in particular to a kind of big plate fan-out-type two-sided antenna encapsulating structure and
Preparation method.
Background technique
Fan-out package is a kind of one of preferable Advanced Packaging method of flexibility, is had compared to conventional wafer-level packaging
There is its uniqueness.And in fan-out-type antenna packages structure, antenna transmission and reception signal are needed using multiple function chips
Module goes to be composed.
The traditional method of fan-out-type antenna packages structure is: attaching semiconductor chip in the side of support plate, then by being electrically connected
Binding structure draws antenna, and antenna is made to be located at the surface of circuit board.This way is in the actual production and application process of product
It has the following deficiencies:
(1), for big plate fan-out package structure, since size is larger, lead to big plate fan-out package structure
Angularity is larger；
(2), antenna occupies additional board area, increases the volume of fan-out-type antenna packages structure, leads to product
Conformability is poor, higher cost.For various high-tech electronic products, if antenna to be directly made in the table of circuit board
Face, then antenna and chip are connected by electric connection structure, it is meant that large volume of circuit board is needed, so that high-tech is electric
Sub- product also takes up biggish volume, and can make that transmission line is longer, efficiency is poor and power consumption is high, this and people
The miniaturization of high-tech electronic product, portable, high-effect, low-power consumption demand are disagreed；
(3), a fan-out-type antenna packages structure is only made on a support plate, production efficiency is low, to improve product
Production cost.
Therefore, how to reduce the volume of big plate fan-out-type antenna packages structure, reduce power consumption, improve fan-out-type antenna packages
The integration performance and reduction production cost of structure, are these current electronic device urgent problems to be solved.
Summary of the invention
It is an object of the present invention to provide a kind of big plate fan-out-type antenna packages structures, will not be because of difference in material properties
Cause surface warp, encapsulation volume can be reduced, improves the efficiency of transmission of antenna and the integration performance of encapsulating structure.
It is another object of the present invention to provide a kind of preparation method of big plate fan-out-type antenna packages structure, Bu Huiyin
Difference in material properties causes product surface warpage, and can improve production efficiency.
To achieve this purpose, the present invention adopts the following technical scheme:
On the one hand, a kind of big plate fan-out-type two-sided antenna encapsulating structure is provided, comprising:
Support plate has opposite the first face and the second face along its thickness direction；
Several semiconductor chips, the back side of several semiconductor chips pass through peeling layer respectively and are attached at the support plate
First face and the second face；
Encapsulated layer positioned at the first face of the support plate and the second face and covers the semiconductor chip, the semiconductor core
The front of piece exposes to the encapsulated layer；
Transport layer, wiring layer and antenna stack, the side positioned at the encapsulated layer far from the support plate, the one of the transport layer
Side and the front of the encapsulated layer and the semiconductor chip are electrically connected, the other side and the wiring layer and antenna stack electricity
Property connection, the wiring layer have pad area and non-pad area；
Solder mask, side positioned at the encapsulated layer far from the support plate simultaneously cover the antenna stack and the wiring layer
The outside of non-pad area；
Metal coupling is welded with the pad area of the wiring layer.
As a kind of preferred embodiment of big plate fan-out-type two-sided antenna encapsulating structure, the semiconductor chip includes naked core
Piece, the end I/O in the bare chip and the connecting column for being convexly equipped in outside the bare chip and being electrically connected with the end I/O,
The connecting column is parallel to the surface of the encapsulated layer far from one end of the bare chip and connect with the transport layer.
As a kind of preferred embodiment of big plate fan-out-type two-sided antenna encapsulating structure, the transport layer includes being affixed on the envelope
Dielectric layer on dress layer and the seed layer that is attached on the dielectric layer, the dielectric layer have along its thickness direction and make described half
The exposed via hole of the connecting column of conductor chip, the seed layer are extended in the via hole and are electrically connected with the connecting column.
As a kind of preferred embodiment of big plate fan-out-type two-sided antenna encapsulating structure, the seed layer includes being located at the envelope
Fill titanium coating of the layer far from the support plate side and the copper metal layer on the titanium coating.
As a kind of preferred embodiment of big plate fan-out-type two-sided antenna encapsulating structure, the thickness of the antenna stack is less than described
The thickness of wiring layer.
On the other hand, a kind of preparation method of big plate fan-out-type two-sided antenna encapsulating structure is provided, comprising the following steps:
S10, support plate and several semiconductor chips are provided, encapsulated layer is respectively adopted, the part semiconductor chip packaging exists
The first side of the support plate and by the remaining semiconductor chip packaging in the second side of the support plate, and make described half
The front of conductor chip faces away from the side of the support plate；
S20, transport layer is made on the encapsulated layer, connects the front of the semiconductor chip electrically with the transport layer
It connects；
S30, wiring layer and antenna stack are made in the transport layer；
S40, photosensitive-ink is coated far from the one side of the support plate in the encapsulated layer, forms solder mask, and make the resistance
Layer covers the non-pad area of the wiring layer and the antenna stack and the pad area of the wiring layer is made to expose to the resistance
Layer；
S50, metal coupling is provided, the metal coupling is implanted into the pad area.
A kind of preferred embodiment of preparation method as big plate fan-out-type two-sided antenna encapsulating structure, the step S10 tool
Body the following steps are included:
S10a, support plate and the first peeling layer are provided, first peeling layer is affixed on to the first face of the support plate；
S10b, several first semiconductor chips are provided, first semiconductor chip are affixed on first peeling layer,
And the front of first semiconductor chip is made to face away from the side of the support plate；
S10c, the first wheat flour the first encapsulated layer of work in the support plate, make first encapsulated layer cover first face
With first semiconductor chip；
S10d, the second peeling layer is provided, overturns the support plate, second peeling layer is affixed on the second of the support plate
Face；
S10e, several second semiconductor chips are provided, second semiconductor chip are affixed on second peeling layer,
And the front of second semiconductor chip is made to face away from the side of the support plate；
S10f, the second wheat flour the second encapsulated layer of work in the support plate, make second encapsulated layer cover second face
With second semiconductor chip.
A kind of preferred embodiment of preparation method as big plate fan-out-type two-sided antenna encapsulating structure, the step S20 tool
Body the following steps are included:
S20a, first encapsulated layer and second encapsulated layer are ground simultaneously, makes first semiconductor core
The connecting column of piece exposes to first encapsulated layer, the connecting column of second semiconductor chip exposes to second encapsulation
Layer；
S20b, dielectric layer is provided, the dielectric layer is affixed on to first encapsulated layer and described second after grinding respectively
On encapsulated layer；
S20c, laser drill is carried out to the dielectric layer, so that the dielectric layer is formed via hole along its thickness direction, for institute
The connecting column of the connecting column and second semiconductor chip of stating the first semiconductor chip is exposed；
S20d, seed layer is formed in the dielectric layer and the via hole by vacuum sputtering, the dielectric layer and described
Seed layer forms the transport layer.
A kind of preferred embodiment of preparation method as big plate fan-out-type two-sided antenna encapsulating structure, the step S30 tool
Body the following steps are included:
S30a, the first photosensitive dry film is provided, first photosensitive dry film is attached in the transport layer；
S30b, pass through first time exposure, development treatment, formed on first photosensitive dry film described in there is blind hole and make
Transport layer exposes to the first graphical hole of the through-hole of first photosensitive dry film；
S30c, electroplating processes are carried out to the described first graphical hole, forms filled layer in the described first graphical hole；
S30d, the second photosensitive dry film is provided, second photosensitive dry film is attached at first photosensitive dry film and described
On filled layer；
S30e, it is exposed by second, development treatment, being formed on second photosensitive dry film makes the part filled layer
The second graphical hole for exposing to second photosensitive dry film is by the filled layer part that second photosensitive dry film covers
Form the wiring layer；
S30f, super roughening treatment is carried out to the filled layer in the second graphical hole, makes the thickness of the filled layer
Degree is reduced to form the antenna stack.
A kind of preferred embodiment of preparation method as big plate fan-out-type two-sided antenna encapsulating structure, the step S30 and
Further include step S31 between the step S40, the step S31 specifically includes the following steps:
S31a, remaining first photosensitive dry film and second photosensitive dry film are removed；
S31b, etching solution is provided, using the etching solution to first photosensitive dry film and the second photosensitive dry film quilt
Exposed seed layer is etched after removal, to remove the seed layer.
Beneficial effects of the present invention: the present invention is successively packaged with semiconductor chip in the two sides of support plate, two sides encapsulated layer with
Support plate is closely linked, and the generation of surface warp will not be caused because of the performance difference of material, can guarantee to give birth to well
Precision, yield rate and welding stability when production；After the completion of semiconductor chip packaging, two-sided transport layer, cloth can be carried out simultaneously
The production of line layer, antenna stack and solder mask can effectively improve production efficiency.Wiring layer and antenna stack are located at same level,
Small in size shared by antenna stack, the integration performance of antenna packages structure and the signal of antenna can be improved in encapsulating structure connection and reasonable arrangement
Efficiency of transmission, and reduce the power consumption of antenna packages structure.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described.It should be evident that drawings described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the cross-sectional view of intermediate products made from step S10a described in the embodiment of the present invention.
Fig. 2 is the cross-sectional view of intermediate products made from step S10b described in the embodiment of the present invention.
Fig. 3 is the cross-sectional view of intermediate products made from step S10c described in the embodiment of the present invention.
Fig. 4 is the cross-sectional view of intermediate products made from step S10d described in the embodiment of the present invention.
Fig. 5 is the cross-sectional view of intermediate products made from step S10e described in the embodiment of the present invention.
Fig. 6 is the cross-sectional view of intermediate products made from step S10f described in the embodiment of the present invention.
Fig. 7 is the cross-sectional view of intermediate products made from step S20a described in the embodiment of the present invention.
Fig. 8 is the cross-sectional view of intermediate products made from step S20d described in the embodiment of the present invention.
Fig. 9 is the cross-sectional view of intermediate products made from step S30a described in the embodiment of the present invention.
Figure 10 is the cross-sectional view of intermediate products made from step S30b described in the embodiment of the present invention.
Figure 11 is the cross-sectional view of intermediate products made from step S30c described in the embodiment of the present invention.
Figure 12 is the cross-sectional view of intermediate products made from step S30d described in the embodiment of the present invention.
Figure 13 is the cross-sectional view of intermediate products made from step S30e described in the embodiment of the present invention.
Figure 14 is the cross-sectional view of intermediate products made from step S30f described in the embodiment of the present invention.
Figure 15 is the cross-sectional view of intermediate products made from step S31a described in the embodiment of the present invention.
Figure 16 is the cross-sectional view of intermediate products made from step S31b described in the embodiment of the present invention.
Figure 17 is the cross-sectional view of intermediate products made from step S40 described in the embodiment of the present invention.
Figure 18 is the cross-sectional view of intermediate products made from step S50a described in the embodiment of the present invention.
Figure 19 is the cross-sectional view of intermediate products made from step S50b described in the embodiment of the present invention.
Figure 20 is the flow chart of the preparation method of big plate fan-out-type two-sided antenna encapsulating structure described in the embodiment of the present invention.
Figure 21 is the specific flow chart of step S10 described in the embodiment of the present invention.
Figure 22 is the specific flow chart of step S20 described in the embodiment of the present invention.
Figure 23 is the specific flow chart of step S30 described in the embodiment of the present invention.
In Fig. 1~19:
1, support plate；
2, semiconductor chip；21, the first semiconductor chip；22, the second semiconductor chip；201, bare chip；202,I/O
End；203, connecting column；
3, peeling layer；31, the first peeling layer；32, the second peeling layer；
4, encapsulated layer；41, the first encapsulated layer；42, the second encapsulated layer；
5, seed layer；
6, wiring layer；61, pad area；62, non-pad area；
7, antenna stack；
8, solder mask；
9, metal coupling；
101, the first photosensitive dry film；102, the first graphical hole；103, the second photosensitive dry film；104, second graphical hole；
11, filled layer.
Specific embodiment
To further illustrate the technical scheme of the present invention below with reference to the accompanying drawings and specific embodiments.
Wherein, the drawings are for illustrative purposes only and are merely schematic diagrams, rather than pictorial diagram, should not be understood as to this
The limitation of patent；Embodiment in order to better illustrate the present invention, the certain components of attached drawing have omission, zoom in or out, not
Represent the size of actual product；It will be understood by those skilled in the art that certain known features and its explanation may be omitted and be in attached drawing
It is understood that.
The same or similar label correspond to the same or similar components in the attached drawing of the embodiment of the present invention；It is retouched in of the invention
In stating, it is to be understood that closed if there is the orientation of the instructions such as term " on ", "lower", "left", "right", "inner", "outside" or position
System is merely for convenience of description of the present invention and simplification of the description to be based on the orientation or positional relationship shown in the drawings, rather than indicates
Or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore retouch in attached drawing
The term for stating positional relationship only for illustration, should not be understood as the limitation to this patent, for the common skill of this field
For art personnel, the concrete meaning of above-mentioned term can be understood as the case may be.
In the description of the present invention unless specifically defined or limited otherwise, if there are the indicate indicators such as term " connection "
Between connection relationship, which shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or at
One；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection of two components interiors or the interaction relationship of two components.For those of ordinary skill in the art and
Speech, can understand the concrete meaning of above-mentioned term in the present invention with concrete condition.
Unless specific instructions, each used in the preparation method of big plate fan-out-type two-sided antenna encapsulating structure of the invention
Kind raw material is commercially available buys, or is prepared according to the conventional method of the art.
As shown in figure 19, the embodiment of the present invention provides a kind of big plate fan-out-type two-sided antenna encapsulating structure, comprising:
Support plate 1 has opposite the first face and the second face along its thickness direction；
Several semiconductor chips 2, the back side of several semiconductor chips 2 pass through peeling layer 3 respectively and are attached at the load
The first face and the second face of plate 1；
Encapsulated layer 4 positioned at the first face of the support plate 1 and the second face and covers the semiconductor chip 2, the semiconductor
The front of chip 2 exposes to the encapsulated layer 4；
Transport layer, wiring layer 6 and antenna stack 7, the side positioned at the encapsulated layer 4 far from the support plate 1, the transport layer
Side and the front of the encapsulated layer 4 and the semiconductor chip 2 be electrically connected, the other side and the wiring layer 6 and described
Antenna stack 7 is electrically connected, and the wiring layer 6 has pad area 61 and non-pad area 62；
Solder mask 8, side positioned at the encapsulated layer 4 far from the support plate 1 simultaneously cover the antenna stack 7 and the wiring
The outside of the non-pad area 62 of layer 6；
Metal coupling 9 is welded with the pad area 61 of the wiring layer 6.
In the present embodiment, unless otherwise specified, term " covering " refers both to wrap some component non-contact with other component
Outer surface.For example, solder mask 8 covers antenna stack 7, refer to that solder mask 8 wraps antenna stack 7 and seed layer 5 is non-contacting
Outer surface.
Antenna packages structure is respectively set on the two sides of support plate 1 in the present embodiment, and two sides encapsulated layer 4 is combined closely with support plate 1
Together, the generation of surface warp will not be caused because of the performance difference of material, can guarantee well production when precision, at
Product rate and welding stability；And wiring layer 6 and antenna stack 7 are respectively provided on the level of the transport layer, i.e., wiring layer 6 and antenna stack 7 are located at same
On one horizontal plane, volume shared by antenna stack 7 can be reduced.Compared with prior art, the big plate fan-out-type two-sided antenna of the present embodiment
Small in size, encapsulating structure connection and reasonable arrangement shared by the antenna stack 7 of encapsulating structure, can be improved the integration performance of antenna packages structure with
The efficiency of antenna, and reduce the power consumption of antenna packages structure.
The size of big plate in the present embodiment is 600mm*600mm, but is not limited to the size, in other examples,
It can also be designed according to specific application product suitably sized.
Optionally, support plate 1 is stainless steel, glass or FR5 material, is fitted on support plate 1 convenient for peeling layer 3.
Wherein, peeling layer 3 is interim bonding material, convenient for fitting and subsequent separation.
Optionally, metal coupling 9 is tin solder, silver solder or gold-tin eutectic solder, and the present embodiment is preferably tin solder
Manufactured tin ball, tin ball bonding are implanted in pad area 61, to realize that the electrical of wiring layer 6 is drawn.
In the present embodiment, the semiconductor chip 2 includes bare chip 201, the end I/O 202 in the bare chip 201
Be convexly equipped in the connecting column 203 that the bare chip 201 is outer and is electrically connected with the end I/O 202, the connecting column 203 is separate
One end of the bare chip 201 is parallel to the surface of the encapsulated layer 4 and connect with the transport layer.Wherein, connecting column 203 is
Conductive metal material, preferably copper post.The semiconductor chip 2 of the present embodiment carries connecting column 203, can simplify subsequent encapsulation work
Skill；And the front (connecting column 203) of semiconductor chip 2 faces away from the side of support plate 1, the front setting with semiconductor chip exists
The side for facing away from support plate is compared, and the connection of semiconductor chip 2 and support plate 1 more closely, can be to avoid because being completely embedded type
Generation that is poor and causing surface warp.
Further, the transport layer includes the dielectric layer being affixed on the encapsulated layer 4 and is attached on the dielectric layer
Seed layer 5, the dielectric layer along its thickness direction have keep the connecting column 203 of the semiconductor chip 2 exposed via hole, institute
It states seed layer 5 and extends in the via hole and be electrically connected with the connecting column 203.Wherein, dielectric layer is ABF (Ajinomoto
Build-up Film) or PP (Polypropylene, polypropylene) material, it is attached on encapsulated layer 4, plays the role of insulation.
Wherein, dielectric layer is being not shown in the figure.
Further, the seed layer 5 include be located at titanium coating of the encapsulated layer 4 far from 1 side of support plate and
Copper metal layer on the titanium coating.Wherein, the adhesive force of titanium coating is high, conductivity is excellent and thickness is uniform, leads to
Crossing titanium coating can be attached to copper metal layer stabilization on encapsulated layer 4.Optionally, titanium coating with a thickness of 85~125nm,
Copper metal layer with a thickness of 275~325nm.
Further, the thickness of the antenna stack 7 is less than the thickness of the wiring layer 6, will not additionally occupy volume.Its
In, the surface of antenna stack 7 is rough surface.
In the present embodiment, the thickness of the antenna stack 7 is unrestricted, depending on the design requirement of electronic product.
There is gap between the pad area 61 and the solder mask 8 of the wiring layer 6, be convenient for welding metal convex block 9.
In the present embodiment, the solder mask 8 is photosensitive printing ink layer.Using photosensitive-ink as solder mask 8, can both play
The effect of wiring layer 6 and antenna stack 7 is protected, and technique can be simplified by exposure, development removal Some seeds layer 5.
Optionally, the material of encapsulated layer 4 includes polyimides, silica gel and EMC (Epoxy Molding Compound, ring
Oxygen plastic packaging material), the preferred EMC of the present embodiment, i.e., the described encapsulated layer 4 is epoxy resin encapsulated layer, and semiconductor chip 2 can be made to stablize
It is fitted on support plate 1, plays the role of protecting semiconductor chip 2.
As shown in figure 20, the embodiment of the present invention also provides a kind of preparation side of big plate fan-out-type two-sided antenna encapsulating structure
Method, comprising the following steps:
S10, support plate 1 and several semiconductor chips 2 are provided, encapsulated layer 4 is respectively adopted by part 2 envelope of semiconductor chip
The second side of the support plate 1 is encapsulated in mounted in the first side of the support plate 1 and by the remaining semiconductor chip 2, and
The front of the semiconductor chip 2 is set to face away from the side of the support plate 1；
S20, transport layer is made on the encapsulated layer 4, keeps the front of the semiconductor chip 2 and the transport layer electrical
Connection；
S30, wiring layer 6 and antenna stack 7 are made in the transport layer；
S40, photosensitive-ink is coated far from the one side of the support plate 1 in the encapsulated layer 4, forms solder mask 8, and make described
Solder mask 8 covers the non-pad area 62 of the wiring layer 6 and the antenna stack 7 and makes outside the pad area 61 of the wiring layer 6
It is exposed to the solder mask 8；
S50, metal coupling 9 is provided, metal coupling 9 is implanted into the pad area 61.
In the step S40 of the present embodiment, photosensitive-ink is uniformly coated on encapsulated layer 4, wiring layer 6 by way of printing
Non- pad area 62 and the antenna stack 7 on, then carry out pre-baked processing.
The present embodiment is successively packaged with semiconductor chip 2 in the two sides of support plate 1, and two sides encapsulated layer 4 is combined closely with support plate 1
Together, the generation of surface warp will not be caused because of the performance difference of material, can guarantee well production when precision, at
Product rate and welding stability；After the completion of semiconductor chip 2 encapsulates, two-sided transport layer, wiring layer 6, antenna stack 7 can be carried out simultaneously
And the production of solder mask 8, production efficiency can be effectively improved.Wiring layer 6 and antenna stack 7 are located at same level, 7 institute of antenna stack
Account for small in size, the integration performance of antenna packages structure and the effectiveness of antenna can be improved in encapsulating structure connection and reasonable arrangement,
And reduce the power consumption of antenna packages structure.
In the present embodiment, semiconductor chip 2 includes 21 He of the first semiconductor chip to be attached at the first face of support plate 1
To be attached at second semiconductor chip 22 in the second face of support plate 1, the first semiconductor chip 21 and the second semiconductor chip 22
Structure it is identical, the position that is only arranged is different.Accordingly, peeling layer 3 includes being attached at the first semiconductor chip 21 and carrying
Second peeling layer of first peeling layer 31 and the second face for being attached at the second semiconductor chip 22 and support plate 1 in the first face of plate 1
32, the first peeling layer 31 is identical with the structure and material of the second peeling layer 32, and the position being only arranged is different；Accordingly, it seals
Dress layer 4 includes the first semiconductor chip 21 being encapsulated in first encapsulated layer 41 in the first face of support plate 1 and by the second semiconductor core
Piece 22 is encapsulated in second encapsulated layer 42 in the second face of support plate 1, the structure and material of the first encapsulated layer 41 and the second encapsulated layer 42
Identical, the position being only arranged is different.
As shown in figure 21, step S10 specifically includes the following steps:
S10a, support plate 1 and the first peeling layer 31 are provided, first peeling layer 31 is affixed on to the first face of the support plate 1
(intermediate products obtained can refer to Fig. 1), in order to the fitting of the first semiconductor chip 21 in step S10b, wherein the first stripping
Absciss layer 31 is interim bonding material；
S10b, several first semiconductor chips 21 are provided, can be pasted first semiconductor chip 21 by chip mounter
In on first peeling layer 31, and the front of first semiconductor chip 21 is made to face away from the side (system of the support plate 1
The intermediate products obtained can refer to Fig. 2)；
S10c, make the first encapsulated layer 41 in the first wheat flour of the support plate 1, first encapsulated layer 41 is made to cover described the
On one side with first semiconductor chip 21 (intermediate products obtained can refer to Fig. 3), i.e., mould EMC by vacuum pressing-combining first
Envelope material tight lives the first semiconductor chip 21, then solidifies EMC plastic packaging material through high temperature, so that the first encapsulated layer 41 is formed,
To play the role of protecting the first semiconductor chip 21；
S10d, the second peeling layer 32 is provided, overturns the support plate 1, second peeling layer 32 is affixed on the support plate 1
Second face (intermediate products obtained can refer to Fig. 4), in order to the fitting of the second semiconductor chip 22 in step S10e, wherein
First peeling layer 31 is interim bonding material；
S10e, several second semiconductor chips 22 are provided, second semiconductor chip 22 is affixed on by institute by chip mounter
It states on the second peeling layer 32, and the side for making the front of second semiconductor chip 22 face away from the support plate 1 is (obtained
Intermediate products can refer to Fig. 5)；
S10f, make the second encapsulated layer 42 in the second wheat flour of the support plate 1, second encapsulated layer 42 is made to cover described the
Two faces and second semiconductor chip 22 (intermediate products obtained can refer to Fig. 6), i.e., mould EMC by vacuum pressing-combining first
Envelope material tight lives the second semiconductor chip 22, then solidifies EMC plastic packaging material through high temperature, so that the second encapsulated layer 42 is formed,
To play the role of protecting the second semiconductor chip 22.
As shown in figure 22, the step S20 specifically includes the following steps:
S20a, first encapsulated layer 41 and second encapsulated layer 42 are ground simultaneously, makes described the first half to lead
It is exposed that the connecting column 203 of body chip 21 exposes to first encapsulated layer 41, the connecting column 203 of second semiconductor chip 22
In second encapsulated layer 42 (intermediate products obtained can refer to Fig. 7)；Specifically, the connecting column of the first semiconductor chip 21
The flush on 203 surface and the first encapsulated layer 41, the surface of the connecting column 203 of the second semiconductor chip 22 and the second encapsulation
The flush of layer 42；
S20b, dielectric layer is provided, first encapsulated layer 41 after the dielectric layer to be affixed on to grinding respectively and described the
On two encapsulated layers 42, the insulation processing of the first encapsulated layer 41 and second encapsulated layer 42 is realized；
S20c, laser drill (UV laser) is carried out to the dielectric layer, formed the dielectric layer along its thickness direction
Hole, so that the connecting column 203 of the connecting column 203 of first semiconductor chip 21 and second semiconductor chip 22 is exposed,
Convenient for the connection of subsequent conditioning circuit；
S20d, seed layer 5 is formed in the dielectric layer and the via hole by vacuum sputtering, the dielectric layer and described
Seed layer 5 forms the transport layer (intermediate products obtained can refer to Fig. 8)；
Preferably, it is heated first in high vacuum state to through intermediate products made from step S20c, on intermediate products
Moisture and pollutant removal after, then there is high adhesion force, excellent conductivity and in homogeneous thickness by magnetron sputtering preparation
Titanium coating, thickness about 85~125nm finally prepare copper metal layer by magnetron sputtering again, thickness about 275~325nm,
The titanium coating and the copper metal layer form the seed layer.
As shown in figure 23, the step S30 specifically includes the following steps:
S30a, the first photosensitive dry film 101 is provided, first photosensitive dry film 101 is attached in the transport layer and (is made
Intermediate products can refer to Fig. 9)；
S30b, it is exposed by first time, development treatment, being formed on first photosensitive dry film 101 has blind hole and make
The transport layer exposes to the first graphical hole 102 of the through-hole of first photosensitive dry film 101, and (intermediate products obtained can join
Examine Figure 10)；
S30c, electroplating processes are carried out to the described first graphical hole 102, is formed and is filled out in the described first graphical hole 102
Fill layer 11 (intermediate products obtained can refer to Figure 11)；
S30d, the second photosensitive dry film 103 is provided, second photosensitive dry film 103 is attached at first photosensitive dry film
101 and the filled layer 11 on (intermediate products obtained can refer to Figure 12)；
S30e, it is exposed by second, development treatment, being formed on second photosensitive dry film 103 makes to fill out described in part
The second graphical hole 104 that layer 11 exposes to second photosensitive dry film 103 is filled, is covered by second photosensitive dry film 103
11 part of filled layer forms the wiring layer 6 (intermediate products obtained can refer to Figure 13)；
S30f, super roughening treatment is carried out to the filled layer 11 in the second graphical hole 104, makes the filled layer
11 thickness is reduced to form the antenna stack 7, and so that roughness is reached the requirement of antenna (intermediate products obtained can refer to figure
14)。
In the present embodiment, the first photosensitive dry film 101 and the second photosensitive dry film 103 are the high photosensitive dry film parsed, are passed through
Laminator can be entirely attached in seed layer 5.
Step S30b is specifically included: LDI (Laser Direct Imaging) exposure machine is used, it will by UV or laser light
Required image data is transferred on the first photosensitive dry film 101, and the graphic width of exposure region is 10~35um in data, non-exposed
The graphic width in area is 10~35um, then is removed the first photosensitive dry film 101 of unexposed area by development, forms the first figure
Change hole 102, leave the figure by UV or laser light irradiation, the first graphical hole 102 has blind hole and makes the kind of the transport layer
Sublayer 5 exposes to the through-hole of first photosensitive dry film 101.Wherein, exposure region and the graphic width of non-exposed area are not limited to
Above range, depending on the design requirement of concrete foundation electronic product.
Step S30c is specifically included: carrying out figure to the first graphical hole 102 (the part copper metal layer and blind hole of exposing)
Plating forms the filled layer 11 of fine copper, wherein the overall thickness of copper metal layer and filled layer 11 in seed layer 5 be 15~20um but
It is not limited to the range, depending on the design requirement of concrete foundation electronic product, blind hole fills plumpness 95% or more.
Step S30e is specifically included: using LDI exposure machine, required image data is transferred to the by UV or laser light
On two photosensitive dry films 103, then pass through development and remove the second photosensitive dry film 103 of unexposed portion, forms second graphical hole
104, the figure by UV or laser light irradiation is left, the filled layer 11 covered by the figure is wiring layer 6.
Further, the preparation method of the big plate fan-out-type two-sided antenna encapsulating structure of the present embodiment is in the step S30
Further include step S31 between the step S40, the step S31 specifically includes the following steps:
S31a, remaining first photosensitive dry film 101 of removal and (the intermediate production obtained of second photosensitive dry film 103
Product can refer to Figure 15)；
S31b, etching solution is provided, using the etching solution to first photosensitive dry film 101 and second photosensitive dry film
103, which are removed rear exposed seed layer 5, is etched, and to remove the seed layer 5, (intermediate products obtained can refer to figure
16)。
Further, step S31b includes: to remove copper metal using the etching solution being made of sulfuric acid and hydrogen peroxide first
Layer, then titanium coating is removed using the etching solution of ammonium acid fluoride and hydrogen peroxide composition.
Figure 17 is referred to through intermediate products made from step S40, solder mask 8 (photosensitive-ink) covers the non-of the wiring layer 6
The outside of pad area 62 and the antenna stack 7.
Further, the step S50 specifically includes the following steps:
S50a, it is exposed by third time, development treatment, forms the pad area for making the wiring layer 6 on the solder mask 8
61 expose to the through-hole of the solder mask 8 (intermediate products obtained can refer to Figure 18)；
S50b, the metal coupling 9 is provided, the metal coupling 9 is implanted into the 61 (intermediate products obtained of pad area
It can refer to Figure 19).
By photosensitive-ink after the pre-baked processing of step S40, solder mask 8 is formed；Then LDI exposure machine is used, is led to
It crosses UV or laser light required image data is transferred on solder mask 8, then passes through development treatment for the photosensitive of unexposed portion
Ink removal, formation make the pad area 61 of the wiring layer 6 expose to the through-hole of the solder mask 8, leave by UV or laser light
The figure of irradiation then carries out baking-curing processing to solder mask 8；Finally by metal coupling 9 be implanted into pad area 61, obtain as
Big plate fan-out-type two-sided antenna encapsulating structure shown in Figure 19.
Support plate 1 can be made to separate with the product of its two sides to get arriving final product by tearing bonding open.
In conclusion the preparation method of big plate fan-out-type two-sided antenna encapsulating structure of the invention, in the two sides of support plate
Semiconductor chip and antenna are packaged respectively, two sides encapsulated layer is closely linked with support plate, will not be because of material
Performance difference causes the generation of surface warp, can guarantee precision, yield rate and welding stability when production, and energy well
Effectively improve packaging efficiency；Wiring layer and antenna stack are located at same level, small in size, encapsulating structure arrangement conjunction shared by antenna stack
Reason, improves the integration performance of antenna packages structure, effectively shortens the signal transmission line of element in encapsulating antenna structure, drops
The low power consumption of antenna packages structures.
It is to be understood that above-mentioned specific embodiment is only that presently preferred embodiments of the present invention and institute's application technology are former
Reason.It will be understood by those skilled in the art that various modifications, equivalent replacement, variation etc. can also be done to the present invention.But this
It is a little to convert and to the equivalence replacement of each raw material of product of the present invention and addition, selection of concrete mode of auxiliary element etc., all answer
Within protection scope of the present invention.In addition, some terms used in present specification and claims are not limit
System, it is only for convenient for description.
Claims (10)
1. a kind of big plate fan-out-type two-sided antenna encapsulating structure characterized by comprising
Support plate has opposite the first face and the second face along its thickness direction；
Several semiconductor chips, the back side of several semiconductor chips pass through peeling layer is attached at the support plate first respectively
Face and the second face；
Encapsulated layer positioned at the first face of the support plate and the second face and covers the semiconductor chip, the semiconductor chip
Front exposes to the encapsulated layer；
Transport layer, wiring layer and antenna stack, the side positioned at the encapsulated layer far from the support plate, the side of the transport layer with
The front of the encapsulated layer and the semiconductor chip is electrically connected, and the other side electrically connects with the wiring layer and the antenna stack
It connects, the wiring layer has pad area and non-pad area；
Solder mask, side positioned at the encapsulated layer far from the support plate and the non-weldering for covering the antenna stack and the wiring layer
The outside in panel；
Metal coupling is welded with the non-pad area of the wiring layer.
2. big plate fan-out-type two-sided antenna encapsulating structure according to claim 1, which is characterized in that the semiconductor chip
Including bare chip, the end I/O in the bare chip and it is convexly equipped in outside the bare chip and is electrically connected with the end I/O
Connecting column, the connecting column are parallel to the surface of the encapsulated layer far from one end of the bare chip and connect with the transport layer
It connects.
3. big plate fan-out-type two-sided antenna encapsulating structure according to claim 1, which is characterized in that the transport layer includes
The dielectric layer being affixed on the encapsulated layer and the seed layer being attached on the dielectric layer, the dielectric layer have along its thickness direction
There is the via hole for keeping the connecting column of the semiconductor chip exposed, the seed layer extends to electric with the connecting column in the via hole
Property connection.
4. big plate fan-out-type two-sided antenna encapsulating structure according to claim 3, which is characterized in that the seed layer includes
Titanium coating positioned at the encapsulated layer far from the support plate side and the copper metal layer on the titanium coating.
5. big plate fan-out-type two-sided antenna encapsulating structure according to claim 1, which is characterized in that the thickness of the antenna stack
Degree is less than the thickness of the wiring layer.
6. a kind of preparation method of big plate fan-out-type two-sided antenna encapsulating structure, which comprises the following steps:
S10, support plate and several semiconductor chips are provided, encapsulated layer is respectively adopted by the part semiconductor chip packaging described
The first side of support plate and by the remaining semiconductor chip packaging in the second side of the support plate, and make the semiconductor
The front of chip faces away from the side of the support plate；
S20, transport layer is made on the encapsulated layer, is electrically connected the front of the semiconductor chip with the transport layer；
S30, wiring layer and antenna stack are made in the transport layer；
S40, photosensitive-ink is coated far from the one side of the support plate in the encapsulated layer, forms solder mask, and make the solder mask
It covers the non-pad area of the wiring layer and the antenna stack and the pad area of the wiring layer is made to expose to the solder mask；
S50, metal coupling is provided, the metal coupling is implanted into the pad area.
7. the preparation method of big plate fan-out-type two-sided antenna encapsulating structure according to claim 6, which is characterized in that described
Step S10 specifically includes the following steps:
S10a, support plate and the first peeling layer are provided, first peeling layer is affixed on to the first face of the support plate；
S10b, several first semiconductor chips are provided, first semiconductor chip is affixed on first peeling layer, and is made
The front of first semiconductor chip faces away from the side of the support plate；
S10c, the first wheat flour the first encapsulated layer of work in the support plate, make first encapsulated layer cover first face and institute
State the first semiconductor chip；
S10d, the second peeling layer is provided, overturns the support plate, second peeling layer is affixed on to the second face of the support plate；
S10e, several second semiconductor chips are provided, second semiconductor chip is affixed on second peeling layer, and is made
The front of second semiconductor chip faces away from the side of the support plate；
S10f, the second wheat flour the second encapsulated layer of work in the support plate, make second encapsulated layer cover second face and institute
State the second semiconductor chip.
8. the preparation method of big plate fan-out-type two-sided antenna encapsulating structure according to claim 7, which is characterized in that described
Step S20 specifically includes the following steps:
S20a, first encapsulated layer and second encapsulated layer are ground simultaneously, makes first semiconductor chip
Connecting column exposes to first encapsulated layer, the connecting column of second semiconductor chip exposes to second encapsulated layer；
S20b, dielectric layer is provided, first encapsulated layer and second encapsulation after the dielectric layer to be affixed on to grinding respectively
On layer；
S20c, laser drill is carried out to the dielectric layer, the dielectric layer is made to form via hole along its thickness direction, for described the
The connecting column of the connecting column of semiconductor chip and second semiconductor chip is exposed；
S20d, seed layer, the dielectric layer and the seed are formed in the dielectric layer and the via hole by vacuum sputtering
Layer forms the transport layer.
9. the preparation method of big plate fan-out-type two-sided antenna encapsulating structure according to claim 6, which is characterized in that described
Step S30 specifically includes the following steps:
S30a, the first photosensitive dry film is provided, first photosensitive dry film is attached in the transport layer；
S30b, it is exposed by first time, development treatment, being formed on first photosensitive dry film has blind hole and make the transmission
Layer exposes to the first graphical hole of the through-hole of first photosensitive dry film；
S30c, electroplating processes are carried out to the described first graphical hole, forms filled layer in the described first graphical hole；
S30d, the second photosensitive dry film is provided, second photosensitive dry film is attached at first photosensitive dry film and the filling
On layer；
S30e, it is exposed by second, development treatment, being formed on second photosensitive dry film keeps the part filled layer exposed
In the second graphical hole of second photosensitive dry film, formed by the filled layer part that second photosensitive dry film covers
The wiring layer；
S30f, super roughening treatment is carried out to the filled layer in the second graphical hole, drops the thickness of the filled layer
It is low to form the antenna stack.
10. the preparation method of big plate fan-out-type two-sided antenna encapsulating structure according to claim 9, which is characterized in that institute
Stating between step S30 and the step S40 further includes step S31, the step S31 specifically includes the following steps:
S31a, remaining first photosensitive dry film and second photosensitive dry film are removed；
S31b, etching solution is provided, first photosensitive dry film and second photosensitive dry film is removed using the etching solution
Exposed seed layer is etched afterwards, to remove the seed layer.
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Effective date of registration: 20230329 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Applicant after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: 528225 room a208-1, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province Applicant before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |