CN100481420C - Stack type chip packaging structure, chip packaging body and manufacturing method thereof - Google Patents

Stack type chip packaging structure, chip packaging body and manufacturing method thereof Download PDF

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CN100481420C
CN100481420C CN 200510102505 CN200510102505A CN100481420C CN 100481420 C CN100481420 C CN 100481420C CN 200510102505 CN200510102505 CN 200510102505 CN 200510102505 A CN200510102505 A CN 200510102505A CN 100481420 C CN100481420 C CN 100481420C
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chip
layer
plurality
core layer
package
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CN 200510102505
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Chinese (zh)
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CN1929120A (en )
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吴政庭
周世文
潘玉堂
邱士峰
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南茂科技股份有限公司;百慕达南茂科技股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

本发明是有关于一种堆叠型芯片封装结构、芯片封装体及其制造方法。 The present invention relates to a stacked package, the chip package and method of manufacturing the chip. 该芯片封装体,其包括一封装基板、一芯片与一封装胶体。 The chip package that includes a package substrate, a chip and an encapsulant. 其中,封装基板包括一核心层与配置于核心层上的一图案化线路层。 Wherein the package substrate includes a core layer and a patterned circuit layer disposed on the core layer. 核心层具有一第一贯孔与多个第二贯孔,其中第一贯孔与这些第二贯孔分别暴露出部分图案化线路层。 A core layer having a first through hole and a plurality of second through holes, wherein the first through hole and the second through hole portion of the patterned circuit layer are exposed. 芯片配置于第一贯孔内,并与图案化线路层电性连接。 Chip is disposed first through hole, and electrically connected to the patterned circuit layer. 封装胶体配置于第一贯孔内,以将芯片固着于封装基板内。 Encapsulant disposed in the first through hole, fixed to the chip in the package substrate. 基于上述,本发明的芯片封装体的厚度能够变薄。 Based on the above, the thickness of the chip package of the present invention can be thinned. 此外,本发明亦提出一种堆叠型芯片封装结构与芯片封装体的制造方法。 Further, the present invention also provides a method for manufacturing a stacked chip package and chip package.

Description

堆叠型芯片封装结构、芯片封装体及其制造方法 Stacked chip package, the chip package and manufacturing method thereof

技术领域 FIELD

本发明是有关于一种封装结构,且特别是有关于一种具有高封装积集度的堆叠型芯片封装结构。 The present invention relates to a package structure, and more particularly to a stacked-type chip package on a high-packaged product set having the degree.

储" Reserve "

在现今的资讯社会中,使用者均是追求高速度、高品质、多工能性的电子产品。 In today's information society, users are pursuing high-speed, high-quality, multi-energy of electronic products. 就产品外观而言,电子产品的设计也朝向轻、薄、短、小的趋势迈进。 On product appearance, the design of electronic products toward light, thin, short, small tendency to move. 为了达到上述目的,许多公司在进行电路设计时,均融入系统化的概念,使得单颗芯片可以具备有多种功能,以节省配置在电子产品中的芯片数目。 To achieve the above object, many companies during circuit design, are integrated into systematic concept, such that a single chip may be provided with a variety of functions, arranged to save the number of chips in electronic products. 另外,就电子封装技术而言,为了配合轻、薄、短、小的设计趋势,亦 Moreover, in the electronic packaging technology, in order to fit the light, thin, short and small design trends, also

发展出多芯片才莫组(mu 11 i-chip modu 1 e, MCM )的封装i殳计概念、芯片尺寸构装(chip scale package, CSP )的封装设计概念及堆叠型多芯片封装设计的概念等。 Development of the concept of a multi-chip was mo group (mu 11 i-chip modu 1 e, MCM) of Shu count concept packaged i, chip size package as (chip scale package, CSP) package design concepts and stacked multi-chip package designs Wait. 以下就分别针对几种现有习知堆叠型芯片封装结构进行说明。 The following will separately be described several prior conventional stack-type chip package.

请参阅图l所示,是现有习知堆叠型芯片封装结构的剖面示意图。 Referring to FIG. L, it is a cross-sectional view of a conventional conventional stacked chip packaging structure. 现有习知的堆叠型芯片封装结构100包括一封装M( package substrate )110、 芯片120a、 120b、 一间隔物(spacer) 130、多条导线140与一封装胶体(encapsulant ) 150。 Existing conventional stacked-type chip package 100 includes a package structure M (package substrate) 110, the chip 120a, 120b, a spacer (spacer) 130, a plurality of leads 140 with encapsulant (encapsulant) 150. 其中,芯片120a与120b配置于封装M 110上,且间隔物130配置于芯片120a与120b之间。 Wherein the chip 120a and 120b disposed on the package M 110, and spacers 130 disposed between the die 120a and 120b. 部分导线140分别电性连接于芯片120a与封装基板110之间,而其他部分导线140则分别电性连接于芯片120b与封装基板110之间。 Portion of the wire 140 are electrically connected between the die 120a and the package substrate 110, while other portions of the wire 140 are electrically connected between the chip 110 and the package substrate 120b. 此外,封装胶体150配置于封装基板110上, 务包覆这些导线140、芯片120a与120b。 Further, the encapsulant 150 is disposed on the package substrate 110, the wire 140 covered traffic, chips 120a and 120b.

由于芯片120a与120b之间必须相距一定的距离,以便于进行打线制程(wire bonding process h因此现有习知堆叠型芯片封装结构100的整体厚度会因为间隔物130的厚度而无法进一步缩减。此外,现有习知堆叠型芯片封装结构100也会产生散热方面的问题。因此,为了解决上述问题,发展出另一种堆叠型芯片封装结构。 Since it is necessary between a distance from the chip 120a and 120b, in order to facilitate wire bonding process (wire bonding process h Therefore, the overall thickness of the prior conventional stack-type chip package structure 100 because of the thickness of the spacer 130 can not be further reduced. Further, the prior conventional stack-type chip package structure 100 also generates heat issues. Accordingly, in order to solve the above problems, the development of another stacked chip package.

请参阅图2所示,是另一现有习知堆叠型芯片封装结构的剖面示意图。 See FIG. 2 is a schematic cross-sectional view of another prior conventional stack-type chip package structure. 现有习知的堆叠型芯片封装结构10包括一封装基板12与多个芯片封装体200a、 200b,其中这些芯片封装体200a、 200b堆叠于封装基板12上,并与封装基板12电性连接。 Existing conventional stacked-type chip package 10 includes a package substrate 12 and a plurality of chip packages 200a, 200b, wherein the chip package 200a, 200b stacked on the package substrate 12 and electrically connected to the package substrate 12. 每一芯片封装体200a、 200b包括一封装基板210、 一芯片220、多个凸块230、 一底胶240与多个焊J求250。 Each chip package 200a, 200b includes a package substrate 210, a chip 220, a plurality of bumps 230, 240 and a plurality of bonding primer 250 J demand. 芯片220与这些凸块230配置于封装4^1 210上,而这些凸块230配置于芯片220与封装基板210之间,且芯片220经由这些凸块电性连接至封装基板210。 The chip 220 with bumps 230 disposed on the package 4 ^ 1210, and these projections 230 disposed between the chip 220 and the package substrate 210, and the chip connected to the package substrate 220 via the bumps 210 electrically. 底胶240配置于芯片220与封装基板210之间,以包覆这些凸块230。 Primer 240 is disposed between the chip 220 and the package substrate 210 to cover the bumps 230.

封装基板210具有多个导电柱212与多个焊球垫214,其中这些导电柱212分别貫穿封M板210,且这些焊球垫214分别配置于这些导电柱212 上。 The package substrate 210 having a plurality of conductive pillars 212 and plurality of solder balls pads 214, 212, respectively, wherein the conductive post penetrating M sealing plate 210, and pads 214 are solder balls disposed on the conductive pillars 212. ,此外,这些焊球250配置于这些焊球垫214上。 In addition, the solder balls 250 arranged on the solder balls 214 on the pads. 值得注意的是,芯片封装体200a与200b经由焊球250彼此电性连接,而芯片封装体200b经由焊球250电性连接至封装基板12。 It is noted that the chip package 200a are electrically connected to each other via the solder balls 250 and 200b, 200b and the chip package 12 is connected to the package substrate 250 via the solder balls electrically.

相较于现有习知的堆叠型芯片封装结构100,此种现有习知的堆叠型芯片封装结构10虽然制程复杂度较低,但此种现有习知的堆叠型芯片封装结构IO的厚度却是大于现有习知的堆叠型芯片封装结构IOO的厚度。 Compared to the conventional stacked-type chip package structure 100, while the lower 10 process complexity, but such prior conventional stack-type chip package structure of such conventional IO conventional stacked-type chip package structure the thickness is the thickness of the stacked chip packaging structure IOO greater than conventional prior art.

发明内容 SUMMARY

有鉴于此,本发明的目的:lfc^在提^^^种芯片封装体,其胁的厚度较薄。 In view of this, object of the present invention: lfc ^ ^^^ kind mentioned in the chip package, the thickness of the thin threat. 此外,本发明的再一目的就是提供一种堆叠型芯片封装结构,其具有较高的封装积集度。 Further, another object of the present invention is to provide a stacked chip package, a package having a high degree of product set.

另外,本发明的又一目的就是提供一种芯片封装体的制造方法,以制造出疾'k式芯片封装体。 Further, still another object of the present invention is to provide a method of manufacturing a chip package, to produce the disease 'k chip package.

基于上述目的或其他目的,本发明提出一种芯片封装体,其包括一封装基板、 一芯片与一封装胶体。 Based on the above object and other objects, the present invention provides a chip package, comprising a package substrate, a chip and an encapsulant. 其中,封装基板包括一核心层(core layer) 与配置子核心层上的一困案化线路层。 Wherein the package substrate includes a core layer (core layer) and a patterned wiring layer stuck on the sub-core configuration. 核心层具有上表面与下表面,且图案化线路层配置于核心层的上表面,核心层具有一第一贯孔与多个第二贯孔,其中第一贯孔与这些第二贯孔分别暴露出位于核心层上表面的部分图案化线路层。 A core layer having an upper surface and a lower surface, and a patterned circuit layer disposed on the surface of the core layer, the core layer having a first through hole and a plurality of second through holes, wherein the first through hole and the second through holes, respectively, exposing portions of the patterned circuit layer is located on the surface of the core layer. 芯片配置于第一贯孔内,并与图案化线路层电性连接。 Chip is disposed first through hole, and electrically connected to the patterned circuit layer. 封装胶体配置于第一贯孔内,以将芯片固着于封装基板内,且封装胶体暴露出芯片的远离困案化线路层的表面。 Encapsulant disposed in the first through hole, fixed to the chip in the package substrate, and the surface of the encapsulant to expose the chip away from the trapped patterned circuit layer. 外部连接端子分别配置在第二贯孔内,且每一外部连接端子经由位于核心层上表面的图案化线路层而电性连接至芯片。 External connection terminals are disposed in a second through hole, and each external connection terminal via a patterned circuit layer disposed on the surface of the core layer is electrically connected to the chip.

.依照本发明实施例,芯片封装体更可以包括多个凸块,其配置于芯片与图棄森^l路层之间,而芯片经由这些凸块电性连接至图案化线路层,且封装胶体包袭这些凸块。 In accordance with an embodiment of the present invention, the chip package may further include a plurality of bumps disposed between the chip and discarded Tucson ^ l FIG path layer, and via these chip connection bumps electrically to the patterned circuit layer, and packaged these projections colloidal package passage. 此外,封^M体可以是暴露出芯片的远离图案化线路层的表面u Further, sealing ^ M may be a chip away from the exposed surface of the patterned circuit layer, u

依照本发明实施例,芯片封装体更可以包括多条导线,其中芯片经由这些务线电性连接至困案化线路层,且封装胶体包覆这些导线。 In accordance with an embodiment of the present invention, the chip package may further include a plurality of wires, wherein the chip is connected via the service line to electrically trapped patterned circuit layer, and the wires coated with encapsulant.

基于上迷目的或其他目的,本发明提出一种堆叠型芯片封装结构,其包 On a fan or other purposes, the present invention provides a stacked chip package, which package

括一共同承栽器与多个芯片封装体,其中这些芯片封装体堆叠于共同承栽器上,并与共同承栽器电性连接。 Comprising a plurality of co-bearing plant with the chip package, wherein the chip package is stacked on a common bearing plant, and a common bearing electrically connected to the plant. 每一芯片封装体包括一封装基板、 一芯片与一封装胶体。 Each chip package comprises a package substrate, a chip and an encapsulant. 其中,封装基板包括一核心层与配置于核心层上的一图案化线路层。 Wherein the package substrate includes a core layer and a patterned circuit layer disposed on the core layer. 核心层具有上表面与下表面,且图案化线路层配置于核心层的上表面.核心层具有一第一贯孔与多个第二贯孔,其中第一贯孔与这些第二贯孔分别暴露出位于核心层上表面的部分图案化线路层。 A core layer having an upper surface and a lower surface, and a patterned circuit layer disposed on the surface of the core layer. The core layer having a first through hole and a plurality of second through holes, wherein the first through hole and the second through holes, respectively, exposing portions of the patterned circuit layer is located on the surface of the core layer. 芯片配置于第 The first chip is disposed

一贯孔内,并与闺案化线路层电性连接。 Always bore and the Inner layer is electrically connected to the patterned circuit. 封装胶体配置于第一贯孔内,以将芯片固着于封装基板内,且封装胶体暴露出芯片的远离图案化线路层的表面。 Encapsulant disposed in the first through hole, fixed to the chip in the package substrate, and the surface of the chip away from the encapsulant to expose the patterned wiring layer. 这些外部连接端子分别配置于这些第二贯孔内,且每一外部连接端子经由位于核心层上表面的图案化线路层电性连接至芯片。 These external connection terminals are disposed in the second through hole, and each external connection terminal is connected to the chip via electrical lines patterned layer positioned on the surface of the core layer. 每一芯片封装体经由对应的这些外部连接端子电性连接至共同承栽器或另一芯片封装体。 Each chip package via these external connection terminal connected electrically to the corresponding common bearing plant or another chip package.

依照本发明实施例,共同承栽器可以是电路板或导线架。 In accordance with embodiments of the present invention, a common bearing plant may be a circuit board or a lead frame.

基于上述目的或其他目的,本发明提出一种芯片封装体的制造方法,其包括下列步槺。 Based on the above object and other objects, the present invention provides a method of manufacturing a chip package, comprising the following steps Kang. 首先,提供一芯片与一封装^,其中封装基板包括一核心层与酶置于核心层上的一图案化线路层,核心层具有上表面与下表面,且图案化钱路层配置于核心层的上表面,而在核心层内已形成一第一贯孔与多个第二贯孔,且第一贯孔与这些第二贯孔分别暴露出位于核心层上表面的部分图案化线路层。 First, a chip and a package ^, wherein the package substrate includes a core layer and an enzyme layer disposed on a circuit patterned core layer, the core layer having an upper surface and a lower surface, and a patterned layer disposed on the path of money core layer the upper surface, and is formed in the core layer has a first through hole and a plurality of second through holes, and the first through hole and the second through holes which expose portions of the patterned circuit layer located on the surface of the core layer. 将芯片配置于第一贯孔内,以使芯片与图案化线路层电性连接。 The chip is disposed first through hole, so that the chip and the patterned layer is electrically connected to the line. 在第一貫孔内形成一封装胶体,以将芯片固着于封装^内,且封装胶体暴露出芯片的远离困案化线路层的表面。 A first through hole formed in the encapsulant, fixing the chip to the package ^ inner surface of the encapsulant and the chip is exposed trapped away from the line patterned layer. 在第二贯孔内形成多个外部连接端子,且每一外部连接端子经由位于核心层上表面的图案化线路层电性连接至芯片。 A plurality of external connection terminals are formed in the second through hole, and each external connection terminal is connected to the chip via electrical lines patterned layer positioned on the surface of the core layer.

依照本发明实施例,芯片封装体的制造方法更可以在芯片与图案化线路层之间形成多个凸块,且芯片经由这些凸块电性连接至图案化线路层。 In accordance with an embodiment of the present invention, a method of manufacturing a chip package may further be formed a plurality of bumps between the chip and the patterned circuit layer, and the chip is connected to the patterned circuit layer is electrically via these bumps.

依照本发明实施例,芯片封装体的制造方法更可以形成多条导线,且这些專线连接芯片与困案化线路层之间。 In accordance with an embodiment of the present invention, a method of manufacturing a chip package can also be formed plurality of wires, and the connection between the chip and the circuit layer trapped text line.

基于上迷,本发明将芯片嵌入封装基板的核心层内,因此所形成的堆叠型芯片封装结构或是芯片封装体的厚度均可变薄。 Based on the fan, the present invention is a core layer embedded in a chip package substrate, so stacked chip package structure or thickness of the chip package can be formed thinner.

为让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附困式,作详细说明如下。 To make the above and other objects, features and advantages of the present invention can be more fully understood by reading the following preferred embodiments and the accompanying difficulties with the formula described in detail below.

附曙藝明 Attached Shu Yi-ming

困l是现有习知堆叠型芯片封装结构的剖面示意图。 L is a sectional view of a conventional trapped conventional stacked chip packaging structure.

图2是另一现有习知堆叠型芯片封装结构的剖面示意图。 FIG 2 is a schematic cross-sectional view of another prior conventional stack-type chip package structure. 围3A至困犯是依照本发明第一实施例的堆叠型芯片封装结构的制造流穉剩面示意困。 Wai 3A is made according to the manufacturer to trapped stacked chip packaging structure of the first embodiment of the present invention is a schematic flow Zhi left side trapped.

困4A至困4B是依照本发明笫二实施例的堆叠型芯片封装结构的制造流程剖面承意困. 4A to 4B are trapped trapped sectional manufacturing process in accordance with stacked bearing intended Zi chip packaging structure of the second embodiment of the present invention trapped.

困5是依照本发明第三实施例的芯片封装结构的剖面示意图。 5 is a schematic cross-sectional trapped chip package in accordance with a third embodiment of the present invention. 10、 100:现有习知的堆叠型芯片封装结构12、 110、 210、 310:封装基板20、 30:堆叠型芯片封装结构 10, 100: existing conventional stacked type chip packaging structure 12, 110, 210, 310: 20, the package substrate 30: stacked chip package structure

22、 32:共用承栽器 22, 32: bearing plant is a common

22a、 22b、 214、 360:焊球垫 22a, 22b, 214, 360: solder ball pad

24、 250、 370:焊球 24, 250, 370: solder ball

120a、 120b、 220、 320、 410:芯片 120a, 120b, 220, 320, 410: chip

130:间隔物 130: spacer

140、 420:导线 140, 420: wire

150、 340、 430:封装胶体 150, 340, 430: encapsulant

200a、 200b、 300a、 300b、 300c、 400a、 400b、 400c、 500a:芯片封 200a, 200b, 300a, 300b, 300c, 400a, 400b, 400c, 500a: chip package

装体 Exterior body

212、 350:导电柱230、 330:凸块240:底胶312:核心层312a:第一贯孔312b:第二贯孔314:图案化线路层316:焊罩层440:外部连接端子510:粘着层 212, 350: conductive pillars 230, 330: projection 240: primer 312: 312a of the core layer: first through hole 312b: second through hole 314: patterned circuit layer 316: solder mask layer 440: external connection terminal 510: adhesive layer

具体实施方式【第一实施例】 DETAILED DESCRIPTION [First embodiment]

图3A至图3E是依照本发明第一实施例的堆叠型芯片封装结构的制造it程剖面示意图。 3A to 3E are cross-sectional schematic diagram of a process for producing it stacked chip packaging structure of the first embodiment of the present invention. 请参阅图3A,本实施例的堆叠型芯片封装结构的制造方法包括下列步骤。 Please refer to Figure 3A, the present embodiment stacked chip package structure manufacturing method of the embodiment includes the following steps. 首先,提供一封装基板310,而封装J41310可以是电路板或是软性电路板。 First, a package substrate 310, and the package may be a circuit board or J41310 flexible circuit board. 此外,封装基板310包括一核心层312与配置于核心层312上的一图案化线路层314,其中核心层312可以是双顺丁烯二酸酰亚胺-三氮杂苯(Bismaleimide-Triazine,虹)材料、介电材料或其他薄膜材料„另外,封装基板310也可以包括一焊罩层316,而焊軍层316配置于核心层312上,并覆盖部分图案化线路层314。 In addition, the package includes a substrate 310 disposed on the core layer 312 and a patterned circuit layer 314 on the core layer 312, wherein the core layer 312 may be a dual maleic acid imide - triazine (Bismaleimide-Triazine, Hong) material, a dielectric material or other thin film material "Further, the package substrate 310 may comprise a solder mask layer 316, and solder layer 316 is disposed on the military core layer 312, and covers the portion of the patterned circuit layer 314.

然后,在核心层312内形成一第一贯孔312a与多个第二贯孔312b,且第一贯孔312a与这些第二贯孔312b分别暴露出部分图案化线路层314。 Then, a first through hole 312a is formed with a plurality of second through holes 312b in the core layer 312, first through hole and the second through holes 312a and 312b respectively exposing a portion of the patterned circuit layer 314. 此外i形成第一贯孔312a与第二贯孔312b的方法可以是雷射钻孔、机械钻孔或是其他能够形成贯孔的制程。 Moreover i formed first through hole 312a and through hole 312b of the second method may be laser drilling, mechanical drilling, or other processes capable of forming the through hole.

请参阅图3B所示,提供一芯片320,并将芯片320配置于第一贯孔312a内。 See FIG. 3B, a one-chip 320 and the chip 320 is disposed in the first through hole 312a. 然后,将芯片320与图案化线路层314电性连接,其中芯片320与图案化线路层314电性连接的方式可以是覆晶^N支术,就亂晶M技术而言,芯片320系藉由凸块330与图案化^U^层314电性连接.在本实施例中,凸块330 可以是形成在图案4匕线路层314上或是形成在芯片320上,然后再经过回烊(reflow)以使得芯片320能够藉由凸块330与图案化线路层314电性连接。 Then, the chip 320 is electrically connected to the pattern 314 of the circuit layer, the manner in which the chip 314 is electrically patterned circuit layer 320 and may be connected to the flip-chip technique branched ^ N, M chaos crystal technology, the chip 320 by means of line by the bumps 330 and the patterned ^ U ^ 314 is electrically connected to layer. in the present embodiment, the bump 330 may be formed on the pattern layer 4 dagger circuit formed on the chip 314 or 320, and then back through the molten ( reflow) so that the chip 320 can be electrically connected by the bumps 314 and the patterned circuit layer 330.

请参阅困3C所示,在第一贯孔312a内形成一封装胶体340,以将芯片320固着于封装^ 310内。 See trapped FIG. 3C, an encapsulant 340 formed in the first through hole 312a, the chip 320 adhered to the package in ^ 310. 在本发明的一实施例中,封装胶体340系包覆凸块330与部分困案化线路层314,至此,初步完成芯片封装体300a的制作。 In an embodiment of the present invention, the encapsulant 340 based cladding bump portion 330 and circuit layer 314 trapped case, thus, completed the initial production of the chip package 300a. 值得一提的是,本实施例的封^体340可暴露出芯片320的远离图案化线路层314的表面,以改善芯片320的散热效率。 It is worth mentioning that, according to the present embodiment of the seal 340 ^ 320 may be exposed surface of the chip away from the patterned circuit layer 314, to improve the heat dissipation efficiency of the chip 320. 换言之,封装胶体340暴露出芯片320的背面,然而封装胶体340也可以是完全包覆芯片320„ 此外,封装胶体340与封装基板310也可以是切齐,然而封装胶体340也可以是突出于封装基板310。 In other words, the back surface encapsulant 340 of chip 320 is exposed, however encapsulant 340 may be completely coated chip 320 "In addition, the encapsulant 340 and the package substrate 310 may be cut flush, however encapsulant 340 may be a protrusion in a package substrate 310.

请参阅图3D所示,在这些第二贯孔312b内形成多个导电柱350,以作为外部连接端子之用,且每一导电柱350经由图案化线路层314电性连接至芯片320,更详细而言,形成这些导电柱350的方式也可以是无电电镀制程、有电电镀^f线是其^^r属';t^制程.然而,也可以是将无铅焊料、^#焊料、其他类型的焊料或其他导电材质填入这些第二贯孔312b内,以形成外部连接端子(如困4A所示)。 Please refer to FIG. 3D, a plurality of conductive posts 350 are formed within the second through holes 312b, as with the external connection terminals, and each conductive pillar 350 is connected to the chip 320 via 314 electrically patterned circuit layer, and more specifically, these methods form a conductive pillar 350 may be an electroless plating process, electroless plating, there is the line F ^ ^^ r genus';. t ^ process, however, may be a lead-free solder, solder ^ # other types of solder or other conductive materials filled into the second through holes 312b, to form an external connection terminal (such as a storm. 4A). 就导电柱350作为外部连接端子而言,在这些导电柱350上形成多个焊球垫360.然后,在这些焊球垫360上形成多个焊球370,而这些焊球370可以是无铅焊球或是锡铅焊球。 Conductive pillars on the external connection terminals 350, the plurality of solder ball pads formed on the conductive pillars 350 360. Then, a plurality of solder balls 370 formed in the solder ball pad 360, which may be a lead-free solder balls 370 or tin-lead solder balls. 至此,大致完成芯片封装体300a的制作。 Thus, substantially complete the production of the chip package 300a.

请参阅图3E所示,重复上述的步骤,以制造出芯片封装体300b与300c。 Refer to FIG 3E, the above steps are repeated to manufacture a chip package 300b and 300c. 然后,提供一共用承栽器22,而共用承栽器22具有多个焊球垫22a与22b。 Then, there is provided a common bearing plant 22, the plant 22 having a common bearing pads plurality of solder balls 22a and 22b. 在本实施例中,共用承栽器22为电路板,但是共用承栽器22也可以是导线架。 In the present embodiment, the common bearing plant is a circuit board 22, but a common bearing plant 22 may be a wire frame. 然后,将芯片封装体300a、 300b与300c堆叠于共用承栽器22上, 其中这些芯片封装体300a、 300b与300c的焊球370与对应的焊球垫360 接触。 Then, the chip package 300a, 300b and 300c are stacked on a common bearing plant 22, wherein the chip package 300a, 360 and 300b in contact with the balls 300c corresponding to the solder ball pads 370. 此外,芯片封装体300c的焊球370与共用承栽器22的焊球垫22a 接触,然后,对于上述结构进行回烀制程(reflow process),以使得这些芯片封装体300a、 300b与300c彼此电性,并使得芯片封装体300c与共用承载器22连接. Furthermore, the chip package 370 solder balls 300c and the common ball bearing 22 is planted contact pads 22a, and then, the above-described configuration Hu-back process (reflow process), so that the 300a, 300b and 300c which are electrically chip package resistance, and 300c so that the chip package 22 is connected to the common carrier.

值得一提的是,这些芯片封装体300a、 300b与300c并不限定图3E所绘示的排列方式,而这些芯片封装体300a、 300b或300c也可以翻转180 度。 It is worth mentioning that these chip package 300a, 300b and 300c is not limited to the arrangement depicted in FIG. 3E, and these chip package 300a, 300b or 300c may be rotated 180 degrees. 以芯片封装体300b翻转180度而言,此时,芯片封装体300b与300c 的图案化线路层3M将面向彼此(类似图4B所示)。 In flip chip package 300b 180 degrees, the time, the chip package 300b and 300c of the patterned circuit layer 3M will face each other (similar to FIG. 4B). 然后,在共用承栽器22的焊球垫22b上形成多个焊球24,以完成堆叠型芯片封装结构20的制作.此堆叠型芯片封装结构20便可以藉由焊球24 配置于一电路板(图中未示)上。 Then, a plurality of solder balls 24 are formed on the common solder ball bearing pad 22b planted 22 to complete a stacked-type chip package structure 20 produced. This stacked chip package can 20 by solder balls 24 disposed on a circuit plate (not shown). 值得一提的是,本实施例并不限制堆叠型芯片封装结构20内的芯片封装体的排列方式与数量. It is worth mentioning that the present embodiment does not limit the arrangement of the chip package in the stacked package 20 and the chip number.

由于每一个芯片封装体300a、 300b与300c的芯片320系嵌入核心层312内,因此每一个芯片封装体300a、 300b与300c的厚度便可变薄,换言之,堆叠型芯片封装结构20的整体厚度也随着变薄。 Because each chip package 300a, 300b and 300c based chip 320 embedded in the core layer 312, so that each chip package 300a, 300b and 300c of the thickness can be thinned, in other words, the overall thickness of the stacked chip package structure 20 along with the thinning. 此外,由于每一个芯片封装体300a、 300b与300c均是单独制造而成,因此不良品的芯片封装体不会使用至堆叠型芯片封装结构20内,以提高堆叠型芯片封装结构20 的良率。 Further, since each of the chip package 300a, 300b and 300c are separately manufactured, and therefore defective chip package is not used until the stacked chip package 20, in order to improve the yield of stacked chip package structure 20 . 另外,每一个芯片封装体300a、 300b与300c的芯片320的背面均是棵露,因此堆叠型芯片封装结构20能够具有较佳的散热效率。 Further, each of the chip package 300a, 300b and 300c of the back surface of the chip 320 are exposed trees, so stacked die package 20 can have a better heat dissipation efficiency.

值得一提的是,在本实施例中,芯片封装体300a、 300b与300c均是覆晶接合封装体,但是也可以使用打线接合封装体,其详述如后。 It is worth mentioning that, in this embodiment, the chip package 300a, 300b and 300c are flip chip bonding packages, but wire bonding can also be used in the package of the present embodiment, as will be described in detail thereof.

【第二实施例1 [Second Embodiment Example 1

图4A至困4B是依照本发明第二实施例的堆叠型芯片封装结构的制造流程剖面示意图.请参阅图4A,本实施例与上述实施例相似,其不同之处在于:将芯片410置于第一贯孔310a内的后,形成多条导线420,以连接齒案化线路层314与芯片410之间。 4A-4B are trapped in accordance with the manufacturing process of the stacked chip packaging structure of the second embodiment of the present invention, please refer to FIG. 4A schematic cross-sectional view, similar to the embodiment of the present embodiment described above, except that it: the chip 410 is placed after the first through the hole 310a, to form a plurality of conductors 420, 410 to be connected between the teeth 314 and patterned circuit layer chip. 同样地,在第一贯孔312a内形成一封装胶体430,以将芯片410固着于封装基板310内,且封装胶体43G包覆芯片410、导线420与部分图案化线路层314。 Likewise, the first through hole formed in an encapsulant 312a 430, 410 fixed to the chip in the package substrate 310, and encapsulant 410 43G coated chip, the wire 420 and the portion of the patterned circuit layer 314. 至此,初步完成芯片封装体400a 的制作. At this point, the initial completion of the production of the chip package 400a.

值得一提的是,在本实施例中,封装胶体430突出于封装基板310,然而封M体430与封装基板310也可以是切齐.然后,将无铅焊料、锡铅焊料、其他类型的焊料或是其他导电材料填入这些第一贯孔312b内,以形成多个外部连接端子440。 It is worth mentioning that, in the present embodiment, the projection 430 on the package encapsulant substrate 310, however, M sealing substrate 310 and the package body 430 may be cut flush Then, the lead-free solder, tin-lead, other types of solder or other conductive material filled into the first through holes 312b, so as to form a plurality of external connection terminals 440. 然而,上述实施例中的导电柱350也可以取代本实施例的外部连接端子440, However, the above-described embodiment, the conductive pillar 350 may be substituted according to the present embodiment the external connection terminal 440 of the embodiment,

请参阅图4B所示,重复上述步骤,以形成芯片封装体的0b与400c。 Please refer to FIG 4B, the above steps are repeated to form a chip package and 0b 400c. 提供一共同承栽器32,而在本实施例中,共同承栽器32为导线架,但是共同承栽器32也可以是电路板(类似图3E所示)。 A plant to provide a common bearing 32, in the present embodiment, the common bearing plant is a lead frame 32, but a common bearing plant 32 may be a circuit board (similar to FIG. 3E). 将这些芯片封装体400a、 400h 与400c堆叠于共同承栽器32上,且这些芯片封装体400a、 400b与400c 藉由外部连接端子440彼此电性连接,此外,芯片封装体400c藉由外部连接端子440电性连接至共同承栽器32。 These chip package 400a, 400h and 400c are stacked together on planted bearing 32, and these chip package 400a, 400b in addition, the chip package 400c and 400c by the external connection terminal 440 by the external connection electrically connected to each other, terminal 440 is electrically connected to a common bearing 32 is planted. 同样地,此堆叠型芯片封装结构30 也可以藉由焊料(solder)或预焊料(pre-solder )配置于一电路板(图 Likewise, this type of stacked chip packaging structure 30 may be by solder (Solder) or pre-solder (pre-solder) is disposed on a circuit board (FIG.

中未示)上. On not shown).

值得一提的是,虽然芯片封装体400a与400b的困案化线路层是面向彼此,但本实施例并不限制堆叠型芯片封装结构30内的芯片封装体的排列方式与数量. 【第三实施例】 It is worth mentioning that, although the trapped case circuit layer 400a and 400b of the chip package are facing each other, but the present embodiment is not limited to the number of arrangement in the chip package stacked chip packaging structure 30. [Third EXAMPLES

请参阅图5所示,是依照本发明第三实施例的芯片封装结构的剖面示意图.本实施例与第一实施例相似,其不同之处在于:将芯片320的部分区域上或困案化线路层314上形成一粘着层510,并使得芯片320与图案化线路层314接合。 See FIG. 5 is a cross-sectional schematic diagram of a chip package structure of a third embodiment according to the present embodiment of the present invention similar to the embodiment and the first embodiment, except that it: the upper portion of the chip region 320 of the text or the storm a circuit layer 314 is formed on the adhesive layer 510, such that the chip 320 and the patterned circuit layer 314 bonded. 然后,进行一引脚压合制程,以使得闺案化线路层314 与凸块330接合,因此图案化线路层314能够经由凸块330与芯片320。 Then, a pin lamination process, so that the text Gui circuit layer 314 and the bump 330 engage, thus can be patterned circuit layer 314 and the bump 330 via chip 320. 更详细而言,引脚压合制程可以是用于贴带自动接合(Tape Automatic BQnding, TAB)的内引脚接合(inner lead bonding, ILB)制程。 More specifically, the pin pressing process may be used to stick tape automated bonding (Tape Automatic BQnding, TAB) in the engagement pin (inner lead bonding, ILB) process.

然后,在第一贯孔312a内形成一封装胶体340,以将芯片320固着于封装^feL 310内,且封装胶体340包覆芯片320、凸块330与部分图案化线4层314.至此,初步完成芯片封装体500a的制作。 Then, through holes are formed in the first encapsulant 312a a 340, 320 fixed to the chip within the package ^ feL 310, encapsulant 340 and the chip cover 320, bumps 330 and the pattern line portion 4 layer 314. At this point, preliminary to complete the production of the chip package 500a. 值得一提的是,在本实施例中,封装胶体340完全包覆芯片320,但是封装胶体340也可以暴^ 出芯片320的背面。 It is worth mentioning that, in this embodiment, encapsulant 340 completely coated chip 320 in the present embodiment, the encapsulant 340 may be violent ^ back surface of the chip 320. 再者,本实施例的芯片封装体500a也可以用于第一实施例或第二实施例的堆叠型芯片封装结构中,在此不再赘述。 Furthermore, the chip package 500a of the present embodiment may also be used in the first embodiment or stacked chip packaging structure of the second embodiment, which is not repeated herein.

综上所述,本发明至少具有下列优点: In summary, the present invention has at least the following advantages:

一、 由于本发明将芯片嵌入封装基板的核心层内,因此本发明的堆叠型芯片封装结构或是芯片封装体的厚度能够变薄。 First, since the present invention is a core layer embedded in a chip package substrate, so stacked or thickness of the chip package structure of a chip package according to the present invention can be thinned.

二、 本发明的堆叠型芯片封装结构或是芯片封装体能应用于覆晶接合鲥程或是打线接合制程. Second, the stacked chip package or a chip package according to the present invention is applied to the physical shad flip chip bonding process or a wire bonding process.

三、 相较于现有习知技术,本发明的堆叠型芯片封装结构或是芯片封装体具有较佳的散热效率。 Third, as compared to the conventional art, the stacked-type chip package or the chip package of the present invention has better heat dissipation efficiency.

虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当M权利要求所界定为准。 Although the invention has been described by reference to preferred embodiments, they are not intended to limit the present invention, any person skilled in this art, without departing from the spirit and scope of the present invention, may make various modifications and variations, so this the scope of the invention defined by the claims as M equivalents.

Claims (8)

  1. 1. 一种芯片封装体,其特征在于其包括:一封装基板,包括一核心层与配置在该核心层上的一图案化线路层,该核心层具有上表面与下表面,且该图案化线路层配置于该核心层的上表面,其中该核心层具有一第一贯孔与多个第二贯孔,且该第一贯孔与该些第二贯孔分别暴露出位于该核心层上表面的部分该图案化线路层;一芯片,配置在该第一贯孔内,并与该图案化线路层电性连接;一封装胶体,配置在该第一贯孔内,以将该芯片固着在该封装基板内,且该封装胶体暴露出该芯片的远离该图案化线路层的表面;以及多个外部连接端子,分别配置在该些第二贯孔内,且每一该些外部连接端子经由位于该核心层上表面的该图案化线路层而电性连接至该芯片。 A chip package, characterized in that it comprises: a package substrate including a core layer and a patterned circuit layer disposed on the core layer, the core layer having an upper surface and a lower surface, and the patterned wiring layer is disposed on the upper surface of the core layer, wherein the core layer having a first through hole and a plurality of second through holes, and the first through holes are located and exposing the plurality of second through holes of the core layer portion of the patterned circuit layer surface; a chip disposed in the first through hole, and electrically connected to the line of the patterned layer; an encapsulant, disposed in the first through hole, the chips are fixed to in the package substrate and the encapsulant to expose the surface of the chip away from the patterned circuit layer; and each of the plurality of external connection terminals connected to external terminals, respectively disposed in the plurality of second through hole, and through the patterned circuit layer located on the surface of the core layer is electrically connected to the chip.
  2. 2. 根据权利要求1所述的芯片封装体,其特征在于其更包括多个凸块, 配置在该芯片与该图案化线路层之间,而该芯片经由该些凸块电性连接至该困案化线路层,且该封装胶体包覆该些凸块。 The chip package according to claim 1, characterized in that it further comprises a plurality of bumps disposed between the chip and the patterned circuit layer, which is connected to the chip through the bumps electrically case trapped circuit layer and the encapsulant covering the bumps.
  3. 3. 根据权利要求1所述的芯片封装体,其特征在于其更包括多条导线, 其中该芯片经由该些导线电性连接至该图案化线路层,且该封装胶体包覆该些导线。 The chip package according to claim 1, characterized in that it further comprises a plurality of wires, wherein the chip is connected via the conductive lines electrically to the patterned circuit layer, and the encapsulant for encapsulating the wire.
  4. 4. 一种堆叠型芯片封装结构,其特征在于其包括: 一共同承栽器;多个芯片封装体,堆叠在该共同承栽器上,并与该共同承栽器电性连接,每一该些芯片封装体包括:一封装J4SL,包括一核心层与配置在该核心层上的一图案化线路层,该核心层具有上表面与下表面,且该图案化线路层配置于该核心层的上表面, 其中该核心层具有一第一贯孔与多个第二贯孔,且该第一贯孔与该些第二贯孔分别暴露出位于该核心层上表面的部分该图案化线路层;一芯片,配里在该第一贯孔内,并与该图案化线路层电性连接;一封装胶体,配置在该第一贯孔内,以将该芯片固着在该封装基板内, 且该封装胶体暴露出该芯片的远离该困案化线路层的表面;以及多个外部连接端子,分别配置在该些第二贯孔内,而每一该些外部连接端子经由位于该核心层上产面的该图案化线 A stacked chip package structure, characterized in that it comprises: a common bearing plant; a plurality of chip packages, stacked on the common bearing plant, and connected to the common supporting plant is electrically, each the plurality of chip package comprising: a package J4SL, comprising a core layer and disposed a patterned wiring layer on the core layer, the core layer having an upper surface and a lower surface, and the patterned circuit layer disposed on the core layer the upper surface, wherein the core layer having a first through hole and a plurality of second through holes, and the first through hole and the plurality of second through holes are positioned on the core layer to expose portions of the surface of the patterned circuit layer; a chip, with the first hole in a consistent and electrically connected to the line of the patterned layer; an encapsulant, disposed in the first through hole, fixed to the chip in the package substrate, the encapsulant and expose the surface of the chip away from the trapped patterned circuit layer; and a plurality of external connection terminals are disposed in the plurality of second through hole, and each of the external connection terminal via the core layer is located producing on the surface of the pattern line 路层电性连接至该,片,,,另一该些芯片封装体。 Layer is electrically connected to the passage, the plurality of sheet ,,, another chip package.
  5. 5.,权利要求4所述的堆叠型芯片封装结构,其特征在于其中所述的共同承栽器包括电路板或导线架。 5, the stacked type chip package structure according to claim 4, characterized in that the common bearing device wherein the plant comprises a circuit board or lead frame.
  6. 6.—种芯片封装体的制造方法,其特征在于其包括:提供一芯片与一封装基板,其中该封装基板包括一核心层与配置在该核心层上的一图案化线路层,该核心层具有上表面与下表面,且该图案化线路层配置于该核心层的上表面,而在该核心层内已形成一第一贯孔与多个第二贯孔,且该第一贯孔与该些第二贯孔分别暴露出位于该核心层上表面的部分该图案化线路层;将该芯片配置在该第一贯孔内,以使该芯片与该图案化线路层电性连在该笫一贯孔内形成一封装胶体,以将该芯片固着在该封装基板内,且该封装胶体暴露出该芯片的远离该困案化线路层的表面;以及在该些第二贯孔内形成多个外部连接端子,且每一该些外部连接端子经由位于该核心层上表面的该图案化线路层电性连接至该芯片。 6.- The method of manufacturing a chip package types, characterized in that it comprises: providing a chip and a package substrate, wherein the package substrate includes a core layer and a patterned circuit layer disposed on the core layer, the core layer having upper and lower surfaces, and the patterned circuit layer disposed on a surface of the core layer, and a first through hole and a plurality of second through holes formed in the core layer, and the first through hole and the plurality of second through holes which expose a portion positioned on the patterned circuit layer surface of the core layer; the chip configuration of the usual hole, so that the chip and the patterned layer is electrically connected in the circuit Zi always encapsulant forming a hole, fixed to the chip in the package substrate and the encapsulant to expose the surface of the chip away from the trapped patterned circuit layer; and forming a plurality of second through-hole in the plurality of external connection terminals and each of the external connection terminal is connected to the chip through the electrical circuit patterned layer located on the surface of the core layer.
  7. 7. 根据权利要求6所述的芯片封装体的制造方法,其特征在于其更包括在该芯片与该图案化线路层之间形成多个凸块,且该芯片经由该些凸块电性连接至该困案化线路层。 7. A method of manufacturing a chip package according to claim 6, characterized in that it further comprises forming a plurality of bumps between the chip and the patterned circuit layer, and the chip through the bumps electrically connected stuck to the patterned wiring layer.
  8. 8. 根据权利要求6所述的芯片封装体的制造方法,其特征在于其更包括形成多条导线,且该些导线连接该芯片与该图案化线路层之间。 8. A method of manufacturing a chip package according to claim 6, characterized in further comprising a plurality of wires formed thereon, and the plurality of lead connection between the chip and the patterned circuit layer.
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