CN100481420C - Stack type chip packaging structure, chip packaging body and manufacturing method thereof - Google Patents
Stack type chip packaging structure, chip packaging body and manufacturing method thereof Download PDFInfo
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- CN100481420C CN100481420C CN 200510102505 CN200510102505A CN100481420C CN 100481420 C CN100481420 C CN 100481420C CN 200510102505 CN200510102505 CN 200510102505 CN 200510102505 A CN200510102505 A CN 200510102505A CN 100481420 C CN100481420 C CN 100481420C
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- 238000004806 packaging method and process Methods 0.000 title claims description 95
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims abstract description 74
- 239000012792 core layer Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000084 colloidal system Substances 0.000 claims description 37
- 238000012856 packing Methods 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000007789 sealing Methods 0.000 abstract 6
- 239000003292 glue Substances 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 17
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
This invention relates to overlap chip sealing structure and its process method, wherein, the structure comprises one sealing baseboard, one chip and one sealing glue; sealing baseboard comprises one core layer and one pattern circuit layer; the core layer has one first hole and several holes exposing partly pattern; the chip is set into first hole connected to pattern circuit; sealing glue is set into first hole to fix into sealing baseboard.
Description
Technical field
The invention relates to a kind of encapsulating structure, and particularly relevant for a kind of stack chip packaging structure with high encapsulation integration.
Background technology
In information society now, the user pursues electronic product high-speed, high-quality, multiplex's energy property.With regard to product appearance, the design of electronic product also strides forward towards light, thin, short, little trend.In order to achieve the above object, many companies all incorporate systematized notion when carrying out circuit design, make single chips to possess to have multiple function, are configured in core number in the electronic product with saving.In addition, with regard to the Electronic Packaging technology, in order to cooperate light, thin, short, little designer trends, also develop and multi-chip modules (multi-chip module, MCM) package design notion, chip size structure dress (chip scale package, the notion of package design notion CSP) and stacked multicore sheet package design etc.Below just describe at several existing known stack chip packaging structures respectively.
Seeing also shown in Figure 1ly, is the generalized section of existing known stack chip packaging structure.Existing known stack chip packaging structure 100 comprises a base plate for packaging (package substrate) 110, chip 120a, 120b, a sept (spacer) 130, many leads 140 and a packing colloid (encapsulant) 150.Wherein, chip 120a and 120b are disposed on the base plate for packaging 110, and sept 130 is disposed between chip 120a and the 120b.Part lead 140 is electrically connected at respectively between chip 120a and the base plate for packaging 110, and other part leads 140 then are electrically connected at respectively between chip 120b and the base plate for packaging 110.In addition, packing colloid 150 is disposed on the base plate for packaging 110, and coats these leads 140, chip 120a and 120b.
Because must be between chip 120a and the 120b at a distance of certain distance, so that carry out routing processing procedure (wire bonding process), the integral thickness of therefore existing known stack chip packaging structure 100 can can't further reduce because of the thickness of sept 130.In addition, existing known stack chip packaging structure 100 also can produce the problem of heat radiation aspect.Therefore, in order to address the above problem, to develop and another kind of stack chip packaging structure.
Seeing also shown in Figure 2ly, is generalized section of another existing known stack chip packaging structure.Existing known stack chip packaging structure 10 comprises a base plate for packaging 12 and a plurality of chip packing- body 200a, 200b, and wherein these chip packing- bodies 200a, 200b are stacked on the base plate for packaging 12, and electrically connects with base plate for packaging 12.Each chip packing- body 200a, 200b comprise a base plate for packaging 210, a chip 220, a plurality of projection 230, a primer 240 and a plurality of soldered balls 250.Chip 220 is disposed on the base plate for packaging 210 with these projections 230, and these projections 230 are disposed between chip 220 and the base plate for packaging 210, and chip 220 is electrically connected to base plate for packaging 210 via these projections.Primer 240 is disposed between chip 220 and the base plate for packaging 210, to coat these projections 230.
Base plate for packaging 210 has a plurality of conductive poles 212 and a plurality of solder ball pads 214, and wherein these conductive poles 212 run through base plate for packaging 210 respectively, and these solder ball pads 214 are disposed at respectively on these conductive poles 212.In addition, these soldered balls 250 are disposed on these solder ball pads 214.It should be noted that chip packing- body 200a and 200b are electrically connected to each other via soldered ball 250, and chip packing-body 200b is electrically connected to base plate for packaging 12 via soldered ball 250.
Compared to existing known stack chip packaging structure 100, though existing known stack chip packaging structure 10 process complexity of this kind are lower, the thickness that this kind has known stack chip packaging structure 10 now is greater than the thickness that has known stack chip packaging structure 100 now.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of chip packing-body, the thinner thickness that it is whole exactly.
In addition, a further object of the present invention just provides a kind of stack chip packaging structure, and it has higher encapsulation integration.
In addition, another purpose of the present invention just provides a kind of manufacture method of chip packing-body, to produce the embedded chip packaging body.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of chip packing-body, and it comprises a base plate for packaging, a chip and a packing colloid.Wherein, base plate for packaging comprises a core layer (core layer) and a patterned line layer that is disposed on the core layer.Core layer has upper surface and lower surface, and patterned line layer is disposed at the upper surface of core layer, core layer has one first perforation and a plurality of second perforation, and wherein first perforation and these second perforations expose the partially patterned line layer that is positioned at the core layer upper surface respectively.Chip configuration and electrically connects with patterned line layer in first perforation.Packing colloid is disposed in first perforation, and so that chip is bonded in the base plate for packaging, and packing colloid exposes the surface away from patterned line layer of chip.External connection terminals is configured in respectively in second perforation, and each external connection terminals is electrically connected to chip via the patterned line layer that is positioned at the core layer upper surface.
According to the embodiment of the invention, chip packing-body more can comprise a plurality of projections, and it is disposed between chip and the patterned line layer, and chip is electrically connected to patterned line layer via these projections, and packing colloid coats these projections.In addition, packing colloid can be the surface away from patterned line layer that exposes chip.
According to the embodiment of the invention, chip packing-body more can comprise many leads, and its chips is electrically connected to patterned line layer via these leads, and packing colloid coats these leads.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of stack chip packaging structure, and it comprises a common carrier and an a plurality of chip packing-body, and wherein these chip packing-bodies are stacked on the common carrier, and electrically connects with common carrier.Each chip packing-body comprises a base plate for packaging, a chip and a packing colloid.Wherein, base plate for packaging comprises a core layer and a patterned line layer that is disposed on the core layer.Core layer has upper surface and lower surface, and patterned line layer is disposed at the upper surface of core layer.Core layer has one first perforation and a plurality of second perforation, and wherein first perforation and these second perforations expose the partially patterned line layer that is positioned at the core layer upper surface respectively.Chip configuration and electrically connects with patterned line layer in first perforation.Packing colloid is disposed in first perforation, and so that chip is bonded in the base plate for packaging, and packing colloid exposes the surface away from patterned line layer of chip.These external connection terminals are disposed at respectively in these second perforations, and each external connection terminals is electrically connected to chip via the patterned line layer that is positioned at the core layer upper surface.Each chip packing-body is electrically connected to common carrier or another chip packing-body via these external connection terminals of correspondence.
According to the embodiment of the invention, common carrier can be circuit board or lead frame.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of manufacture method of chip packing-body, and it comprises the following steps.At first, one chip and a base plate for packaging are provided, wherein base plate for packaging comprises a core layer and a patterned line layer that is disposed on the core layer, core layer has upper surface and lower surface, and patterned line layer is disposed at the upper surface of core layer, and formed one first perforation and a plurality of second perforation in core layer, and first perforation and these second perforations expose the partially patterned line layer that is positioned at the core layer upper surface respectively.With chip configuration in first perforation, so that chip and patterned line layer electrically connect.Form a packing colloid in first perforation, so that chip is bonded in the base plate for packaging, and packing colloid exposes the surface away from patterned line layer of chip.In second perforation, form a plurality of external connection terminals, and each external connection terminals is electrically connected to chip via the patterned line layer that is positioned at the core layer upper surface.
According to the embodiment of the invention, the manufacture method of chip packing-body more can form a plurality of projections between chip and patterned line layer, and chip is electrically connected to patterned line layer via these projections.
According to the embodiment of the invention, the manufacture method of chip packing-body more can form many leads, and between these conductor connecting core sheets and the patterned line layer.
Based on above-mentioned, the present invention embeds chip in the core layer of base plate for packaging, but therefore formed stack chip packaging structure or all attenuation of the thickness of chip packing-body.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the generalized section of existing known stack chip packaging structure.
Fig. 2 is the generalized section of another existing known stack chip packaging structure.
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section according to the stack chip packaging structure of first embodiment of the invention.
Fig. 4 A to Fig. 4 B is the manufacturing process generalized section according to the stack chip packaging structure of second embodiment of the invention.
Fig. 5 is the generalized section according to the chip-packaging structure of third embodiment of the invention.
10,100: existing known stack chip packaging structure
12,110,210,310: base plate for packaging
20,30: stack chip packaging structure
22,32: shared carrier
22a, 22b, 214,360: solder ball pad
24,250,370: soldered ball
120a, 120b, 220,320,410: chip
130: sept
140,420: lead
150,340,430: packing colloid
200a, 200b, 300a, 300b, 300c, 400a, 400b, 400c, 500a: chip packing-body
212,350: conductive pole
230,330: projection
240: primer
312: core layer
312a: first perforation
312b: second perforation
314: patterned line layer
316: welding cover layer
440: external connection terminals
510: adhesion coating
Embodiment
[first embodiment]
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section according to the stack chip packaging structure of first embodiment of the invention.See also Fig. 3 A, the manufacture method of the stack chip packaging structure of present embodiment comprises the following steps.At first, provide a base plate for packaging 310, and base plate for packaging 310 can be circuit board or flexible circuit board.In addition, base plate for packaging 310 comprises a core layer 312 and a patterned line layer 314 that is disposed on the core layer 312, wherein core layer 312 can be bismaleimide-triazine (Bismaleimide-Triazine,
BT) material, dielectric material or other thin-film materials.In addition, base plate for packaging 310 also can comprise a welding cover layer 316, and welding cover layer 316 is disposed on the core layer 312, and cover part patterned line layer 314.
Then, in core layer 312, form one first perforation 312a and a plurality of second perforation 312b, and the first perforation 312a and these second perforations 312b expose partially patterned line layer 314 respectively.In addition, the method that forms the first perforation 312a and the second perforation 312b can be Laser drill, machine drilling or other can form the processing procedure of perforation.
See also shown in Fig. 3 B, a chip 320 is provided, and chip 320 is disposed in the first perforation 312a.Then, chip 320 and patterned line layer 314 are electrically connected, its chips 320 can be the chip bonding technology with the mode that patterned line layer 314 electrically connects.With regard to the chip bonding technology, chip 320 is to electrically connect by projection 330 and patterned line layer 314. in the present embodiment, projection 330 can be formed on the patterned line layer 314 or be formed on the chip 320, and then process reflow (reflow) is so that chip 320 can electrically connect by projection 330 and patterned line layer 314.
See also shown in Fig. 3 C, in the first perforation 312a, form a packing colloid 340, so that chip 320 is bonded in the base plate for packaging 310.In one embodiment of this invention, packing colloid 340 is to coat projection 330 and partially patterned line layer 314.So far, tentatively finish the making of chip packing-body 300a.What deserves to be mentioned is that the packing colloid 340 of present embodiment can expose the surface away from patterned line layer 314 of chip 320, to improve the radiating efficiency of chip 320.In other words, packing colloid 340 exposes the back side of chip 320, yet packing colloid 340 also can be complete coating chip 320.In addition, packing colloid 340 also can be to trim with base plate for packaging 310, yet packing colloid 340 also can be to protrude in base plate for packaging 310.
See also shown in Fig. 3 D, form a plurality of conductive poles 350 in these second perforations 312b, with the usefulness as external connection terminals, and each conductive pole 350 is electrically connected to chip 320 via patterned line layer 314.More specifically, the mode that forms these conductive poles 350 can be the electroless-plating processing procedure also, the long-pending processing procedure of electric electroplating process or other metal Shen arranged.Yet, also can be that scolder or other conductive material of lead-free solder, tin-lead solder, other types are inserted in these second perforations 312b, to form external connection terminals (shown in Fig. 4 A).As with regard to the external connection terminals, on these conductive poles 350, form a plurality of solder ball pads 360 with regard to conductive pole 350.Then, on these solder ball pads 360, form a plurality of soldered balls 370, and these soldered balls 370 can be lead-free solder ball or tin lead welding ball.So far, roughly finish the making of chip packing-body 300a.
See also shown in Fig. 3 E, repeat above-mentioned step, to produce chip packing-body 300b and 300c.Then, provide a shared carrier 22, and shared carrier 22 have a plurality of solder ball pad 22a and 22b.In the present embodiment, shared carrier 22 is a circuit board, but shared carrier 22 also can be a lead frame.Then, chip packing- body 300a, 300b and 300c are stacked on the shared carrier 22, wherein the soldered ball 370 of these chip packing- bodies 300a, 300b and 300c contacts with corresponding solder ball pad 360.In addition, the soldered ball 370 of chip packing-body 300c contacts with the solder ball pad 22a of shared carrier 22.Then, carry out back welding process (reflow process),, and make chip packing-body 300c be connected with shared carrier 22 so that these chip packing- bodies 300a, 300b and 300c are electrical each other for said structure.
What deserves to be mentioned is that these chip packing- bodies 300a, 300b and 300c do not limit the arrangement mode that Fig. 3 E is illustrated, and these chip packing- bodies 300a, 300b or 300c also can turn over turnback.300b turns over turnback with chip packing-body, and at this moment, the patterned line layer 314 of chip packing- body 300b and 300c will be towards (shown in similar Fig. 4 B) each other.
Then, on the solder ball pad 22b of shared carrier 22, form a plurality of soldered balls 24, to finish the making of stack chip packaging structure 20.This stack chip packaging structure 20 just can be disposed on the circuit board (not shown) by soldered ball 24.What deserves to be mentioned is that present embodiment does not limit the arrangement mode and the quantity of the chip packing-body in the stack chip packaging structure 20.
Because the chip 320 of each chip packing- body 300a, 300b and 300c is to embed in the core layer 312, but so just attenuation of thickness of each chip packing- body 300a, 300b and 300c.In other words, the integral thickness of stack chip packaging structure 20 is also along with attenuation.In addition, because each chip packing- body 300a, 300b and 300c make separately to form, so the chip packing-body of defective products can not use to stack chip packaging structure 20, with the yield of raising stack chip packaging structure 20.In addition, the back side of the chip 320 of each chip packing- body 300a, 300b and 300c all is exposed, so stack chip packaging structure 20 can have preferable radiating efficiency.
What deserves to be mentioned is that in the present embodiment, chip packing- body 300a, 300b and 300c all are chip bonding packaging bodies, but also can use the routing bonding packaging body, its describe in detail as after.
[second embodiment]
Fig. 4 A to Fig. 4 B is the manufacturing process generalized section according to the stack chip packaging structure of second embodiment of the invention.See also Fig. 4 A, present embodiment is similar to the aforementioned embodiment, and its difference is: with chip 410 place in the first perforation 310a after, form many leads 420, to connect between patterned line layer 314 and the chip 410.Similarly, in the first perforation 312a, form a packing colloid 430, so that chip 410 is bonded in the base plate for packaging 310, and packing colloid 430 coating chips 410, lead 420 and partially patterned line layer 314.So far, tentatively finish the making of chip packing-body 400a.
What deserves to be mentioned is that in the present embodiment, packing colloid 430 protrudes in base plate for packaging 310, yet packing colloid 430 also can be to trim with base plate for packaging 310.Then, scolder or other electric conducting materials of lead-free solder, tin-lead solder, other types are inserted in these first perforations 312b, to form a plurality of external connection terminals 440.Yet the conductive pole 350 in the foregoing description also can replace the external connection terminals 440 of present embodiment.
See also shown in Fig. 4 B, repeat above-mentioned steps, to form chip packing-body 400b and 400c.Provide a common carrier 32, and in the present embodiment, common carrier 32 is a lead frame, but common carrier 32 also can be circuit board (shown in similar Fig. 3 E).These chip packing- bodies 400a, 400b and 400c are stacked on the common carrier 32, and these chip packing- bodies 400a, 400b and 400c are electrically connected to each other by external connection terminals 440.In addition, chip packing-body 400c is electrically connected to common carrier 32 by external connection terminals 440.Similarly, this stack chip packaging structure 30 also can be disposed on the circuit board (not shown) by scolder (solder) or pre-welding material (pre-solder).
What deserves to be mentioned is that though the patterned line layer 314 of chip packing- body 400a and 400b is towards each other, present embodiment does not limit the arrangement mode and the quantity of the chip packing-body in the stack chip packaging structure 30.
[the 3rd embodiment]
Seeing also shown in Figure 5ly, is the generalized section according to the chip-packaging structure of third embodiment of the invention.Present embodiment is similar to first embodiment, and its difference is: will form an adhesion coating 510 on the subregion of chip 320 or on the patterned line layer 314, and make chip 320 engage with patterned line layer 314.Then, carry out a pin pressure programming, so that patterned line layer 314 engages with projection 330, so patterned line layer 314 can be via projection 330 and chip 320.More specifically, the pin pressure programming can be to be used for pasting band to engage (Tape AutomaticBonding, TAB) interior pin joint (inner lead bonding, ILB) processing procedure automatically.
Then, in the first perforation 312a, form a packing colloid 340, so that chip 320 is bonded in the base plate for packaging 310, and packing colloid 340 coating chips 320, projection 330 and partially patterned line layer 314.So far, tentatively finish the making of chip packing-body 500a.What deserves to be mentioned is, in the present embodiment, packing colloid 340 complete coating chips 320, but packing colloid 340 also can expose the back side of chip 320.Moreover the chip packing-body 500a of present embodiment also can be used for the stack chip packaging structure of first embodiment or second embodiment, does not repeat them here.
In sum, the present invention has following advantage at least:
One, because the present invention embeds chip in the core layer of base plate for packaging, therefore the stack chip packaging structure of the present invention or the thickness of chip packing-body can attenuation.
Two, the stack chip packaging structure of the present invention or Chip Packaging physical efficiency is applied to chip bonding processing procedure or line connection process.
Three, compared to existing known techniques, stack chip packaging structure of the present invention or chip packing-body have preferable radiating efficiency.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention claim after looking defines and is as the criterion.
Claims (8)
1. chip packing-body is characterized in that it comprises:
One base plate for packaging, comprise a core layer and a patterned line layer that is configured on this core layer, this core layer has upper surface and lower surface, and this patterned line layer is disposed at the upper surface of this core layer, wherein this core layer has one first perforation and a plurality of second perforation, and this first perforation and those second perforations expose this patterned line layer of part that is positioned at this core layer upper surface respectively;
One chip is configured in this first perforation, and electrically connects with this patterned line layer;
One packing colloid is configured in this first perforation, and so that this chip is anchored in this base plate for packaging, and this packing colloid exposes the surface away from this patterned line layer of this chip; And
A plurality of external connection terminals are configured in respectively in those second perforations, and each those external connection terminals is electrically connected to this chip via this patterned line layer that is positioned at this core layer upper surface.
2. chip packing-body according to claim 1, it is characterized in that it more comprises a plurality of projections, be configured between this chip and this patterned line layer, and this chip is electrically connected to this patterned line layer via those projections, and this packing colloid coats those projections.
3. chip packing-body according to claim 1 is characterized in that it more comprises many leads, and wherein this chip is electrically connected to this patterned line layer via those leads, and this packing colloid coats those leads.
4. stack chip packaging structure is characterized in that it comprises:
One common carrier;
A plurality of chip packing-bodies are stacked on this common carrier, and electrically connect with this common carrier, and each those chip packing-body comprises:
One base plate for packaging, comprise a core layer and a patterned line layer that is configured on this core layer, this core layer has upper surface and lower surface, and this patterned line layer is disposed at the upper surface of this core layer, wherein this core layer has one first perforation and a plurality of second perforation, and this first perforation and those second perforations expose this patterned line layer of part that is positioned at this core layer upper surface respectively;
One chip is configured in this first perforation, and electrically connects with this patterned line layer;
One packing colloid is configured in this first perforation, and so that this chip is anchored in this base plate for packaging, and this packing colloid exposes the surface away from this patterned line layer of this chip; And
A plurality of external connection terminals, be configured in respectively in those second perforations, and each those external connection terminals is electrically connected to this chip via this patterned line layer that is positioned at this core layer upper surface, and each those chip packing-body is electrically connected to this common carrier or another those chip packing-bodies via those external connection terminals of correspondence.
5. stack chip packaging structure according to claim 4 is characterized in that wherein said common carrier comprises circuit board or lead frame.
6. the manufacture method of a chip packing-body is characterized in that it comprises:
One chip and a base plate for packaging are provided, wherein this base plate for packaging comprises a core layer and a patterned line layer that is configured on this core layer, this core layer has upper surface and lower surface, and this patterned line layer is disposed at the upper surface of this core layer, and formed one first perforation and a plurality of second perforation in this core layer, and this first perforation and those second perforations expose this patterned line layer of part that is positioned at this core layer upper surface respectively;
With this chip configuration in this first perforation, so that this chip and this patterned line layer electrically connect;
Form a packing colloid in this first perforation, so that this chip is anchored in this base plate for packaging, and this packing colloid exposes the surface away from this patterned line layer of this chip; And
In those second perforations, form a plurality of external connection terminals, and each those external connection terminals is electrically connected to this chip via this patterned line layer that is positioned at this core layer upper surface.
7. the manufacture method of chip packing-body according to claim 6 it is characterized in that it more is included in a plurality of projections of formation between this chip and this patterned line layer, and this chip is electrically connected to this patterned line layer via those projections.
8. the manufacture method of chip packing-body according to claim 6 it is characterized in that it more comprises many leads of formation, and those leads connects between this chip and this patterned line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510102505 CN100481420C (en) | 2005-09-08 | 2005-09-08 | Stack type chip packaging structure, chip packaging body and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510102505 CN100481420C (en) | 2005-09-08 | 2005-09-08 | Stack type chip packaging structure, chip packaging body and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1929120A CN1929120A (en) | 2007-03-14 |
| CN100481420C true CN100481420C (en) | 2009-04-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510102505 Active CN100481420C (en) | 2005-09-08 | 2005-09-08 | Stack type chip packaging structure, chip packaging body and manufacturing method thereof |
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| Country | Link |
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| CN (1) | CN100481420C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100885924B1 (en) | 2007-08-10 | 2009-02-26 | 삼성전자주식회사 | A semiconductor package having a buried conductive post in sealing resin and manufacturing method thereof |
| TWI419270B (en) * | 2011-03-24 | 2013-12-11 | Chipmos Technologies Inc | Package on package structure |
| CN102496581A (en) * | 2011-12-22 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacturing method for semiconductor packaging substrate of semiconductor packaging structure |
| CN103531549A (en) * | 2013-10-24 | 2014-01-22 | 桂林微网半导体有限责任公司 | Semiconductor chip packaging structure and packaging method |
| TWI550805B (en) * | 2015-04-20 | 2016-09-21 | 南茂科技股份有限公司 | Multi-chip stack package structure |
| CN113488454B (en) * | 2020-11-05 | 2022-06-03 | 浙江荷清柔性电子技术有限公司 | Packaging structure and packaging method |
-
2005
- 2005-09-08 CN CN 200510102505 patent/CN100481420C/en active Active
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| Publication number | Publication date |
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| CN1929120A (en) | 2007-03-14 |
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