TWI550805B - Multi-chip stack package structure - Google Patents

Description

Wafer stack package structure

The present invention relates to a package structure, and in particular to a knot A wafer stacked package structure with flip chip and wire bonding.

In the current chip packaging process, usually through wire bonding (wire Bonding or flip chip bonding or the like electrically connects the wafer to the line carrier. In the case of wire bonding, it is connected to the wafer bonding region of the wiring carrier with respect to the back surface of the active surface of the wafer, and is electrically connected to the pads on the active surface and the contacts on the wiring carrier through the metal wires. In addition, in the case of flip chip bonding, solder bumps are formed on the pads on the active surface of the wafer, and then the wafer is oriented with its active surface toward the wafer bonding region of the wiring carrier, and the solder bump is formed. The block is aligned with the contacts on the line carrier. Thereafter, the solder bumps are electrically soldered to electrically connect the pads on the active surface to the contacts on the line carrier.

Furthermore, by wire bonding to electrically connect the wafer to the line carrier, The contacts on the line carrier can only be placed around the wafer bonding area. Moreover, by simply flip-chip bonding to electrically connect the wafer to the line carrier, the contacts on the line carrier can only be set. Placed in the wafer bonding area. However, in today's electronics industry, for maximum electrical efficiency, low cost and high integration of integrated circuits, fine pitch, etc., wire bonding or flip chip bonding is used to electrically connect wafers and wires. The packaging process and package structure of the carrier board cannot fully meet the requirements of the current electronics industry.

The present invention provides a wafer stack package structure that meets the design requirements of high integration and fine pitch.

The present invention provides a wafer stack package structure including a line carrier, a first wafer, a plurality of solder balls, a second wafer, and a plurality of bonding wires. The line carrier has a plurality of first pads and a plurality of second pads surrounding the first pads. The first wafer is disposed on the line carrier. The first wafer has a first active surface, a first back surface opposite the first active surface, and a plurality of first conductive pillars on the first active surface. The solder balls are electrically connected to the first conductive pillars and the first pads, respectively. The second wafer has a second active surface, a second back surface opposite to the second active surface, and a plurality of second conductive pillars on the second active surface, wherein the second wafer is disposed on the first wafer, and the second back surface is The first back faces are opposite each other. The bonding wires are electrically connected to the second conductive pillars and the second pads, respectively.

In an embodiment of the invention, the material of the bonding wire comprises copper, gold, silver or an alloy of the above metals.

In an embodiment of the invention, the material of the first conductive pillar and the second conductive pillar is selected from the group consisting of copper, gold, silver or an alloy of the above metals. One of the materials.

In an embodiment of the invention, each of the second conductive pillars has a metal layer. Each of the metal layers is located at an end of the corresponding second conductive post that is relatively far from the second active surface.

In an embodiment of the invention, the material of the metal layer comprises aluminum.

In an embodiment of the invention, the first pad is located within an orthographic projection of the first wafer on the line carrier.

In an embodiment of the invention, the second pad is located outside the orthographic projection of the first wafer on the line carrier.

In an embodiment of the invention, the wafer stack package structure further includes an adhesive layer. The adhesive layer connects the first back side of the first wafer and the second back side of the second wafer.

In an embodiment of the present invention, the wafer stack package structure further includes an encapsulant covering the second pads, the first wafer, the second wafer, the second conductive pillars, and the bonding wires, and filling in the first An active surface is interposed between the line carrier and the line carrier to encapsulate the first conductive posts, the solder balls, and the first pads.

In an embodiment of the invention, the surface area of the first back surface is greater than or equal to the surface area of the second back surface.

Based on the above, the wafer stack package structure of the present invention may include a first wafer and a second wafer stacked on each other, wherein the first wafer may be electrically bonded to the first pad in a manner of flip chip bonding, and the second The wafer can be wire bonded to electrically connect the second conductive post to the second pad, so that the wiring area is limited On the carrier board, the number of high feet can also be obtained to meet the design requirements of high integration and micro-pitch.

The above described features and advantages of the invention will be apparent from the following description.

100, 100A‧‧‧ wafer stacking structure

110‧‧‧Line carrier

111‧‧‧Substrate

111a‧‧‧ surface

112‧‧‧First mat

113‧‧‧second mat

120‧‧‧First chip

121‧‧‧First active surface

122‧‧‧ first back

123‧‧‧First conductive column

130‧‧‧ solder balls

140‧‧‧second chip

141‧‧‧Second active surface

142‧‧‧ second back

143‧‧‧Second conductive column

143a‧‧‧End

144‧‧‧metal layer

150‧‧‧welding line

160‧‧‧Adhesive layer

170‧‧‧Package colloid

1 is a top plan view of a wafer stack package structure in accordance with an embodiment of the present invention.

2 is a cross-sectional view of the wafer stack package structure of FIG. 1 taken along line A-A.

3 is a cross-sectional view showing a wafer stack package structure according to another embodiment of the present invention.

1 is a top plan view of a wafer stack package structure in accordance with an embodiment of the present invention. 2 is a cross-sectional view of the wafer stack package structure of FIG. 1 taken along line A-A. For clarity and convenience of description, FIG. 1 omits the encapsulant 170. Referring to FIG. 1 and FIG. 2 , in the embodiment, the wafer stack package structure 100 includes a circuit carrier 110 , a first wafer 120 , a plurality of solder balls 130 , a second wafer 140 , and a plurality of bonding wires 150 . The material of the substrate 111 of the board 110 is, for example, a material generally used for a substrate of a printed circuit board, and is, for example, a FR4, FR5 or BT material. However, the material of the substrate 111 of the line carrier 110 is not limited to the above-mentioned materials such as FR4, FR5 or BT, and the substrate 111 of the line carrier 110 may also be made of polyimide, PI or polyethylene. Phthalate (PET), polyether (PES), carbonate (PC) or other suitable Made of flexible material. On the other hand, a plurality of first pads 112 and a plurality of second pads 113 surrounding the first pads 112 are formed on the surface 111a of the substrate 111. Generally, the material of the first pad 112 and the second pad 113 may include copper, gold, silver, aluminum or an alloy of the above metals.

The first wafer 120 is disposed on the line carrier 110, wherein the first wafer 120 has a first active surface 121, a first back surface 122 opposite to the first active surface 121, and a plurality of first conductive layers on the first active surface 121. Column 123. As shown in FIG. 2, the first wafer 120 is disposed on the line carrier 110 with its first active surface 121 facing the surface 111a of the substrate 111. In detail, the number of the first conductive pillars 123 may correspond to the number of the first pads 112, and after the first wafer 120 is disposed on the line carrier 110, the first conductive pillars 123 may correspond to the first The pads 112 are relatively aligned. On the other hand, before the first wafer 110 is placed on the line carrier 110, the solder balls 130 are first formed on the end portions 123a of the respective first conductive pillars 123 away from the first active surface 121. Therefore, after the first wafer 110 is disposed on the line carrier 110, each of the first conductive pillars 123 can be abutted against the corresponding first pads 112 through the corresponding solder balls 130, and processed by reflow processing. The first conductive pillar 123 is electrically connected to the corresponding first pad 112 through the corresponding solder ball 130 . In other words, the first wafer 120 is electrically connected to the line carrier 110 by, for example, flip chip bonding.

The second wafer 140 has a second active surface 141, a second back surface 142 opposite to the second active surface 141, and a plurality of second conductive pillars 143 on the second active surface 141, wherein the second wafer 140 is, for example, The second back surface 142 is disposed on the first wafer 120 toward the first back surface 122 of the first wafer 120 such that the second back The face 142 and the first back face 122 are opposed to each other. In this embodiment, the wafer stack package structure 100 further includes an adhesive layer 160, such as an adhesive layer such as an insulating layer, an insulating film or an insulating heat sink. After the second wafer 140 is stacked on the first wafer 120, the first back surface 122 of the first wafer 120 and the second back surface 142 of the second wafer 140 are connected by the adhesive layer 160 to transfer the second wafer. The adhesive is attached to the first wafer 110. In the present embodiment, the size of the first wafer 120 is substantially the same as the size of the second wafer 140, and thus the surface area of the first back surface 122 of the first wafer 120 is, for example, equal to the surface area of the second back surface 142 of the second wafer 140. However, the invention is not limited thereto. In other embodiments, the size of the first wafer 120 may also be larger than the size of the second wafer 140. The surface area of the first back surface 122 of the first wafer 120 is greater than the surface area of the second back surface 142 of the second wafer 140, for example. .

As shown in FIG. 1 and FIG. 2, the number of the first conductive pillars 123 on the first wafer 120 of the present embodiment is, for example, the same as the number of the second conductive pillars 143 on the second wafer 140, but the first conductive pillar 123 The positional distribution on the active surface 121 differs from the positional distribution of the second conductive post 143 on the active surface 121. In other words, after the second wafer 140 is stacked on the first wafer 120, the first conductive pillars 123 and the second conductive pillars 143 are asymmetrically disposed on opposite sides of the adhesive layer 160, for example. In another embodiment, the same number of the first conductive pillars 123 and the second conductive pillars 143 may be symmetrically disposed on opposite sides of the adhesive layer 160. In still another embodiment, the number of the first conductive pillars 123 on the first wafer 120 may be different from the number of the second conductive pillars 143 on the second wafer 140, and the first conductive pillar 123 and the second conductive pillar 143 are made. They are asymmetrically disposed on opposite sides of the adhesive layer 160.

As shown in FIG. 2, the first pad 112 is located in the orthographic projection of the first wafer 120 on the line carrier 110, and the second pad 113 surrounding the first pad 112 is located on the first wafer 120. In addition to the orthographic projection on the line carrier 110, the second wafer 140 is electrically connected to the second pad 113 by means of wire bonding. In this embodiment, one end of the bonding wire 150 is connected to the second conductive pillar 143 of the second wafer 140, and the other end of the bonding wire 150 is connected to the second pad 113 of the circuit carrier 110 to be electrically connected. The second conductive pillar 143 and the second pad 113. In general, the material of the bonding wire 150 may include copper, gold, silver, or an alloy of the above metals.

In short, since the wafer stack package structure 100 of the present embodiment includes the first wafer 120 and the second wafer 140 stacked on each other, the first wafer 120 can be electrically connected to the first conductive pillar 123 by flip-chip bonding. A pad 112 is disposed, and the second wafer 140 can be electrically connected to the second pad 113 by means of wire bonding. Therefore, the number of pins on the line carrier 110 having a limited wiring area can be obtained. In order to meet the design requirements of high integration and micro-pitch.

In addition, the material of the first conductive pillar 123 and the second conductive pillar 143 may be selected from one of a group consisting of copper, gold, silver or an alloy of the above metals. Preferably, the first conductive pillar 123 and The second conductive pillars 143 are all copper or copper alloy pillars, but the invention is not limited thereto. Specifically, the first wafer 120 is bonded to the line carrier 110 through the copper pillars, and then supported by the copper pillars above the line carrier 110. The first wafer 120 and the second wafer 140 stacked on each other are also located. The copper pillars on the active surface 121 of the first wafer 120 are supported, so that no underfill is required to be filled between the active surface 121 of the first wafer 120 and the surface 111a of the substrate 111. Due to copper The metal material has low resistance and high electromigration resistance, so the copper pillar is used as a medium for electrically connecting the first wafer 120 and the wiring carrier 110, and the copper pillar is used as the bonding wire 150 and the second wafer. The medium that is electrically connected between 140 can effectively reduce the probability of current pushing and electromigration effects.

Referring to FIG. 2 , in the embodiment, the wafer stack package structure 100 further includes an encapsulant 170 , which may be made of epoxy resin. The encapsulant 170 is formed on the surface 111a of the substrate 111 for covering the second pad 113, the first wafer 120, the second wafer 140, the second conductive pillar 143, and the bonding wire 150, wherein the encapsulant 170 is further filled. The first active surface 121 and the line carrier 110 are interposed to cover the first conductive pillars 123, the solder balls 130, and the first pads 112. The first conductive pillar 123 can improve the bonding area and bonding strength between the circuit carrier 110 and the first wafer 120 and the encapsulant 170, and the second conductive pillar 143 can improve the bonding between the second wafer 140 and the encapsulant 170. The area and bonding strength, thus helping to improve the delamination of the encapsulant 170 to improve the reliability of the wafer stack package structure 100.

Other embodiments are listed below for illustration. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

3 is a cross-sectional view showing a wafer stack package structure according to another embodiment of the present invention. Referring to FIG. 3, the wafer stack package structure 100A of FIG. 3 is substantially similar to the wafer stack package structure 100 of FIG. 2, but the main difference between the two is: in the wafer stack In the stacked package structure 100A, each of the second conductive pillars 143 may have a metal layer 144, wherein each of the metal layers 144 is located at an end 143a of the corresponding second conductive pillar 143 that is relatively far from the second active surface 141. Generally, each metal layer 144 is formed on the end portion 143a of the corresponding second conductive pillar 143 by electroplating, wherein the metal layer 144 is made of aluminum and has a thickness of about 0.6 micrometers to 0.9 micrometers. between. Therefore, the bonding wire 150 of the present embodiment can be bonded to the end portion 143a of the second conductive pillar 143 through the metal layer 144, thereby increasing the bonding strength between the bonding wire 150 and the second conductive pillar 143.

In summary, the wafer stack package structure of the present invention may include a first wafer and a second wafer stacked on each other, wherein the first wafer may be electrically bonded to the first pad by flip-chip bonding, and The second wafer can be electrically connected to the second pad by wire bonding, so that the number of high pins can be obtained on the line carrier with limited wiring area to meet the high integration and fine pitch. Design needs. On the other hand, the first wafer can be supported by the first conductive pillar above the line carrier, so that it is not necessary to fill the primer between the first wafer and the line carrier. Since the first conductive pillar and the second conductive pillar are both copper pillars, wherein copper is a metal material with low resistance and high electromigration resistance, the copper pillar is used as the electrical property between the first wafer and the line carrier. The medium to be connected, as well as the copper column as the medium for the electrical connection between the bonding wire and the second wafer, can effectively reduce current pushing and electromigration (the probability of occurrence of effects). In addition, the encapsulant can also pass through the first conductive pillar and the second conductive pillar to tightly bond to the line carrier and the oppositely stacked first wafer and the second wafer, thereby helping to improve the phenomenon of encapsulation colloid delamination. Improve the reliability of the wafer stack package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ wafer stacking structure

110‧‧‧Line carrier

111‧‧‧Substrate

111a‧‧‧ surface

112‧‧‧First mat

113‧‧‧second mat

120‧‧‧First chip

121‧‧‧First active surface

122‧‧‧ first back

123‧‧‧First conductive column

130‧‧‧ solder balls

140‧‧‧second chip

141‧‧‧Second active surface

142‧‧‧ second back

143‧‧‧Second conductive column

150‧‧‧welding line

160‧‧‧Adhesive layer

170‧‧‧Package colloid

Claims (10)

A wafer stacking package structure includes: a line carrier board having a plurality of first pads and a plurality of second pads surrounding the first pads; a first chip disposed on the line carrier board, the The first wafer has a first active surface, a first back surface opposite to the first active surface, and a plurality of first conductive pillars on the first active surface; a plurality of solder balls electrically connected to the first a conductive pillar and the first pads; a second wafer having a second active surface, a second back surface opposite to the second active surface, and a plurality of second conductive pillars connected to the second active surface The second wafer is disposed on the first wafer, and the second back surface and the first back surface are opposite to each other; and the plurality of bonding wires are electrically connected to the second conductive pillars and the second pads respectively One end of each of the bonding wires is connected to the corresponding second conductive post, and the other end of each of the bonding wires is connected to the corresponding second pad. The wafer stack package structure according to claim 1, wherein the material of the bonding wires comprises copper, gold, silver or an alloy of the above metals. The wafer stack package structure of claim 1, wherein the materials of the first conductive pillars and the second conductive pillars are selected from the group consisting of copper, gold, silver or alloys of the above metals. One of the materials. The wafer stack package structure of claim 3, wherein each of the second conductive pillars has a metal layer, and each of the metal layers is located at the corresponding second conductive layer. The post is relatively far from one end of the second active surface. The wafer stack package structure of claim 4, wherein the material of the metal layers comprises aluminum. The wafer stack package structure of claim 1, wherein the first pads are located in an orthographic projection of the first wafer on the line carrier. The wafer stack package structure of claim 1, wherein the second pads are located outside the orthographic projection of the first wafer on the line carrier. The wafer stack package structure of claim 1, further comprising: an adhesive layer connecting the first back surface and the second back surface. The wafer stack package structure of claim 1, further comprising: an encapsulant covering the second pads, the first wafer, the second wafer, the second conductive pillars, and the And bonding the first active surface and the line carrier to cover the first conductive pillars, the solder balls, and the first pads. The wafer stack package structure of claim 1, wherein the first back surface has a surface area greater than or equal to a surface area of the second back surface.