TWI585924B - Dram chip package structure - Google Patents

Description

Random dynamic memory chip package structure

The present invention relates to a random dynamic memory chip package structure having a multi-wafer stacked package structure.

With the proliferation of mobile multimedia products and their urgent need for higher digital signal processing, new storage architectures with higher storage capacity and flexibility, the application of multi-chip stacked chip package structures is growing rapidly.

In the current random dynamic memory dual die package structure, the active surface of the upper wafer and the active surface of the lower wafer are arranged oppositely. Generally, the active surface of the lower wafer is toward the circuit substrate, while the active surface of the upper wafer is away from the wiring substrate. When the upper wafer and the lower wafer are designed as double-row pads, the pads of the upper wafer and the lower wafer can be designed so that the pads on the same side of the upper wafer and the lower wafer can be electrically connected to the corresponding solder balls. For each other as a mirror. However, producing two wafers with mirrored mounting pads increases manufacturing costs.

Alternatively, the rewiring process can be performed on the wafer so that the pads of the upper wafer and the pads of the lower wafer have the same configuration. However, performing the rewiring process on the wafer not only increases the manufacturing cost but also increases the wiring area.

The present invention provides a random dynamic memory chip package structure in which a wiring substrate under an upper wafer and a lower wafer is connected by a wiring substrate between an upper wafer and a lower wafer.

The present invention provides a random dynamic memory chip package structure including a first circuit substrate, a first wafer, a second circuit substrate, a second wafer, a plurality of solder balls, a plurality of first bumps, and a plurality of first bonding wires And encapsulation colloids. The first circuit substrate has opposite first and second surfaces. The first wafer has a first active surface, a first column of pads and a second column of pads, wherein the first column of pads is disposed in parallel with the second column of pads on the first active surface, and the first wafer is first active The surface is disposed on the first circuit substrate in a manner of facing the first surface, and the first wafer is electrically connected to the first circuit substrate by the first column pad and the second column pad. A plurality of solder balls are disposed on the second surface. The second circuit substrate has opposite third and fourth surfaces, and the second circuit substrate is disposed on the first wafer. a second wafer having a second active surface, a third column of pads, and a fourth column of pads, wherein the third column of pads is disposed on the second active surface in parallel with the fourth column of pads, and the second wafer is in a second active The surface is disposed on the second circuit substrate in a manner of facing the third surface, and the second wafer is electrically connected to the second circuit substrate through the third pad row and the fourth pad row. The plurality of first bumps connect the third row of pads and the second circuit substrate and the fourth column of pads and the second circuit substrate. A plurality of first bonding wires connect the first circuit substrate and the second circuit substrate. The encapsulant is disposed on at least the first surface and covers the first wafer, the second wafer, the second wiring substrate, and the first bonding wire.

In one embodiment of the present invention, the first wafer is electrically connected to the first circuit substrate by a plurality of second bonding wires, and the first circuit substrate has a first row of pads and a second column of pads. Slotting, the second bonding wire passes through the slot to connect the first row of pads with the first circuit substrate and the second column of pads and the first circuit substrate. The encapsulant covers the second bonding wire, the first column pad and the second column pad.

In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the first circuit substrate and the first wafer.

In one embodiment of the present invention, the first wafer is electrically connected to the first circuit substrate by the plurality of second bumps, and the second bump is connected to the first row of pads and the second circuit substrate and is connected to the second substrate. The column pads are connected to the first circuit substrate.

In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the first circuit substrate and the first wafer.

In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the first row of pads, the second column of pads, and the second bumps.

In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the second circuit substrate and the second wafer.

In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the third row of pads, the fourth row of pads, and the first bumps.

The present invention provides a random dynamic memory chip package structure including a first circuit substrate, a first wafer, a second circuit substrate, a second wafer, a plurality of solder balls, a plurality of first bumps, and a plurality of second bumps , a plurality of first bonding wires and a package colloid. The first circuit substrate has opposite first and second surfaces. The first wafer has a first active surface, a first column of pads and a second column of pads, wherein the first column of pads is disposed in parallel with the second column of pads on the first active surface, and the first wafer is first active The surface is disposed on the first circuit substrate in such a manner as to be away from the first surface. A plurality of solder balls are disposed on the second surface. a second circuit substrate having opposite third and fourth surfaces, the second circuit substrate being disposed on the first wafer with the fourth surface facing the first active surface, and the first wafer is coupled to the first wafer by the first row of pads The second column of pads is electrically connected to the second circuit substrate. a second wafer having a second active surface, a third column of pads, and a fourth column of pads, wherein the third column of pads is disposed on the second active surface in parallel with the fourth column of pads, and the second wafer is in a second active The surface is disposed on the second circuit substrate in a manner of facing the third surface, and the second wafer is electrically connected to the second circuit substrate through the third pad row and the fourth pad row. The plurality of first bumps connect the third row of pads and the second circuit substrate and connect the fourth column of pads and the second circuit substrate. The plurality of second bumps connect the first column of pads and the second circuit substrate and connect the second column of pads and the second circuit substrate. The plurality of first bonding wires are electrically connected to the first circuit substrate and the second circuit substrate. The encapsulant is disposed on the first surface and covers the first wafer, the second wafer, the second wiring substrate, and the first bonding wire.

In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the first circuit substrate and the first wafer.

In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the second circuit substrate and the first wafer.

In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the first row of pads, the second column of pads, and the second bumps.

In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the second circuit substrate and the second wafer. In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the third row of pads, the fourth row of pads, and the first bumps.

Based on the above, in the random dynamic memory chip package structure of the present invention, since the circuit substrate is provided between the upper wafer and the lower wafer, and the upper wafer having the double-row pad design is flip-chip bonded to the circuit substrate Electrically connected, it can be placed in the same direction as the wafer with the lower row of the double-row pad design, which simplifies process complexity. Alternatively, the upper wafer and the lower wafer having the double-row pad design can be connected to the circuit substrate therebetween by using the respective double-row pads, and the upper wafer and the lower wafer can be connected to the wiring by the interconnections in the circuit substrate. The pads around the substrate are electrically connected, so that it is not necessary to fabricate the wafers with the mirrors mirrored each other or to perform a rewiring process on the wafers to solve the problem that the upper wafers are opposite to the lower wafers.

The above described features and advantages of the invention will be apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a wafer package structure in accordance with a first embodiment of the present invention. Referring to FIG. 1 , the chip package structure 10 of the present embodiment includes a circuit substrate 100 , a wafer 110 , a circuit substrate 120 , a wafer 130 , solder balls 140 , a bonding wire 150 , an encapsulant 160 , an adhesive layer 170 , an adhesive layer 180 , and an adhesive layer . 190. The circuit substrate 100 is, for example, a printed wiring board. The circuit substrate 100 has surfaces 100a and surfaces 100b opposed to each other. The pad 102a and the pad 102b are disposed on the surface 100a and the surface 100b, respectively. The material of the pad 102a and the pad 102b is, for example, copper, gold, silver, aluminum or an alloy of the above metals.

The solder balls 140 are disposed on the surface 100b and are connected to the pads 102b on the surface 100b. The material of the solder ball 140 is, for example, tin. The chip package structure 10 can be electrically connected to external circuits or other electronic components through the solder balls 140.

The wafer 110 has an active surface 110a, a back surface 110b, a first column of pads 112, and a second column of pads 114. The first column of pads 112 are disposed in parallel with the second column of pads 114 on the active surface 110a. In the present embodiment, the first row of pads 112 are disposed in parallel with the second row of pads 114 in the intermediate region of the active surface 110a. The wafer 110 is disposed on the circuit substrate 100 such that the active surface 110a faces the surface 100a. The bumps 116 are connected to the first row of pads 112 and the pads 102a and are connected to the second column pads 114 and the pads 102a to electrically connect the wafer 110 and the circuit substrate 100. In other words, the wafer 110 is electrically connected to the circuit substrate 100 by flip chip bonding. The material of the bumps 116 is, for example, gold, copper, tin or an alloy of the above metals.

The wafer 110 is fixed to the wiring substrate 100 through the adhesive layer 170. In the present embodiment, the adhesive layer 170 has an insulating property. The adhesive layer 170 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 170 is disposed between the circuit substrate 100 and the wafer 110 and exposes the first row of pads 112, the second column of pads 114, the bumps 116, and the pads 102a connected thereto. In addition, the space formed by the surface 100a, the active surface 110a and the adhesive layer 170 may be filled by an underfill 118, and the first row of pads 112, the second row of pads 114, the bumps 116 and A pad 102a connected thereto. The material of the primer 118 is, for example, an epoxy resin.

The circuit substrate 120 is disposed on the back surface 110b of the wafer 110. The circuit substrate 120 is, for example, a printed circuit board. The circuit substrate 120 has surfaces 120a and 120b opposed to each other. The pads 122 are disposed on the surface 120a. The material of the pad 112 is, for example, copper, gold, silver, aluminum or an alloy of the above metals.

The wiring substrate 120 is fixed to the wafer 110 by the adhesive layer 180. The adhesive layer 180 is, for example, an insulating layer, an insulating film or an insulating heat sink.

The wafer 130 has an active surface 130a, a back surface 130b, a third row of pads 132, and a fourth row of pads 134, wherein the third row of pads 132 are disposed in parallel with the fourth column of pads 134 on the active surface 130a. In the present embodiment, the third row of pads 132 are disposed in parallel with the fourth row of pads 134 in the intermediate region of the active surface 130a. The wafer 130 is disposed on the circuit substrate 120 such that the active surface 130a faces the surface 120a. The bumps 136 are connected to the third column pads 132 and the pads 122 and connect the fourth column pads 134 and the pads 122 to electrically connect the wafers 130 and the circuit substrate 120. In other words, the wafer 130 is electrically connected to the circuit substrate 120 by flip chip bonding. The material of the bumps 136 is, for example, gold, copper, tin or an alloy of the above metals.

The wafer 130 is fixed to the wiring substrate 120 by the adhesive layer 190. In the present embodiment, the adhesive layer 190 has an insulating property. The adhesive layer 190 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 190 is disposed between the circuit substrate 120 and the wafer 130 and exposes the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads 122 connected thereto. The space formed by the surface 120a, the active surface 130a and the adhesive layer 190 may be filled by the primer 138, and the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads connected thereto may be covered. 122.

The two ends of the bonding wire 150 are respectively connected to the pad 122 on the surface 120a and the pad 102a on the surface 100a to electrically connect the circuit substrate 120 to the circuit substrate 100. The material of the bonding wire 150 is, for example, copper, gold, silver or an alloy of the above metals.

The encapsulant 160 is disposed on the surface 100a and covers the wafer 110, the wafer 130, the wiring substrate 120, and the bonding wires 150. The material of the encapsulant 160 is, for example, an epoxy resin.

In this embodiment, since the chip package structure 10 includes the circuit substrate 120, the wafer 130 having the double-row pad design is electrically connected to the circuit substrate 120 by flip-chip bonding and the wafer having the double-row pad design. The arrangement direction of the 110 is the same, so that it is not necessary to manufacture a wafer in which the pads are mirror images or an additional rewiring process on the wafer to solve the problem that the arrangement of the upper wafer and the lower wafer is opposite.

2 is a schematic view of a chip package structure in accordance with a second embodiment of the present invention. The wafer package structure 20 of FIG. 2 is substantially similar to the wafer package structure 10 of FIG. In FIG. 2, the same elements as those in FIG. 1 will be denoted by the same reference numerals and will not be separately described. Referring to FIG. 2, the main difference between the chip package structure 20 of FIG. 2 and the chip package structure 10 of FIG. 1 is that in the embodiment, the adhesive layer 170 and the adhesive layer 190 are adhesive layers having an opposite conductivity. The adhesive layers 170 and 190 are, for example, an anisotropic conductive film (ACF). The adhesive layer 170 is disposed between the circuit substrate 100 and the wafer 110 and covers the first row of pads 112, the second row of pads 114, the bumps 116, and the pads 102a connected thereto. The adhesive layer 190 is disposed between the circuit substrate 120 and the wafer 130 and covers the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads 122 connected thereto.

In this embodiment, the first layer of the pad 112, the second row of pads 114, the bumps 116, and the pads 102a connected thereto are directly replaced by the adhesive layer 170, and the adhesive layer 190 is used instead. The primer covers the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads 122 connected thereto, thereby avoiding the problem that the filling primer may be incomplete during the filling of the primer.

In this embodiment, the adhesive layer 170 and the adhesive layer 190 are both adhesive layers having an opposite conductivity. However, the present invention is not limited thereto. In one embodiment, the adhesive layer 170 may be an adhesive layer having an isotropic conductivity, and the adhesive layer 190 may be an insulating adhesive layer. In another embodiment, the adhesive layer 170 may be an insulating adhesive layer, and the adhesive layer 190 is an adhesive layer having an isotropic conductivity.

3 is a schematic diagram of a chip package structure in accordance with a third embodiment of the present invention. The wafer package structure 30 of FIG. 3 is substantially similar to the wafer package structure 10 of FIG. In FIG. 3, the same components as those in FIG. 1 will be denoted by the same reference numerals and will not be described herein. Referring to FIG. 1 and FIG. 3 simultaneously, the main difference between the chip package structure 30 of FIG. 3 and the chip package structure 10 of FIG. 1 is that, in FIG. 1, the wafer 110 is electrically connected to the circuit substrate 100 by bumps 116. That is, the wafer 110 is electrically connected to the circuit substrate 100 in a flip chip bonding manner. In FIG. 3, the wafer 110 is electrically connected to the circuit substrate 100 by a bonding wire 316, that is, the wafer 110 is electrically connected to the circuit substrate 100 by wire bonding.

In detail, in FIG. 3, the circuit substrate 100 has a slot 318 exposing the first row of pads 112 and the second row of pads 114, and the bonding wires 316 pass through the slots 318 to connect the first row of pads 112 to the surface. The pad 102b on the 100b and the pad 102b on the surface 100b are connected to the second row of pads 114b. The encapsulant 160 fills the trench 318 and covers the bonding wires 316, the first column pads 112, the second column pads 114, and the pads 102b connected to the bonding wires 316.

Similarly, in other embodiments, the insulating adhesive layer 190 of FIG. 3 can also be replaced with an adhesive layer having an anisotropic conductivity.

4 is a schematic view of a chip package structure in accordance with a fourth embodiment of the present invention. Referring to FIG. 4 , the chip package structure 40 of the present embodiment includes a circuit substrate 400 , a wafer 410 , a circuit substrate 420 , a wafer 430 , solder balls 440 , a bonding wire 450 , an encapsulant 460 , an adhesive layer 470 , an adhesive layer 480 , and an adhesive layer . 490. The circuit substrate 400 is, for example, a printed circuit board. The circuit substrate 400 has surfaces 400a and 400b opposed to each other. The pads 402a and the pads 402b are disposed on the surface 400a and the surface 400b, respectively. The material of the pad 402a and the pad 402b is, for example, copper, gold, silver, aluminum or an alloy of the above metals.

Solder balls 440 are disposed on surface 400b and are coupled to pads 402b on surface 400b. The material of the solder balls 440 is, for example, tin. The chip package structure 40 can be electrically connected to external circuits or other electronic components through the solder balls 440.

The wafer 410 has an active surface 410a, a back surface 410b, a first row of pads 412, and a second column of pads 414, wherein the first column of pads 412 are disposed in parallel with the second column of pads 414 on the active surface 410a. In the present embodiment, the first row of pads 412 are disposed in parallel with the second row of pads 414 in the intermediate region of the active surface 410a. The wafer 410 is disposed on the circuit substrate 400 in such a manner that the back surface 410b faces the surface 400a (ie, the active surface 410a is away from the surface 400a).

The wafer 410 is fixed to the wiring substrate 400 through the adhesive layer 470. The adhesive layer 470 is, for example, an insulating layer, an insulating film or an insulating heat sink.

The wiring substrate 420 has surfaces 420a and 420b opposed to each other. The wiring substrate 420 is disposed on the wafer 410 such that the surface 420b faces the active surface 410a. The circuit substrate 420 is, for example, a printed circuit board. The pads 422a and the pads 422b are disposed on the surface 420a and the surface 420b, respectively. The material of the pads 422a and the pads 422b is, for example, copper, gold, silver, aluminum or an alloy of the above metals.

The bump 416 is connected to the first column pad 412 and the pad 422b and connects the second column pad 414 and the pad 422b to electrically connect the wafer 410 and the circuit substrate 420. The material of the bumps 416 is, for example, gold, copper, tin or an alloy of the above metals.

The wiring substrate 420 is fixed to the wafer 410 through the adhesive layer 480. In the present embodiment, the adhesive layer 480 has insulation properties. The adhesive layer 480 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 480 is disposed between the circuit substrate 420 and the wafer 410 and exposes the first row of pads 412, the second column of pads 414, the bumps 416, and the pads 422b connected thereto. The primer 418 fills the space formed by the surface 420b, the active surface 410a and the adhesive layer 480, and covers the first row of pads 412, the second row of pads 414, the bumps 416, and the pads 422b connected thereto. The material of the primer 418 is, for example, an epoxy resin.

The wafer 430 has an active surface 430a, a back surface 430b, a third row of pads 432, and a fourth column of pads 434, wherein the third column of pads 432 are disposed in parallel with the fourth column of pads 434 on the active surface 430a. In the present embodiment, the third row of pads 432 are disposed in parallel with the fourth row of pads 434 in the intermediate region of the active surface 430a. The wafer 430 is disposed on the wiring substrate 420 with the active surface 430a facing the surface 420a. The bumps 436 are connected to the third row of pads 432 and the pads 422 are connected and connected to the fourth row of pads 434 and the pads 422. In other words, the wafer 430 is electrically connected to the circuit substrate 420 by flip chip bonding. The material of the bump 436 is, for example, gold, copper, tin or an alloy of the above metals.

The wafer 430 is fixed to the wiring substrate 420 through the adhesive layer 490. In the present embodiment, the adhesive layer 490 has insulation properties. The adhesive layer 490 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 490 is disposed between the circuit substrate 420 and the wafer 430 and exposes the third row of pads 432, the fourth row of pads 434, the bumps 436, and the pads 422a connected thereto. The primer 438 fills the space formed by the surface 420a, the active surface 430a and the adhesive layer 490, and covers the third row of pads 432, the fourth row of pads 434, the bumps 436, and the pads 422a connected thereto.

The two ends of the bonding wire 450 are respectively connected to the pads 422a on the surface 420a and the pads 402a on the surface 400a to electrically connect the circuit substrate 420 and the circuit substrate 400.

The encapsulant 460 is disposed on the surface 400a and covers the wafer 410, the wafer 430, the wiring substrate 420, and the bonding wires 450. The material of the encapsulant 460 is, for example, an epoxy resin.

In the present embodiment, since the chip package structure 40 includes the circuit substrate 420, even in the case where the arrangement direction of the wafer 410 and the wafer 430 is opposite, the first row of pads 412 of the wafer 410 and the third row of the wafer 430 are connected. The pad 432 can be electrically connected to the pad 422a of the left half of FIG. 4 by the interconnection of the circuit substrate 420, and further electrically connected to the circuit substrate 400 by the bonding wire 450. Similarly, the second row of pads 414 of the wafer 410 and the fourth row of pads 434 of the wafer 430 can be electrically connected to the pads 422a of the right half of FIG. 4 by the interconnection of the circuit substrate 420, and further borrowed. The bonding wire 450 is electrically connected to the circuit substrate 400. Therefore, it is not necessary to manufacture a wafer in which the pads are mirror images or to perform a rewiring process on the wafer to solve the problem that the arrangement direction of the upper wafer and the lower wafer is opposite. In addition, since both the wafer 410 and the wafer 430 are electrically connected to the circuit substrate 420 first, and then the circuit substrate 400 and the circuit substrate 420 are connected by the bonding wire 450, it is possible to avoid the unequal length of the upper wafer and the lower wafer. problem.

In this embodiment, the adhesive layer 480 and the adhesive layer 490 are both insulating adhesive layers. However, the present invention is not limited thereto. In an embodiment, the adhesive layer 480 and the adhesive layer 490 may both be adhesive layers having an opposite conductivity. In another embodiment, the adhesive layer 480 can be an insulating adhesive layer, and the adhesive layer 490 can be an adhesive layer having an isotropic conductivity. In still another embodiment, the adhesive layer 490 can be an insulating adhesive layer, and the adhesive layer 480 can be an adhesive layer having an isotropic conductivity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 40: chip package structures 100, 120, 400, 420: circuit substrates 100a, 100b, 120a, 120b, 400a, 400b, 420a, 420b: surfaces 102a, 102b, 122, 402a, 402b, 422a, 422b: pads 110, 130, 410, 430: wafers 110a, 130a, 410a, 430a: active surfaces 110b, 130b, 410b, 430b: backs 112, 412: first row of pads 114, 414: second row of pads 116, 136, 416, 436: bumps 118, 138, 418, 438: primer 132, 432: third row of pads 134, 434: fourth row of pads 140, 440: solder balls 150, 316, 450: Bonding wires 160, 360: encapsulant 170, 180, 190, 470, 480, 490: adhesive layer 318: slotted

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a wafer package structure in accordance with a first embodiment of the present invention. 2 is a cross-sectional view showing a wafer package structure in accordance with a second embodiment of the present invention. 3 is a cross-sectional view showing a wafer package structure in accordance with a third embodiment of the present invention. 4 is a cross-sectional view showing a wafer package structure in accordance with a fourth embodiment of the present invention.

30: chip package structure 100, 120: circuit substrate 100a, 100b, 120a, 120b: surface 102a, 102b, 122: pads 110, 130: wafer 110a, 130a: active surface 110b, 130b: back 112: first row Pad 114: second row of pads 136: bumps 138: primer 132: third row of pads 134: fourth row of pads 140: solder balls 150, 316: bonding wires 160: encapsulants 170, 180, 190: Adhesive layer 318: slotted

Claims (15)

A random dynamic memory chip package structure, comprising: a first circuit substrate having opposite first and second surfaces; a first wafer having a first active surface, a first column of pads, and a second column of pads, wherein The first row of pads are disposed on the first active surface in parallel with the second column of pads, and the first wafer is disposed on the first surface with the first active surface facing the first surface On the first circuit substrate, the first wafer is electrically connected to the first circuit substrate by the first column pad and the second column pad; and a plurality of solder balls are disposed on the first circuit substrate a second circuit substrate having opposite third and fourth surfaces, the second circuit substrate being disposed on the first wafer; the second wafer having a second active surface and a third row of pads And a fourth row of pads, wherein the third column of pads is disposed on the second active surface in parallel with the fourth column of pads, and the second wafer faces the second active surface a three-surface manner disposed on the second circuit substrate The second wafer is electrically connected to the second circuit substrate by the third pad row and the fourth pad row; the plurality of first bumps are connected to the third column pad and the ground a second circuit substrate connected to the fourth column pad and the second circuit substrate; a plurality of first bonding wires connecting the first circuit substrate and the second circuit substrate; and an encapsulant, at least configured On the first surface, and covering the first wafer, the second wafer, the second circuit substrate, and the first bonding wire. The random dynamic memory chip package structure of claim 1, wherein the first wafer is electrically connected to the first circuit substrate by a plurality of second bonding wires, and the first circuit substrate a slot having the first row of pads and the second row of pads exposed, the second wire passing through the slot to connect the first column of pads with the first circuit substrate and Connecting the second column of pads to the first circuit substrate, the encapsulant covering the second bonding wire, the first column pad and the second column pad. The random dynamic memory chip package structure of claim 2, further comprising an adhesive layer disposed between the first circuit substrate and the first wafer. The random dynamic memory chip package structure of claim 1, wherein the first wafer is electrically connected to the first circuit substrate by a plurality of second bumps, and the second bump is connected. The first column of pads and the first circuit substrate are connected to the second column of pads and the first circuit substrate. The random dynamic memory chip package structure of claim 4, further comprising an adhesive layer disposed between the first circuit substrate and the first wafer. The random dynamic memory chip package structure of claim 5, wherein the adhesive layer is electrically conductive and covers the first column pad, the second column pad, and the second protrusion Piece. The random dynamic memory chip package structure of claim 1, further comprising an adhesive layer disposed between the second circuit substrate and the first wafer. The random dynamic memory chip package structure of claim 1, further comprising an adhesive layer disposed between the second circuit substrate and the second wafer. The random dynamic memory chip package structure of claim 8, wherein the adhesive layer is electrically conductive and covers the third column pad, the fourth column pad, and the first protrusion Piece. A random dynamic memory chip package structure, comprising: a first circuit substrate having opposite first and second surfaces; a first wafer having a first active surface, a first column of pads, and a second column of pads, wherein The first row of pads is disposed on the first active surface in parallel with the second column of pads, and the first wafer is disposed on the first active surface in a manner away from the first surface a first circuit substrate; a plurality of solder balls disposed on the second surface; a second circuit substrate having opposite third and fourth surfaces, the second circuit substrate facing the fourth surface The first active surface is disposed on the first wafer, and the first wafer is electrically connected to the second circuit substrate by the first column pad and the second column pad; The second wafer has a second active surface, a third row of pads, and a fourth row of pads, wherein the third column of pads is disposed on the second active surface in parallel with the fourth column of pads. The second wafer is oriented toward the second active surface The third surface is disposed on the second circuit substrate, and the second wafer is electrically connected to the second circuit substrate by the third pad row and the fourth pad row; a first bump connecting the third column pad and the second circuit substrate and connecting the fourth column pad and the second circuit substrate; a plurality of second bumps connecting the first column a pad and the second circuit substrate and connecting the second column pad and the second circuit substrate; a plurality of first bonding wires electrically connecting the first circuit substrate and the second circuit substrate; And an encapsulant disposed on the first surface and covering the first wafer, the second wafer, the second wiring substrate, and the first bonding wire. The random dynamic memory chip package structure of claim 10, further comprising an adhesive layer disposed between the first circuit substrate and the first wafer. The random dynamic memory chip package structure of claim 10, further comprising an adhesive layer disposed between the second circuit substrate and the first wafer. The random dynamic memory chip package structure according to claim 12, wherein the adhesive layer is electrically conductive and covers the first column pad, the second column pad, and the second protrusion Piece. The random dynamic memory chip package structure of claim 10, further comprising an adhesive layer disposed between the second circuit substrate and the second wafer. The random dynamic memory chip package structure of claim 14, wherein the adhesive layer is electrically conductive and covers the third column pad, the fourth column pad, and the first protrusion Piece.