CN101853845B - Multichip stacking encapsulation - Google Patents
Multichip stacking encapsulation Download PDFInfo
- Publication number
- CN101853845B CN101853845B CN2009101305754A CN200910130575A CN101853845B CN 101853845 B CN101853845 B CN 101853845B CN 2009101305754 A CN2009101305754 A CN 2009101305754A CN 200910130575 A CN200910130575 A CN 200910130575A CN 101853845 B CN101853845 B CN 101853845B
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- chip
- bearing seat
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- active face
- chip bearing
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- 238000005538 encapsulation Methods 0.000 title claims abstract description 41
- 239000012790 adhesive layer Substances 0.000 claims description 23
- 239000000084 colloidal system Substances 0.000 claims description 14
- 239000002390 adhesive tape Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 6
- 238000012856 packing Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 238000005253 cladding Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229920000297 Rayon Polymers 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses multichip stacking encapsulation. An embodiment of multichip stacking encapsulation comprises a first chip, a first chip carrying seat, a plurality of first leads, a second chip, a sticking layer, a second chip carrying seat and a plurality of second leads, wherein the first chip is provided with a first active surface and a first back; the first chip carrying seat is provided with a first opening and jointed with the first active surface; the first leads pass through the first opening and are used for being electrically connected with the first active surface and the first carrying seat; the second chip is provided with a second active surface and a second back; the sticking layer is used for cladding the first leads and sticking and combining the first chip carrying seat and the second back; the second chip carrying seat is provided with a second opening and jointed and electrically connected with the second active surface; and the second leads pass through the second opening and are used for being electrically connected with the second active surface and the second chip carrying seat.
Description
Technical field
The invention relates to a kind of semiconductor chip package, particularly about a kind of multi-chip stacking encapsulation.
Background technology
With a plurality of chip-stacked being packaged in the packaging body, can improve the density of electronic component, shorten the electrical path between electronic component, this technology not only can reduce a plurality of chips and use upward shared volume, more can improve the whole performance of a plurality of chips.And in a plurality of chip-stacked encapsulation technologies, the stacked package technology of a plurality of unidimensional chips is one of common encapsulation technologies.
The stacked package of a plurality of unidimensional chips is that the semiconductor chip with a plurality of same sizes up is stacked on the substrate one by one, and the active face of those semiconductor chips is to connect in order to bonding wire up usually.In order to prevent that the bonding wire that each time square chip connects is stacked in the chip damage of its top or causes short circuit, at each chip chamber one distance piece (interposer) is provided all, and the height of this distance piece need be higher than the camber with one deck bonding wire.Traditionally, distance piece can be Polyimide adhesive tape (PI tape), empty chip (dummy chip) or sheet metal (metalplate) or the like.
Yet the use of distance piece need increase extra processing procedure, for example: and the coating of chip viscose glue, chip installation and mature making process etc., and the increase of this extra processing procedure all can cause the increase of cost and the reduction of yield.
In addition, yield is important considering as far as multicore sheet encapsulation, because after a plurality of chips are inserted single encapsulation; The result of the compound yield of its generation; Can cause hurriedly increasing of cost, especially when comprising the chip of any high price in the packaging body, considering of its risk is particularly important.Because when at a low price chip damages or dresses up when causing defective in the chip-stacked process in subsequent group, chips of these high prices must together be scrapped, and this certainly will cause impact serious on the cost.
Therefore, in the face of the trend of multicore sheet encapsulation, and the expensive risk of multicore sheet encapsulation now, industrial circle still needs the multichip packaging structure of a kind of low cost, high yield.
Summary of the invention
The present invention provides a kind of multi-chip stacking encapsulating structure, utilize one first chip bearing holder structure with chip-stacked on the chip of being located on the substrate, pile up encapsulating structure to form one.The present invention combines the chip encapsulation technology and the chip-stacked technology of high yield, and the multi-chip stacking encapsulating structure of institute's construction has the advantage of high yield.
One embodiment of multi-chip stacking encapsulation of the present invention comprises one first chip with one first active face and one first back side; The first chip bearing seat that has one first opening and engage with first active face; Many through first opening and first lead that is used to electrically connect first active face and the first chip bearing seat; One second chip with one second active face and one second back side; One is used to coat the adhesive-layer at first lead and the cohesive bond first chip bearing seat and second back side; Tool second opening and the second chip bearing seat that engages and be electrical connected with second active face; Through many second leads of second opening be used to be electrical connected second active face and the second chip bearing seat; And many privates that are used to be electrically connected at this first chip bearing seat and the second chip bearing seat.
Another embodiment of multi-chip stacking encapsulation of the present invention comprises one first chip with one first active face and one first back side, the one first chip bearing seat that has one first opening and engage with this first active face; Through this first opening and electrically connect this first active face and many first leads of this first chip bearing seat; One second chip with one second active face and one second back side; Coat an adhesive-layer at this first chip bearing seat of these many first leads and cohesive bond and this second back side; Have one second opening and engage with this second active face, and the one second chip bearing seat that is electrical connected with this first chip bearing seat; Through this second opening and electrically connect this second active face and many second leads of this second chip bearing seat.
Among one embodiment, the first chip bearing seat of aforesaid multi-chip stacking encapsulating structure can be printed circuit board (PCB) (printed circuit board), lead frame (leadframe) or flexible circuit board (flexible circuit board).
Among one embodiment, first chip and second area of chip of aforesaid multi-chip stacking encapsulating structure can equate.
Among one embodiment, the adhesive-layer of aforesaid multi-chip stacking encapsulating structure is that a film covers weldering (Filmon Wire; FOW) line layer.
Among one embodiment, comprise the packing colloid of a coating first chip, the first chip bearing seat, second chip and many second leads in the aforesaid multi-chip stacking encapsulating structure in addition.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
The generalized section of the multi-chip stacking encapsulation 10 of Fig. 1 illustration one embodiment of the invention; And
The generalized section of the multi-chip stacking encapsulation 20 of Fig. 2 illustration another embodiment of the present invention.
The main element symbol description:
10,20 multi-chip stackings encapsulation
13,13 ' the first chip bearing seats
15 privates
16 adhesive-layers
17 insulating barriers
18 packing colloids
19 second chip bearing seats
21 outside terminals
111 first chips
112 second chips
121,122 colloids
131,131 ' inwall
132,132 ' the first openings
133 sides
141 first leads
142 second leads
191 inwalls
192,192 ' the second openings
1,111 first active faces
1,112 first back sides
1,121 second active faces
1,122 second back sides
Embodiment
The generalized section of the multi-chip stacking encapsulation 10 of Fig. 1 illustration first embodiment of the present invention.The multi-chip stacking encapsulation 10 that first embodiment of the invention discloses comprises one first chip 111, one first chip bearing seat 13, many first leads 141, one second chip 112, an adhesive-layer 16, one second chip bearing seat 19 and many second leads 142.First chip 111 comprise have on first active face 1111 and first back side, 1112, the first active faces 1111 with respect to first active face 1111 by a plurality of electronic components be connected the integrated circuit that distribution between each electronic component etc. forms.First active face 1111 that has first opening, 132, the first chips 111 that defined by inwall 131 on the first chip bearing seat 13 is engaged in this first chip bearing seat 13 towards this first opening 132.In the present embodiment, first chip 111 is to engage by colloid 121 with 13 of the first chip bearing seats, and this colloid 121 can be sticking brilliant glue (paste) or sticking brilliant adhesive tape (tape or film).
Many first leads 141 are through first opening 132 of the first chip bearing seat 13, electrically connect the opposite face that engages the surface of first chip 111 on first active face 1111 and the first chip bearing seat 13 of first chip 111.Adhesive-layer 16 is disposed at the first chip bearing seat 13 and engages on the opposite face on surface of first chip 111, and filling is in first opening 132 of the first chip bearing seat 13, and coats above-mentioned this first lead 141.In the present embodiment, adhesive-layer 16 can be film and covers lead (Film on Wire; FOW) layer can reduce packaging height promotes lead with the effect of wire-protecting is provided stability.
Many second leads 142 are through second opening 192 of the second chip bearing seat 19, electrically connect the opposite face that engages the surface of second chip 112 on second active face 1121 and the second chip bearing seat 19 of second chip 112.The adhesive-layer 16 that is disposed at the first chip bearing seat 13 and first chip 111 is to be engaged on second back side 1122 of second chip 112, and many privates 15 are first chip, 111 composition surfaces and second chip, 112 composition surfaces on this second chip bearing seat 19 that electrically connect on this first chip bearing seat 13.Packing colloid 18 coats first chip 111, the first chip bearing seat 13, second chip 112, privates 15; And filling is in second opening 192 of the second chip bearing seat 19; And coat this second lead 142, form the multi-chip stacking encapsulation 10 that first embodiment of the invention disclosed.Preferably; In present embodiment; An insulating barrier 17 more can be established in addition in the adhesive- layer 16 and 1122 at second back side of second chip 112 that are disposed on the first chip bearing seat 13 and first chip 111; Produce short circuit to prevent this first lead 141 from contacting with second chip 112, simultaneously can bonding first chip 111 and second chip 112.
In the present embodiment, the aforesaid first chip bearing seat 13 can be printed circuit board (PCB) (printed circuitboard, PCB) or lead frame (leadframe).And the second chip bearing seat can be printed circuit board (PCB) (printedcircuit board), lead frame (leadframe) or flexible circuit board (flexible circuit board).On the opposite face on the surface that engages second chip 112, can be provided with a plurality of outside terminals 21 in addition for example is the tin ball on this second chip bearing seat 19.
The generalized section of the multi-chip stacking encapsulation 20 of Fig. 2 illustration second embodiment of the invention.With reference to Fig. 1 and Fig. 2, the multi-chip stacking encapsulation 20 that present embodiment discloses comprise one first chip 111, one first chip bearing seat 13 ', many first leads 141, one second chip 112, an adhesive-layer 16, one second chip bearing seat 19 and many second leads 142.First chip 111 comprise have on first active face 1111 and first back side, 1112, the first active faces 1111 with respect to first active face 1111 by a plurality of electronic components be connected the integrated circuit that distribution between each electronic component etc. forms.The first chip bearing seat 13 ' on have first opening 132 by inwall 131 ' defined ', and first active face 1111 of this first chip 111 be towards this first opening 132 ', and be engaged in this first chip bearing seat 13 '.In the present embodiment, first chip 111 and the first chip bearing seat 13 ' be to engage by colloid 121, and this colloid 121 can be sticking brilliant glue (paste) or sticking brilliant adhesive tape (tape or film).
Many first leads 141 be through the first chip bearing seat 13 ' first opening 132 ', and electrically connect first active face 1111 and the first chip bearing seat 13 of this first chip 111 ' on engage the opposite face on the surface of first chip 111.Adhesive-layer 16 is to be disposed on the opposite face on surface of the first chip bearing seat 13 ' joint first chip 111, and filling in this first chip bearing seat 13 ' first opening 132 ', and coat above-mentioned this first lead 141.In the present embodiment, adhesive-layer 16 can be film and covers lead (Film on Wire; FOW) layer promotes the stability of lead except reducing packaging height also the effect of wire-protecting can be provided.
Many second leads 142 be second opening 192 through the second chip bearing seat 19 ', and electrically connect the opposite face that engages the surface of second chip 112 on second active face 1121 and this second chip bearing seat 19 of this second chip 112.
The adhesive-layer 16 that is disposed on the first chip bearing seat 13 and first chip 111 is to be engaged on second back side 1122 of second chip 112; And the first chip bearing seat 13 ' both side ends can be bent, cause the first chip bearing seat 13 ' side 133 on a plurality of contacts (not illustrating) must electrically connect with the second chip bearing seat 19.Packing colloid 18 coat first chip 111, the first chip bearing seat 13 ', second chip 112, privates 15; And filling in second opening 192 of the second chip bearing seat 19 '; And coat this second lead 142, form the multi-chip stacking encapsulation 20 that second embodiment of the invention disclosed.In the present embodiment, the first chip bearing seat 13 ' comprise flexible circuit board (flexible circuit board) or lead frame.In another embodiment; Be disposed at the first chip bearing seat 13 ' and first chip 111 on 1122 at second back side of adhesive-layer 16 and second chip 112 also can be shown in Fig. 1 embodiment as; Other establishes an insulating barrier (not illustrating); And utilize this insulating barrier (not illustrating) can prevent that this first lead 141 from contacting and producing short circuit with second chip 112, the while also can bonding first chip 111 and second chip 112.
And the second chip bearing seat can be printed circuit board (PCB) (printed circuit board), lead frame or flexible circuit board (flexible circuit board).On the opposite face on the surface that engages second chip 112, can be provided with a plurality of outside terminals 21 in addition for example is the tin ball on this second chip bearing seat 19.
In the embodiments of the invention, the area of aforementioned this first chip 111 and second chip 112 can equate, forms unidimensional multi-chip stacking encapsulation 10 and 20 and make.
In the embodiments of the invention, aforementioned this first chip 111 and second chip 112 can be dynamic random access memory.
The present invention utilizes adhesive-layer to can be film and covers lead (Film on Wire; FOW) therefore layer can reduce packaging height promotes lead with the effect of wire-protecting is provided stability.Simultaneously more can establish an insulating barrier in addition, produce short circuit to prevent first lead from contacting with second chip, simultaneously can bonding first chip 111 and second chip 112.And aforementioned two combinations are rejoined after can testing respectively, so can avoid the high price chip because of producing defective in the encapsulation process, and beyond economic repair cost risk, and then reach the multichip packaging structure of high yield.
Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still maybe be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by claims.
Claims (16)
1. multi-chip stacking encapsulation comprises:
One first chip has one first active face and one first back side;
One first chip bearing seat has one first opening, and engages with this first active face;
Many first leads through this first opening, and electrically connect this first active face and this first chip bearing seat;
One second chip has one second active face and one second back side;
One adhesive-layer coats these many first leads, and this first chip bearing seat of cohesive bond and this second back side;
One second chip bearing seat has one second opening, engages with this second active face;
A plurality of outside terminals are located at the surface of this second chip bearing seat;
Many second leads through this second opening, and electrically connect this second active face and this second chip bearing seat; And
Many privates are electrically connected at this first chip bearing seat and this second chip bearing seat.
2. multi-chip stacking encapsulation according to claim 1 is characterized in that, also comprises the packing colloid of this first chip of coating, this first chip bearing seat, this second chip and these many second leads.
3. multi-chip stacking encapsulation according to claim 1 is characterized in that this first chip bearing seat is a printed circuit board (PCB) or lead frame.
4. multi-chip stacking encapsulation according to claim 1 is characterized in that, this adhesive-layer is that a film covers conductor layer.
5. multi-chip stacking encapsulation according to claim 1 is characterized in that, this first chip and this first chip bearing seat are to be bonded with each other by a sticking brilliant glue or a sticking brilliant adhesive tape.
6. multi-chip stacking encapsulation according to claim 1 is characterized in that, this second chip and this second chip bearing seat are to be bonded with each other by a sticking brilliant glue or a sticking brilliant adhesive tape.
7. multi-chip stacking encapsulation according to claim 1 is characterized in that this second chip bearing seat is printed circuit board (PCB), lead frame or flexible circuit board.
8. multi-chip stacking encapsulation according to claim 1 is characterized in that this adhesive-layer filling is in this first opening.
9. multi-chip stacking encapsulation according to claim 1 is characterized in that, also comprises to be located at the middle insulating barrier of this adhesive-layer and this second back side.
10. multi-chip stacking encapsulation according to claim 1 is characterized in that this first chip and this second area of chip equate.
11. a multi-chip stacking encapsulation comprises:
One first chip has one first active face and one first back side;
One first chip bearing seat has one first opening, and engages with this first active face;
Many first leads through this first opening, and electrically connect this first active face and this first chip bearing seat;
One second chip has one second active face and one second back side;
One adhesive-layer coats these many first leads, and this first chip bearing seat of cohesive bond and this second back side;
One second chip bearing seat has one second opening, engages with this second active face, and is electrical connected with this first chip bearing seat;
A plurality of outside terminals are located at the surface of this second chip bearing seat; And
Many second leads through this second opening, and electrically connect this second active face and this second chip bearing seat.
12. multi-chip stacking encapsulation according to claim 11 is characterized in that this first chip bearing seat is flexible circuit board or lead frame, and has a plurality of contacts that are connected with this second chip bearing seat.
13. multi-chip stacking encapsulation according to claim 11 is characterized in that, this adhesive-layer is that a film covers conductor layer.
14. multi-chip stacking encapsulation according to claim 11 is characterized in that this adhesive-layer filling is in this first opening.
15. multi-chip stacking encapsulation according to claim 11 is characterized in that this first chip and this second area of chip equate.
16. multi-chip stacking encapsulation according to claim 11 is characterized in that, also comprises to be located at the middle insulating barrier of this adhesive-layer and this second back side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101305754A CN101853845B (en) | 2009-04-03 | 2009-04-03 | Multichip stacking encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101305754A CN101853845B (en) | 2009-04-03 | 2009-04-03 | Multichip stacking encapsulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101853845A CN101853845A (en) | 2010-10-06 |
| CN101853845B true CN101853845B (en) | 2012-02-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101305754A Expired - Fee Related CN101853845B (en) | 2009-04-03 | 2009-04-03 | Multichip stacking encapsulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI585924B (en) * | 2015-11-09 | 2017-06-01 | 力晶科技股份有限公司 | Dram chip package structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2543206Y (en) * | 2002-03-26 | 2003-04-02 | 胜开科技股份有限公司 | Internal storage chip stacking structure |
| CN101150119A (en) * | 2006-09-21 | 2008-03-26 | 三星电子株式会社 | Stacked semiconductor package and method of manufacturing the same |
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2009
- 2009-04-03 CN CN2009101305754A patent/CN101853845B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2543206Y (en) * | 2002-03-26 | 2003-04-02 | 胜开科技股份有限公司 | Internal storage chip stacking structure |
| CN101150119A (en) * | 2006-09-21 | 2008-03-26 | 三星电子株式会社 | Stacked semiconductor package and method of manufacturing the same |
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| Publication number | Publication date |
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| CN101853845A (en) | 2010-10-06 |
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