CN101232004A - Chip stack package structure - Google Patents
Chip stack package structure Download PDFInfo
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- CN101232004A CN101232004A CNA2007100040719A CN200710004071A CN101232004A CN 101232004 A CN101232004 A CN 101232004A CN A2007100040719 A CNA2007100040719 A CN A2007100040719A CN 200710004071 A CN200710004071 A CN 200710004071A CN 101232004 A CN101232004 A CN 101232004A
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- package structure
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- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
A chip stack package structure comprises a substrate, a first chip, a plurality of conductors, a second chip and a plurality of conductive columns. The substrate includes a first surface, and the first chip is arranged on the first surface and forms a first orthographic projection on the first surface. The conductors are arranged and electrically connected between the first chip and the first surface. The second chip is arranged on the first surface and forms a second orthographic projection on the first surface, wherein at least a portion of the first chip is between the second chip and the substrate; and the first orthographic projection and the second orthographic projection partially overlap at least. Additionally, the conductive columns are arranged and electrically connected between the second chip and the first surface.
Description
Technical field
The invention relates to a kind of semiconductor element, and particularly relevant for a kind of chip stack package structure (multi-chip package).
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the making (IC process) of the design of integrated circuit (IC design), integrated circuit and the encapsulation (IC package) of integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cut crystal steps such as (wafer sawing).Wafer has an active face (activesurface), the surface with active element (active element) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active face of wafer more disposed a plurality of connection pads (bonding pad), can outwards be electrically connected at carrier (carrier) via these connection pads so that finally cut formed chip by wafer.Carrier for example is lead frame (leadframe) or base plate for packaging (packagesubstrate).Chip can wire-bonded (wire bonding) or the flip-chip mode that engages (flip chip bonding) be connected on the carrier, make these connection pads of chip can be electrically connected at the contact of carrier, to constitute a chip-packaging structure.
With regard to flip-chip joining technique (flip chip bonding technology), usually on the active face of wafer, form after these connection pads, can on each connection pad, make a solder projection (solderbump), to electrically connect the usefulness of outer enclosure substrate as chip.Since these solder projections usually with the face arranged in array mode on the active face of chip, make the flip-chip joining technique be suitable for being used in the chip-packaging structure of high number of contacts and high contactor density, for example be applied to the flip-chip/spherical grid array type encapsulation (flip chip/ball grid array package) in the semiconductor packages industry at large.In addition, compare,, make the flip-chip joining technique can promote the electrical property of chip-packaging structure (electrical performance) because these projections can provide transmission path short between chip and the carrier with the wire-bonded technology.
Yet under the requirement for the high integration (integration) of electrical property maximization, low-cost and integrated circuit etc. of electronic industry now, the above-mentioned chip-packaging structure that has single-chip traditionally can't satisfy the requirement of electronic industry now fully.Therefore, it is a plurality of chip-stacked to form the direction that a kind of chip stack package structure will be worth effort to utilize wire-bonded technology or flip-chip joining technique to make.
In the prior art, be the media that is used as electrically connecting with bonding wire or solder projection between these chips of chip stack package structure and the substrate, but the density of bonding wire has certain limitation and transmission path longer, and under the situation that the height along with the chip that electrically connects with substrate increases, the occupied volume of solder projection also will increase gradually.Therefore, generally speaking, though be with bonding wire or solder projection as the media that electrically connects, the volume of the chip stack package structure of prior art is all bigger.
Summary of the invention
The purpose of this invention is to provide a kind of chip stack package structure, the volume that it had is less.
Another object of the present invention provides a kind of chip stack package structure, and the contactor density that its inside chip had is higher.
For reaching above-mentioned or other purposes, the present invention proposes a kind of chip stack package structure, and it comprises substrate, first chip, a plurality of electric conductor (conductive body), second chip and a plurality of conductive pole (conductive stud).Substrate has first surface, and first chip configuration is in forming first orthographic projection (orthogonal projection) on the first surface and on first surface.These electric conductors are disposed at and are electrically connected between first chip and the first surface.Second chip configuration is in forming second orthographic projection on the first surface and on first surface, wherein to small part first chip be between second chip and substrate, and first orthographic projection and second orthographic projection overlap at least (overlap).In addition, these conductive poles are disposed at and are electrically connected between second chip and the first surface.
In one embodiment of this invention, above-mentioned substrate also can have a depression (cavity), and it is positioned on the first surface, and wherein first chip is positioned at recess.
In one embodiment of this invention, the material of above-mentioned these conductive poles for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned these electric conductors can be conductive projection (conductivebump).
In one embodiment of this invention, the external form of above-mentioned these electric conductors can be identical with the external form of these conductive poles.In addition, the material of these electric conductors for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises adhesion coating (adhesive layer), and it is disposed between first chip and second chip.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises primer layer (underfill layer), and it coats these electric conductors and these conductive poles at least.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises a plurality of soldered balls (solder ball), and it is disposed on the second surface with respect to first surface of substrate.
For reaching above-mentioned or other purposes, the present invention proposes a kind of chip stack package structure, and it comprises substrate, first chip, a plurality of electric conductor, second chip, a plurality of first conductive pole, the 3rd chip and a plurality of second conductive pole.Substrate has first surface, and first chip configuration is in forming first orthographic projection on the first surface and on first surface.These electric conductors are disposed at and are electrically connected between first chip and the first surface.Second chip configuration is in forming second orthographic projection on the first surface and on first surface, wherein to small part first chip be between second chip and substrate, and first orthographic projection and second orthographic projection are overlapped at least, and these first conductive poles are disposed at and are electrically connected between second chip and the first surface.The 3rd chip configuration is in forming the 3rd orthographic projection on the first surface and on first surface, wherein to small part second chip be between the 3rd chip and substrate, and second orthographic projection and the 3rd orthographic projection are overlapped at least, and these second conductive poles are disposed at and are electrically connected between the 3rd chip and the first surface.
In one embodiment of this invention, above-mentioned substrate more can have a depression, and it is positioned on the first surface, and wherein first chip is positioned at recess.
In one embodiment of this invention, the material of above-mentioned these first conductive poles for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, the material of above-mentioned these second conductive poles for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned these electric conductors can be conductive projection.
In one embodiment of this invention, the external form of above-mentioned these electric conductors can be identical with the external form of these first conductive poles or these second conductive poles.In addition, the material of these electric conductors for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises first adhesion coating, and it is disposed between first chip and second chip.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises second adhesion coating, and it is disposed between second chip and the 3rd chip.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises primer layer, and it coats these electric conductors, these first conductive poles and these second conductive poles at least.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises a plurality of soldered balls, and it is disposed on the second surface with respect to first surface of substrate.
For reaching above-mentioned or other purposes, the present invention proposes a kind of chip stack package structure, and it comprises substrate, first chip, second chip, a plurality of first electric conductor and a plurality of first conductive pole.Substrate has first surface, and first chip configuration is in forming first orthographic projection on the first surface and on first surface.Second chip configuration is in forming second orthographic projection on the first surface and on first surface, and wherein part first chip is between second chip and substrate, and first orthographic projection and second orthographic projection are overlapped at least.These first electric conductors are disposed at and are electrically connected between first chip and second chip.In addition, these first conductive poles are disposed at and are electrically connected between second chip and the first surface.
In one embodiment of this invention, above-mentioned substrate also can have a depression, and it is positioned on the first surface, and wherein first chip is positioned at recess.
In one embodiment of this invention, the material of above-mentioned these first conductive poles for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned these first electric conductors can be conductive projection.
In one embodiment of this invention, the external form of above-mentioned these first electric conductors can be identical with the external form of these first conductive poles.In addition, the material of these first electric conductors for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises adhesion coating, and it is disposed between first chip and the substrate.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises primer layer, and it coats these first electric conductors and these first conductive poles at least.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises a plurality of soldered balls, and it is disposed on the second surface with respect to first surface of substrate.
In one embodiment of this invention, the said chip stack package structure also comprises the 3rd chip, a plurality of second electric conductor and a plurality of second conductive pole.Form the 3rd orthographic projection on this first surface of the 3rd chip configuration and on first surface, wherein part first chip is between the 3rd chip and substrate, and first orthographic projection and the 3rd orthographic projection are overlapped at least.These second electric conductors are disposed at and are electrically connected between first chip and the 3rd chip.These second conductive poles are disposed at and are electrically connected between the 3rd chip and the first surface.In addition, the material of these second conductive poles for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
For reaching above-mentioned or other purposes, the present invention proposes a kind of chip stack package structure, and it comprises substrate, first chip, a plurality of first electric conductor, second chip, a plurality of second electric conductor, the 3rd chip and a plurality of conductive pole.Substrate has first surface, and first chip configuration is in forming one first orthographic projection on the first surface and on first surface.These first electric conductors are disposed at and are electrically connected between first chip and the first surface.Second chip configuration is in forming second orthographic projection on the first surface and on first surface, and these second electric conductors are disposed at and are electrically connected between second chip and the first surface.The 3rd chip configuration is in forming the 3rd orthographic projection on the first surface and on first surface, wherein first chip and second chip are between the 3rd chip and substrate, and the 3rd orthographic projection is overlapped at least with first orthographic projection and second orthographic projection respectively, and these conductive poles are disposed at and are electrically connected between the 3rd chip and the first surface.
In one embodiment of this invention, above-mentioned substrate more can have two depressions, and it is positioned on the first surface, and wherein first chip and second chip lay respectively at these recess.
In one embodiment of this invention, the material of above-mentioned these conductive poles for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned these first electric conductors can be conductive projection.
In one embodiment of this invention, the external form of above-mentioned these first electric conductors can be identical with the external form of these conductive poles.In addition, the material of these first electric conductors for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned these second electric conductors can be conductive projection.
In one embodiment of this invention, the external form of above-mentioned these second electric conductors can be identical with the external form of these conductive poles.In addition, the material of these second electric conductors for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises adhesion coating, and it is disposed between the 3rd chip and first chip and between the 3rd chip and second chip.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises primer layer, and it coats these first electric conductors, these second electric conductors and these conductive poles at least.
In one embodiment of this invention, above-mentioned chip stack package structure also comprises a plurality of soldered balls, and it is disposed on the second surface with respect to first surface of substrate.
Based on above-mentioned, since these chips that chip stack package structure of the present invention had one of them is to be electrically connected to substrate by these conductive poles at least, and the occupied space of each conductive pole is less, so compare with the chip stack package structure of prior art, the volume of chip stack package structure of the present invention is less.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A illustrates the generalized section of a kind of chip stack package structure of first embodiment of the invention.
The chip that Figure 1B illustrates Figure 1A forms the schematic diagram of orthographic projection on substrate.
Fig. 1 C illustrates the generalized section of the another kind of chip stack package structure of first embodiment of the invention.
Fig. 2 A illustrates the generalized section of a kind of chip stack package structure of second embodiment of the invention.
The chip that Fig. 2 B illustrates Fig. 2 A forms the schematic diagram of orthographic projection on substrate.
Fig. 3 A illustrates the generalized section of a kind of chip stack package structure of third embodiment of the invention.
The chip that Fig. 3 B illustrates Fig. 3 A forms the schematic diagram of orthographic projection on substrate.
Fig. 3 C illustrates the generalized section of the another kind of chip stack package structure of third embodiment of the invention.
The chip that Fig. 3 D illustrates Fig. 3 C forms the schematic diagram of orthographic projection on substrate.
Fig. 4 A illustrates the generalized section of a kind of chip stack package structure of fourth embodiment of the invention.
The chip that Fig. 4 B illustrates Fig. 4 A forms the schematic diagram of orthographic projection on substrate.
Description of reference numerals
100,100 ', 200,300,300 ', 400: chip stack package structure
110,110 ', 210,310,310 ', 410: substrate
112,112 ', 116,212,312,312 ', 412: the surface
114 ': depression
120,120 ', 140,220,240,260,320,320 ', 340,340 ', 360,420,440,460: chip
130,230,330,430,450: electric conductor
142: connection pad
150,250,270,350,370,470: conductive pole
160: adhesion coating
170: primer layer
180: soldered ball
P120, P140, P220, P260, P260, P320, P320 ', P340, P340 ', P360, P420, P440, P460: orthographic projection
Embodiment
First embodiment
Figure 1A illustrates the generalized section of a kind of chip stack package structure of first embodiment of the invention, and the chip that Figure 1B illustrates Figure 1A forms the schematic diagram of orthographic projection on substrate.Please refer to Figure 1A and Figure 1B, the chip stack package structure 100 of first embodiment comprises substrate 110, first chip 120, a plurality of electric conductor 130, second chip 140 and a plurality of conductive poles 150.Substrate 110 has first surface 112, and first chip 120 is disposed on the first surface 112 and form the first orthographic projection P120 on first surface 112.
These electric conductors 130 are disposed at and are electrically connected between first chip 120 and the first surface 112.Second chip 140 is disposed on the first surface 112 and forms the second orthographic projection P140 on first surface 112, wherein to small part first chip 120 be between second chip 140 and substrate 110, and the first orthographic projection P120 and the second orthographic projection P140 overlap at least (overlap).In addition, these conductive poles 150 are disposed at and are electrically connected between the first surface 112 of second chip 140 and substrate 110.
Because second chip 140 is to be electrically connected to substrate 110 by these conductive poles 150, and the occupied space of each conductive pole 150 is less, so each connection pad (bondingpad) 142 correspondences of second chip 140 can be less with each conductive pole 150 contacted areas, and the spacing of adjacent these connection pads 142 (pitch) can be less.Therefore, compare with the chip stack package structure of prior art, second chip 140 of the chip stack package structure 100 of present embodiment is under the situation of the fixed amount of these connection pads 142, and the volume of second chip 140 can be less, and then makes that the volume of chip stack package structure 100 can be less.
Please refer to Fig. 1 C, it illustrates the generalized section of the another kind of chip stack package structure of first embodiment of the invention.In this mandatory declaration is that for the volume that makes chip stack package structure 100 ' is littler, substrate 110 ' also can have the depression 114 ' that is positioned on the first surface 112 ', and first chip 120 ' is positioned at depression and 114 ' locates.Such feature can shorten the length of these conductive poles 150 indirectly.
Refer again to Figure 1A and Figure 1B, among first embodiment, the material of these conductive poles 150 for example be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.In addition, these electric conductors 130 of first embodiment can be conductive projection, and its material can be lead-containing materials (for example lead or leypewter) or lead-free, and it comprises gold, copper, tin or nickel, and also can comprise alloy or the compound that contains gold, copper, tin or nickel.In this mandatory declaration be, for the volume that makes the chip 120 of winning can be less, the external form of these electric conductors 130 of first embodiment also can be identical with the external form of these conductive poles 150 (but not illustrating) with drawing, the material of these electric conductors 130 can be identical with the material of these conductive poles 150 simultaneously.
In first embodiment, chip stack package structure 100 also comprises adhesion coating 160, primer layer 170 and a plurality of soldered balls 180.Adhesion coating 160 is disposed between first chip 120 and second chip 140, and the function of adhesion coating 160 is to allow second chip 140 be securely bonded on first chip 120.In addition, primer layer 170 coats these electric conductors 130 and these conductive poles 150 at least, and in first embodiment, primer layer 170 more can coat first chip 120.Primer layer 170 is in order to protect these electric conductors 130 and these conductive poles 150; and produce when chip stack package structure 100 running when hot, between the substrate 110 that primer layer 170 available buffers are heated and first chip 120 that is heated and the phenomenon of do not match (mismatch) of the thermal strain (thermal strain) that is produced between the substrate 110 that is heated and second chip 140 that is heated.
These soldered balls 180 are disposed on the second surface 116 with respect to first surface 112 of substrate 110, in order to the electronic installation (not illustrating) that electrically connects other.These soldered balls 180 of first embodiment can arranged in array mode, and (ball grid array, BGA) signal of type is exported into the interface so that ball grid array to be provided.What deserves to be explained is, these soldered balls 180 also can be replaced by a plurality of conduction stitch (conductive pin) or a plurality of conduction suspension column (conductive column), so that pin grid array (pin gridarray to be provided respectively, PGA) type or column gate array (column grid array, CGA) signal of type is exported into the interface, but the back both do not represent with drawing.
Second embodiment
Fig. 2 A illustrates the generalized section of a kind of chip stack package structure of second embodiment of the invention, and the chip that Fig. 2 B illustrates Fig. 2 A forms the schematic diagram of orthographic projection on substrate.Please refer to Figure 1A, Fig. 2 A and Fig. 2 B, the main difference part of the chip stack package structure 200 of second embodiment and the chip stack package structure 100 of first embodiment is that the chip stack package structure 200 of second embodiment comprises first chip 220, second chip 240 and the 3rd chip 260.
Offer a piece of advice it, to small part first chip 220 be between second chip 240 and substrate 210, and first chip 220 formed first orthographic projection P220 on the first surface 212 of substrate 210 is overlapped at least with second chip 240 formed second orthographic projection P240 on first surface 212.In addition, to small part second chip 240 be between the 3rd chip 260 and substrate 210, and the 3rd chip 260 formed the 3rd orthographic projection P260 on first surface 212 is overlapped at least with the second orthographic projection P240.In a second embodiment, the first orthographic projection P220 is positioned at the second orthographic projection P240 inside, and the second orthographic projection P240 is positioned at the 3rd orthographic projection P260 inside.Yet, the designer can change the relative position of first chip 220, second chip 240 and the 3rd chip 260 according to its design requirement, as long as the first orthographic projection P220 is overlapped at least with the second orthographic projection P240, and the 3rd orthographic projection P260 overlaps with the second orthographic projection P240 to get final product at least.
Among second embodiment, these first conductive poles 250 are disposed at and are electrically connected between the first surface 212 of second chip 240 and substrate 210, and these second conductive poles 270 are disposed at and are electrically connected between the first surface 212 of the 3rd chip 260 and substrate 210, and these electric conductors 230 are disposed at and are electrically connected between first chip 220 and the first surface 212.In addition, these first conductive poles 250 are same as the description of first embodiment for conductive pole 150 (seeing Figure 1A) with external form, material and the function class of these second conductive poles 270, so repeat no more in this.The external form of these electric conductors 230, material and function class are same as the description of first embodiment for electric conductor 130 (seeing Figure 1A), so also repeat no more in this.
The 3rd embodiment
Fig. 3 A illustrates the generalized section of a kind of chip stack package structure of third embodiment of the invention, and the chip that Fig. 3 B illustrates Fig. 3 A forms the schematic diagram of orthographic projection on substrate.Please refer to Fig. 2 A, Fig. 3 A and Fig. 3 B, the main difference part of the chip stack package structure 300 of the 3rd embodiment and the chip stack package structure 200 of second embodiment is that the stack manner of first chip 320, second chip 340 and the 3rd chip 360 of the chip stack package structure 300 of the 3rd embodiment is different.
Offer a piece of advice it, to small part first chip 320 be between second chip 340 and substrate 310, and first chip 320 formed first orthographic projection P320 on the first surface 312 of substrate 310 is overlapped at least with second chip 340 formed second orthographic projection P340 on first surface 312.In addition, to small part first chip 320 be between the 3rd chip 360 and substrate 310, and the first orthographic projection P320 is overlapped at least with the 3rd chip 360 formed the 3rd orthographic projection P360 on the first surface 312 of substrate 310.
These electric conductors 330 of part are disposed at and are electrically connected between first chip 320 and second chip 340, and these electric conductors 330 of another part are disposed at and are electrically connected between first chip 320 and the 3rd chip 360.In addition, these first conductive poles 350 are disposed at and are electrically connected between the first surface 312 of second chip 340 and substrate 310, and these second conductive poles 370 are disposed at and are electrically connected between the 3rd chip 360 and the first surface 312.In addition, these first conductive poles 350 are same as the description of first embodiment for conductive pole 150 (seeing Figure 1A) with external form, material and the function class of these second conductive poles 370, so repeat no more in this.The external form of these electric conductors 230, material and function class are same as the description of first embodiment for electric conductor 130 (seeing Figure 1A), so also repeat no more at this.
Fig. 3 C illustrates the generalized section of the another kind of chip stack package structure of third embodiment of the invention, and the chip that Fig. 3 D illustrates Fig. 3 C forms the schematic diagram of orthographic projection on substrate.Please refer to Fig. 3 C and Fig. 3 D, chip stack package structure 300 ' is that with the main difference part of chip stack package structure 300 chip stack package structure 300 ' does not have the 3rd chip 360 (seeing Fig. 3 A).It must be emphasized that second chip 340 ' can be gone up the area of the formed first orthographic projection P320 ' less than first chip 320 ' at the first surface 312 ' of substrate 310 ' at the area of first surface 312 ' the last formed second orthographic projection P340 ' of substrate 310 '.
The 4th embodiment
Fig. 4 A illustrates the generalized section of a kind of chip stack package structure of fourth embodiment of the invention, and the chip that Fig. 4 B illustrates Fig. 4 A forms the schematic diagram of orthographic projection on substrate.Please refer to Fig. 2 A, Fig. 4 A and Fig. 4 B, the main difference part of the chip stack package structure 400 of the 4th embodiment and the chip stack package structure 200 of second embodiment is that the stack manner of first chip 420, second chip 440 and the 3rd chip 460 of the chip stack package structure 400 of the 4th embodiment is different.
Offer a piece of advice it, first chip 420 and second chip 440 are between the 3rd chip 460 and substrate 410, and the 3rd chip 460 formed the 3rd orthographic projection P460 on the first surface 412 of substrate 410 is overlapped at the formed second orthographic projection P420 on first surface 412 of the formed first orthographic projection P420 and second chip 440 on the first surface 412 at least with first chip 420 respectively.In the 4th embodiment, the first orthographic projection P420 and the second orthographic projection P440 lay respectively at the 3rd orthographic projection P460 inside.Yet, the designer can change the relative position of first chip 420, second chip 440 and the 3rd chip 460 according to its design requirement, as long as the first orthographic projection P420 is overlapped at least with the 3rd orthographic projection P460, and the second orthographic projection P440 overlaps with the 3rd orthographic projection P460 to get final product at least.
Among the 4th embodiment, these first electric conductors 430 are disposed at and are electrically connected between the first surface 412 of first chip 420 and substrate 410, and these second electric conductors 450 are disposed at and are electrically connected between second chip 440 and the first surface 412, and these conductive poles 470 are disposed at and are electrically connected between the 3rd chip 460 and the first surface 412.In addition, these first electric conductors 430 are same as the description of first embodiment for electric conductor 130 (seeing Figure 1A) with external form, material and the function class of these second electric conductors 450, so repeat no more in this.The external form of these conductive poles 470, material and function class are same as the description of first embodiment for conductive pole 150 (seeing Figure 1A), so also repeat no more in this.
In sum, chip stack package structure of the present invention has following advantage at least:
One, since these chips that chip stack package structure of the present invention had one of them is to be electrically connected to substrate by these conductive poles at least, and the occupied space of each conductive pole is less, so each connection pad of this chip is corresponding and the contacted area of each conductive pole can be less, and the spacing of adjacent these connection pads can be less.Therefore, compare with the chip stack package structure of prior art, this chip of chip stack package structure of the present invention is under the situation of the fixed amount of these connection pads, and the volume of this chip can be less, and then makes that the volume of chip stack package structure of the present invention can be less.
Two, because the substrate of chip stack package structure of the present invention can have the depression of at least one ccontaining chip, so the volume of chip stack package structure of the present invention can be littler.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those of ordinary skill under any in the technical field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (43)
1. chip stack package structure comprises:
Substrate has first surface;
First chip is disposed on this first surface and formation first orthographic projection on this first surface;
A plurality of electric conductors are disposed at and are electrically connected between this first chip and this first surface;
Second chip is disposed on this first surface and forms second orthographic projection on this first surface, wherein to this first chip of small part be between this second chip and this substrate, and this first orthographic projection and this second orthographic projection are overlapped at least; And
A plurality of conductive poles are disposed at and are electrically connected between this second chip and this first surface.
2. chip stack package structure as claimed in claim 1, wherein this substrate also has a depression, and it is positioned on this first surface, and wherein this first chip is positioned at this recess.
3. chip stack package structure as claimed in claim 1, wherein the material of these conductive poles be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
4. chip stack package structure as claimed in claim 1, wherein these electric conductors are conductive projection.
5. chip stack package structure as claimed in claim 1, wherein the external form of these electric conductors is identical with the external form of these conductive poles.
6. chip stack package structure as claimed in claim 5, wherein the material of these electric conductors be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
7. chip stack package structure as claimed in claim 1 also comprises adhesion coating, and it is disposed between this first chip and this second chip.
8. chip stack package structure as claimed in claim 1 also comprises primer layer, and it coats these electric conductors and these conductive poles at least.
9. chip stack package structure as claimed in claim 1 also comprises a plurality of soldered balls, and it is disposed on the second surface with respect to this first surface of this substrate.
10. chip stack package structure comprises:
Substrate has first surface;
First chip is disposed on this first surface and formation first orthographic projection on this first surface;
A plurality of electric conductors are disposed at and are electrically connected between this first chip and this first surface;
Second chip is disposed on this first surface and forms second orthographic projection on this first surface, wherein to this first chip of small part be between this second chip and this substrate, and this first orthographic projection and this second orthographic projection are overlapped at least;
A plurality of first conductive poles are disposed at and are electrically connected between this second chip and this first surface;
The 3rd chip is disposed on this first surface and forms the 3rd orthographic projection on this first surface, wherein to this second chip of small part be between the 3rd chip and this substrate, and this second orthographic projection and the 3rd orthographic projection are overlapped at least; And
A plurality of second conductive poles are disposed at and are electrically connected between the 3rd chip and this first surface.
11. chip stack package structure as claimed in claim 10, wherein this substrate also has a depression, and it is positioned on this first surface, and wherein this first chip is positioned at this recess.
12. chip stack package structure as claimed in claim 10, wherein the material of these first conductive poles be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
13. chip stack package structure as claimed in claim 10, wherein the material of these second conductive poles be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
14. chip stack package structure as claimed in claim 10, wherein these electric conductors are conductive projection.
15. chip stack package structure as claimed in claim 10, wherein the external form of these electric conductors is identical with the external form of these first conductive poles or these second conductive poles.
16. chip stack package structure as claimed in claim 15, wherein the material of these electric conductors be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
17. chip stack package structure as claimed in claim 10 also comprises first adhesion coating, it is disposed between this first chip and this second chip.
18. chip stack package structure as claimed in claim 10 also comprises second adhesion coating, it is disposed between this second chip and the 3rd chip.
19. chip stack package structure as claimed in claim 10 also comprises primer layer, it coats these electric conductors, these first conductive poles and these second conductive poles at least.
20. chip stack package structure as claimed in claim 10 also comprises a plurality of soldered balls, it is disposed on the second surface with respect to this first surface of this substrate.
21. a chip stack package structure comprises:
Substrate has first surface;
First chip is disposed on this first surface and formation first orthographic projection on this first surface;
Second chip is disposed on this first surface and forms second orthographic projection on this first surface, and wherein this first chip of part is between this second chip and this substrate, and this first orthographic projection and this second orthographic projection are overlapped at least;
A plurality of first electric conductors are disposed at and are electrically connected between this first chip and this second chip; And
A plurality of first conductive poles are disposed at and are electrically connected between this second chip and this first surface.
22. as claim 21 described chip stack package structure, wherein this substrate has more a depression, it is positioned on this first surface, and wherein this first chip is positioned at this recess.
23. as claim 21 described chip stack package structure, wherein the material of these first conductive poles be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
24. chip stack package structure as claimed in claim 21, wherein these first electric conductors are conductive projection.
25. chip stack package structure as claimed in claim 21, wherein the external form of these first electric conductors is identical with the external form of these first conductive poles.
26. chip stack package structure as claimed in claim 25, wherein the material of these first electric conductors be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
27. chip stack package structure as claimed in claim 21 also comprises adhesion coating, it is disposed between this first chip and this substrate.
28. chip stack package structure as claimed in claim 21 also comprises primer layer, it coats these first electric conductors and these first conductive poles at least.
29. chip stack package structure as claimed in claim 21 also comprises a plurality of soldered balls, it is disposed on the second surface with respect to this first surface of this substrate.
30. chip stack package structure as claimed in claim 21 also comprises:
The 3rd chip is disposed on this first surface and forms the 3rd orthographic projection on this first surface, and wherein this first chip of part is between the 3rd chip and this substrate, and this first orthographic projection and the 3rd orthographic projection are overlapped at least;
A plurality of second electric conductors are disposed at and are electrically connected between this first chip and the 3rd chip; And
A plurality of second conductive poles are disposed at and are electrically connected between the 3rd chip and this first surface.
31. chip stack package structure as claimed in claim 30, wherein the material of these second conductive poles be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
32. a chip stack package structure comprises:
Substrate has first surface;
First chip is disposed on this first surface and formation first orthographic projection on this first surface;
A plurality of first electric conductors are disposed at and are electrically connected between this first chip and this first surface;
Second chip is disposed on this first surface and formation second orthographic projection on this first surface;
A plurality of second electric conductors are disposed at and are electrically connected between this second chip and this first surface;
The 3rd chip, be disposed on this first surface and formation the 3rd orthographic projection on this first surface, wherein this first chip and this second chip are between the 3rd chip and this substrate, and the 3rd orthographic projection is overlapped at least with this first orthographic projection and this second orthographic projection respectively; And
A plurality of conductive poles are disposed at and are electrically connected between the 3rd chip and this first surface.
33. chip stack package structure as claimed in claim 32, wherein this substrate has more two depressions, and it is positioned on this first surface, and wherein this first chip and this second chip lay respectively at these recess.
34. chip stack package structure as claimed in claim 32, wherein the material of these conductive poles be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
35. chip stack package structure as claimed in claim 32, wherein these first electric conductors are conductive projection.
36. chip stack package structure as claimed in claim 32, wherein the external form of these first electric conductors is identical with the external form of these conductive poles.
37. chip stack package structure as claimed in claim 36, wherein the material of these first electric conductors be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
38. chip stack package structure as claimed in claim 32, wherein these second electric conductors are conductive projection.
39. chip stack package structure as claimed in claim 32, wherein the external form of these second electric conductors is identical with the external form of these conductive poles.
40. chip stack package structure as claimed in claim 39, wherein the material of these second electric conductors be selected from copper, aluminium, gold, platinum, titanium, these combination and these alloy formed a kind of material in the group.
41. chip stack package structure as claimed in claim 32 also comprises adhesion coating, it is disposed between the 3rd chip and this first chip and between the 3rd chip and this second chip.
42. chip stack package structure as claimed in claim 32 also comprises primer layer, it coats these first electric conductors, these second electric conductors and these conductive poles at least.
43. chip stack package structure as claimed in claim 32 also comprises a plurality of soldered balls, it is disposed on the second surface with respect to this first surface of this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100040719A CN101232004A (en) | 2007-01-23 | 2007-01-23 | Chip stack package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100040719A CN101232004A (en) | 2007-01-23 | 2007-01-23 | Chip stack package structure |
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| Publication Number | Publication Date |
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| CN101232004A true CN101232004A (en) | 2008-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100040719A Pending CN101232004A (en) | 2007-01-23 | 2007-01-23 | Chip stack package structure |
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| CN (1) | CN101232004A (en) |
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| CN105374805A (en) * | 2014-08-29 | 2016-03-02 | 展讯通信（上海）有限公司 | Multi-chip packaging structure |
| CN106409800A (en) * | 2016-11-15 | 2017-02-15 | 广东美的制冷设备有限公司 | Intelligent power module and manufacturing method thereof |
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