CN102593110B - Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method - Google Patents
Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method Download PDFInfo
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- CN102593110B CN102593110B CN201210012062.5A CN201210012062A CN102593110B CN 102593110 B CN102593110 B CN 102593110B CN 201210012062 A CN201210012062 A CN 201210012062A CN 102593110 B CN102593110 B CN 102593110B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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Abstract
The invention discloses a laminated inverted chip packaging structure of ultra-fine spacing welding plates and a preparation method thereof. According to the embodiment of the invention, the laminated inverted chip packaging structure comprises a substrate, a plurality of vertically-stacked chips and a plurality of conducting columns, wherein a plurality of welding plates are arranged on the substrate; one welding plate is arranged on each chip; and the conducting columns are arranged between the chips and the substrate; a part of the conducting columns are vertically stacked together; and the welding plates on the substrate and the welding plates on the chips are electrically connected through the conducting columns. Bottom filling materials are filled in gaps among the chips and gaps between the chips and the substrate and cover solder on each layer and the conducting columns. With the adoption of the laminated inverted chip packaging structure of the ultra-fine spacing welding plates disclosed by the embodiment of the invention, the requirements on the ultra-fine spacing welding plates on the vertically-stacked chips can be satisfied.
Description
Technical field
The present invention relates to a kind of lamination flip chip packaging structure and manufacture method, particularly relate to a kind of lamination flip-chip small size thin encapsulation structure of ultra fine-pitch pad and adopt the manufacture method of underfill.
Background technology
As shown in Figure 1, traditional comprises in the laminated packaging structure of two-layer flip-chip, interconnection between chip bonding pad with substrate pads normally the second chip 2 (chip that position is top, distance substrate is far away) is connected with substrate 100 pad by larger spherical solder bump, and the first chip 1 (position chip on the lower) is connected with substrate pads by less spherical solder bump.
In order to overcome in the laminated packaging structure of traditional two-layer flip-chip, solder bump cannot be applicable to the problem of ultra fine-pitch pad, there is conductive pole interconnection structure in recent years, can use this conductive pole interconnection structure on the first chip 1, or the first chip 1 and the second chip 2 use conductive pole interconnection structure simultaneously.
Be used on the first chip 1 iff by the interconnection of this novel conductive pole, and when the second chip 2 still uses spherical solder bump interconnect, the ultra fine-pitch pad being less than 150um cannot be applied to.
If when conductive pole interconnection being simultaneously used on the first chip 1 and the second chip 2, there are problems.Because prior art generally can only accomplish the conductive pole of about 70um height, after deducting the thickness of chip surface protection insulating barrier and substrate surface insulating barrier, the gap d between chip and substrate will be less than 50um (see Fig. 3).But the space (d2) simultaneously at least needing to retain 10um between the back side of the first chip 1 and the surface of the second chip 2 is for being connected or the filling of underfill.The existing chip thinning technology that can realize volume production is general the thinnest is 30um thickness, and therefore the thickness Tc of lower layer chip 1 has 30um at least, causes the gap d 1 between lower layer chip 1 and substrate 100 remaining less than 10um.This structure is difficult to realize at present.
Summary of the invention
The object of the present invention is to provide a kind of flip-chip laminated packaging structure of ultra fine-pitch pad, the requirement of the ultra fine-pitch pad of upper and lower lamination flip-chip can be met simultaneously.
To achieve these goals, according to embodiments of the invention, provide a kind of lamination flip chip packaging structure, wherein, described lamination flip chip packaging structure comprises: substrate, substrate is provided with multiple pad; Multiple chips of stacked on top, each chip is provided with pad; Multiple conductive pole, be arranged between the pad of chip and substrate, be electrically connected by described multiple conductive pole between substrate pads with chip bonding pad, together, the chip of the superiors is electrically connected with substrate by multilayer conductive post a part of stacked on top in described multiple conductive pole; Underfill, is filled in the gap between each chip.
The number of plies of the conductive pole that chip bonding pad is arranged is more than or equal to the number of plies being positioned at the conductive pole that the chip bonding pad of this beneath chips is arranged.
Undermost chip is electrically connected with substrate by one deck conductive pole.
Each layer chip all includes the pad that spacing is less than 150um.
Described multiple conductive pole comprises the first conductive pole, the second conductive pole and the 3rd conductive pole, and the second conductive pole is stacked on above the first conductive pole, and the 3rd conductive pole is arranged on undermost chip.
Between first conductive pole and the second conductive pole and the first conductive pole and the 3rd be connected by solder between conductive pole with substrate pads, solder comprises the first solder, the second solder and the 3rd solder.
Substrate pads is connected with one end of the first conductive pole by the first solder, and substrate pads is connected with the 3rd conductive pole one end by the 3rd solder, is connected between the first conductive pole with the second conductive pole by the second solder.
The fusing point of the first solder is higher more than 50 DEG C than the fusing point of the second solder and the 3rd solder.
The material of the first solder and the second solder and the 3rd solder is lead-free solder.
This encapsulating structure for each layer conductive pole between to connect and in all solders of being connected with substrate pads for conductive pole, the fusing point of the solder set by the conductive pole lower end be directly connected with each layer chip is minimum.
Underfill is also filled in the gap between chip and substrate, and coated each layer solder and conductive pole.
The material of the first conductive pole and the second conductive pole and the 3rd conductive pole is all copper.
UBM layer is provided with between the pad of chip and a part of conductive pole.
According to a further aspect in the invention, additionally provide a kind of method manufacturing lamination flip chip packaging structure as above, wherein, described method comprises: be connected to after on substrate by Reflow Soldering by the carrier presetting the first conductive pole, be separated the first conductive pole and carrier, first conductive pole is connected by the first solder retain on the substrate pads, by preset the 3rd conductive pole the first chip attachment to substrate on corresponding pad, by on the first corresponding to substrate for the second chip attachment presetting the second conductive pole conductive pole, again make chip and substrate be formed after Reflow Soldering to interconnect, then be filled in the gap between chip and chip and the gap between chip and substrate with underfill.
Wherein, arrange protective layer on the surface of carrier, before separation first conductive pole and carrier, the first conductive pole is plated on the protective layer of carrier.
Wherein, the adhesion between the first conductive pole and the first solder and the adhesion between the first solder and substrate pads are greater than the adhesion between the first conductive pole and the protective layer of carrier.
Use the flip-chip laminated packaging structure of ultra fine-pitch pad according to an embodiment of the invention, the requirement of the ultra fine-pitch pad of upper and lower lamination flip-chip can be met simultaneously.
Accompanying drawing explanation
By below in conjunction with exemplarily illustrating the description that the accompanying drawing of an example carries out, above and other object of the present invention and feature will become apparent, wherein:
Fig. 1 is the flip chip structure schematic diagram that traditional layers of chips all uses spherical solder bump;
Fig. 2 is that second chip on upper strata uses spherical solder bump, and the first chip of lower floor uses conductive pillar structure schematic diagram;
Fig. 3 is the structural representation that upper and lower layers of chips all uses single layer of conductive post;
Fig. 4 is the schematic diagram of laminated packaging structure according to an embodiment of the invention;
Fig. 5 is the schematic diagram mounted by the carrier being prefixed the first conductive pole on substrate;
Fig. 6 is that the carrier being prefixed the first conductive pole forms the schematic diagram be connected with substrate after first time refluxes;
Fig. 7 is the schematic diagram be separated with the first conductive pole by carrier, and wherein, the first conductive pole stays on the substrate pads;
Fig. 8 is after being separated with the first conductive pole by carrier, the schematic diagram at the first conductive pole top of substrate side;
Fig. 9 is after being separated with the first conductive pole by carrier, the schematic diagram of carrier side;
Figure 10 be by the first chip attachment on the substrate with the first conductive pole corresponding pad locations on schematic diagram;
Figure 11 is by the schematic diagram on the first conductive pole position corresponding in the second chip attachment to substrate;
Figure 12 is the interconnection schematic diagram of the first chip and substrate and the second chip and the substrate formed after second time backflow;
Figure 13 for underfill is filled into the second chip, the schematic diagram in the gap between the first chip and substrate.
Embodiment
The spatial relationship term such as " in ... below ", " lower floor ", " in ... top ", " upper strata " can be used such as in the present invention easily to describe the relation of the element of shown in figure or feature and other elements or feature.Should be appreciated that except the orientation described in accompanying drawing, spatial relationship term is also intended to comprise device different azimuth in use or operation.Such as, if the device upset in accompanying drawing, be then described as be in other elements or feature " below " or " under " the orientation of element will be positioned in " top " of other elements or feature subsequently.Therefore, exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.Device can be positioned at other orientation (90-degree rotation or in other orientation), and then spatial relation description used herein symbol should be interpreted accordingly.
Below, embodiments of the invention are described in detail with reference to accompanying drawing.
Fig. 4 is laminated packaging structure schematic diagram according to an embodiment of the invention.As shown in Figure 4, laminated packaging structure comprises according to an embodiment of the invention: substrate 100, and substrate 100 is provided with multiple pad; Two chips 1,2 of stacked on top (are not limited to two, the upper and lower stacking chip of more than three can be had according to encapsulating structure of the present invention, the first chip, the second chip, the 3rd chip etc. can be called successively from top to bottom), the first chip 1 and the second chip 2 are provided with multiple pad; Conductive pole, is arranged between the first chip 1 and substrate 100 and between the second chip 2 and substrate 100, is electrically connected between substrate pads with chip bonding pad by described conductive pole.
Further, according to one embodiment of present invention, first chip 1 to the second chip 2 is closer to substrate 100 (also the first chip 1 can be described as in the below of the second chip 2), one deck the 3rd conductive pole 5 is only provided with between first chip 1 and substrate 100, and the lower of the second chip 2 can be provided with two-layer conductive pole, be respectively the first conductive pole 3 and the second conductive pole 4.
If this laminated packaging structure comprises more chip, position chip is more by the top connected with substrate by more multi-layered conductive pole.According to embodiments of the invention, at least the chip of the superiors is electrically connected with substrate by multilayer conductive post.The number of plies of the conductive pole that the pad of any layer chip is arranged is more than or equal to the number of plies of the conductive pole of the chip setting being positioned at this layer of beneath chips.
Conductive pole cross sectional shape can be square or circular, and has no special requirements.
First chip 1 and the second chip 2 all include the ultra fine-pitch pad that spacing is less than 150um.Substrate pads is connected with first conductive pole 3 one end by the first solder 6, and first conductive pole 3 other end is connected with the second conductive pole 4 by the second solder 7, and second conductive pole 4 other end is connected with the pad of the second chip 2.
Substrate pads is connected with the 3rd conductive pole 5 one end by the 3rd solder 8, and the 3rd conductive pole 5 other end is connected with the pad of the first chip 1.
Underfill 12 has been filled in the gap between chip and substrate 100, and coated first solder 6, first conductive pole 3, second solder 7, second conductive pole the 4, three solder the 8, three conductive pole 5.
In addition, soldered ball can be distributed with in the lower surface of substrate, to be electrically connected with other components and parts.
The material of the first conductive pole material 3 and the second conductive pole 4 and the 3rd conductive pole 5 all can be Cu.
First and second and the 3rd solder material all can be unleaded (that is, lead content must reduce to the level lower than 1000ppm).
UBM layer 10 (salient point bottom metal layer, under bump metal) is had between the pad of the second chip 2 and/or the first chip 1 and partially conductive post.UBM layer can ensure the adhibit quality of flange and pad and prevent intermetallic phase counterdiffusion.
The fusing point of the first solder 6 can than high 50 DEG C of fusing point of the second solder 4 and the 3rd solder 8 or more.
Fig. 5-Figure 13 shows the manufacture method of the flip-chip laminated packaging structure of ultra fine-pitch pad according to an embodiment of the invention.
Fig. 5 is the schematic diagram mounted by the carrier being prefixed the first conductive pole on substrate; Fig. 6 is that the carrier being prefixed the first conductive pole forms the schematic diagram be connected with substrate after first time refluxes; Fig. 7 is the schematic diagram be separated with the first conductive pole by carrier, and wherein, the first conductive pole stays on the substrate pads.
As shown in Figure 5, the conductive pole carrier 9 presetting the first conductive pole 3 and the first solder 6 is mounted on substrate.The flipchip-bumped manufacture craft of existing maturation can be implemented on carrier 9 and successively plates conductive pole and solder; specifically; pre-set on the surface of carrier 9 and do not produce the protective layer of metallurgical binding with metal; after the polymeric coating layers such as coating polyimide; carry out flipchip-bumped manufacture craft again, can make to maintain extremely low adhesion between the first conductive pole 3 and the protective layer of carrier 9.The firmly metallurgical binding between the first solder 6 and the first conductive pole 3 is formed again by techniques such as Reflow Solderings.
Then, as shown in Figure 6, after again refluxing, make to form solder with the carrier 9 of the first solder 6 with substrate 100 with the first conductive pole 3 and be connected.
As shown in Figure 7, carrier of separating 9 and the first conductive pole 3.Specifically; after reflow soldering process; between first conductive pole 3 and the first solder 6; and first between solder 6 and substrate pads; all define firmly metallurgical binding; adhesion between them is far longer than the adhesion between the first conductive pole 3 and the protective layer of carrier 9, is so just easy to realize the first conductive pole 3 and being separated between carrier 9, and the first conductive pole 3 is retained on the substrate pads.Fig. 8 is after being separated with the first conductive pole 3 by carrier, the schematic diagram at the first conductive pole 3 top of substrate side, and Fig. 9 is after being separated with the first conductive pole 3 by carrier 9, the schematic diagram of carrier 9 side.Fig. 8 and Fig. 9 is only an example, and the distribution of the first conductive pole 3 is not limited to the shape shown in Fig. 8 and Fig. 9.
Figure 10 be by the first chip attachment on the substrate with the first conductive pole corresponding pad locations on schematic diagram; Figure 11 is by the schematic diagram on the first conductive pole position corresponding in the second chip attachment to substrate; Figure 12 is the interconnection schematic diagram of the first chip and substrate and the second chip and the substrate formed after second time backflow; Figure 13 for underfill is filled into the second chip, the schematic diagram in the gap between the first chip and substrate.
As shown in figures 10-13, the first chip 1 being prefixed the 3rd conductive pole 5 is mounted on the substrate with the first conductive pole 3.Then mount on the substrate with the first conductive pole 3 by the second chip 2 being prefixed the second conductive pole 4, attachment process should note the conductive pole that aligns.After Reflow Soldering, the pad of chip 1, chip 2 and the pad of substrate are formed and interconnect.
Cause the first conductive pole 3 crooked in order to avoid the first solder 6 melts in the process of this Reflow Soldering and can not align with the second conductive pole 4, may need to make the fusing point of the first solder 6 than high 50 DEG C of fusing point of the second solder 4 and the 3rd solder 8 or more.
Finally be filled in the gap between each chip with underfill, be also filled in the gap between chip and substrate, and coated first solder 6, first conductive pole 3, second solder 7, second conductive pole 4,3rd solder the 8, three conductive pole 5, thus final molding.
If need the laminated packaging structure of making three layers or more multi-layered chip, then on substrate, need the conductive pole of stacked multilayer, then place the first chip, the second chip, the 3rd chip, the 4th chip successively, the rest may be inferred, finally fills underfill material.This wherein will experience multiple tracks reflux technique, knows according to foregoing reason, and the fusing point of solder set on the conductive pole be directly connected with each layer chip is minimum in all solders, because they are in last reflow process.
In addition, soldered ball can be distributed with in the lower surface of substrate, to be electrically connected with other components and parts.
Although described exemplary embodiment of the present invention in detail above, there is common practise person in the technical field of the invention not departing from spirit and scope of the present utility model, various amendments, retouching and modification can have been made to embodiments of the invention.But should be appreciated that In the view of those skilled in the art, these amendments, retouching and modification will fall in the spirit and scope of the exemplary embodiment of the present invention that claim limits.
Finally, unless to point out here or in addition and the obvious contradiction of context, otherwise methodical step described herein can perform with the order of any appropriate.
Claims (14)
1. a lamination flip chip packaging structure, wherein, described lamination flip chip packaging structure comprises:
Substrate, substrate is provided with multiple pad;
Multiple chips of stacked on top, each chip is provided with pad, and each layer chip all includes the pad that spacing is less than 150um;
Multiple conductive pole, be arranged between the pad of chip and substrate, be electrically connected by described multiple conductive pole between substrate pads with chip bonding pad, together, the chip of the superiors is electrically connected with substrate by multilayer conductive post a part of stacked on top in described multiple conductive pole;
Underfill, is filled in the gap between each chip,
Wherein, connected by solder between mutually stacking conductive pole, this encapsulating structure for each layer conductive pole between to connect and in all solders of being connected with substrate pads for conductive pole, the fusing point of the solder set by the conductive pole lower end be directly connected with each layer chip is minimum.
2. lamination flip chip packaging structure according to claim 1, wherein,
The number of plies of the conductive pole that chip bonding pad is arranged is more than or equal to the number of plies being positioned at the conductive pole that the chip bonding pad of this beneath chips is arranged.
3. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Undermost chip is electrically connected with substrate by one deck conductive pole.
4. lamination flip chip packaging structure according to claim 1 and 2, described multiple conductive pole comprises the first conductive pole, the second conductive pole and the 3rd conductive pole, second conductive pole is stacked on above the first conductive pole, and the 3rd conductive pole is arranged on undermost chip.
5. lamination flip chip packaging structure according to claim 4, wherein,
Between first conductive pole and the second conductive pole and the first conductive pole and the 3rd be connected by solder between conductive pole with substrate pads, solder comprises the first solder, the second solder and the 3rd solder.
6. lamination flip chip packaging structure according to claim 5, wherein,
Substrate pads is connected with one end of the first conductive pole by the first solder, and substrate pads is connected with the 3rd conductive pole one end by the 3rd solder, is connected between the first conductive pole with the second conductive pole by the second solder.
7. the lamination flip chip packaging structure according to claim 5 or 6, wherein,
The fusing point of the first solder is higher more than 50 DEG C than the fusing point of the second solder and the 3rd solder.
8. the lamination flip chip packaging structure according to claim 5 or 6, wherein,
The material of the first solder and the second solder and the 3rd solder is lead-free solder.
9. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Underfill is also filled in the gap between chip and substrate, and coated each layer solder and conductive pole.
10. lamination flip chip packaging structure according to claim 1 and 2, wherein,
The material of the first conductive pole and the second conductive pole and the 3rd conductive pole is all copper.
11. lamination flip chip packaging structures according to claim 1 and 2, wherein,
UBM layer is provided with between the pad of chip and a part of conductive pole.
The method of the lamination flip chip packaging structure of 12. 1 kinds of manufactures according to any one of claim 1-11, wherein, described method comprises:
The carrier presetting the first conductive pole is connected to after on substrate by Reflow Soldering, is separated the first conductive pole and carrier, the first conductive pole is connected by the first solder and retains on the substrate pads,
The first chip attachment presetting the 3rd conductive pole on corresponding pad, by presetting on first conductive pole of the second chip attachment correspondence to substrate of the second conductive pole, again being made chip and substrate be formed and interconnecting to substrate after Reflow Soldering,
Then be filled in the gap between chip and chip and the gap between chip and substrate with underfill.
13. methods according to claim 12, wherein, arrange protective layer on the surface of carrier, and before separation first conductive pole and carrier, the first conductive pole is plated on the protective layer of carrier.
14. methods according to claim 13, wherein, the adhesion between the first conductive pole and the first solder and the adhesion between the first solder and substrate pads are greater than the adhesion between the first conductive pole and the protective layer of carrier.
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| CN201210012062.5A CN102593110B (en) | 2012-01-05 | 2012-01-05 | Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method |
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| CN201210012062.5A CN102593110B (en) | 2012-01-05 | 2012-01-05 | Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method |
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