CN102593110B - Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method - Google Patents

Abstract

The invention discloses a laminated inverted chip packaging structure of ultra-fine spacing welding plates and a preparation method thereof. According to the embodiment of the invention, the laminated inverted chip packaging structure comprises a substrate, a plurality of vertically-stacked chips and a plurality of conducting columns, wherein a plurality of welding plates are arranged on the substrate; one welding plate is arranged on each chip; and the conducting columns are arranged between the chips and the substrate; a part of the conducting columns are vertically stacked together; and the welding plates on the substrate and the welding plates on the chips are electrically connected through the conducting columns. Bottom filling materials are filled in gaps among the chips and gaps between the chips and the substrate and cover solder on each layer and the conducting columns. With the adoption of the laminated inverted chip packaging structure of the ultra-fine spacing welding plates disclosed by the embodiment of the invention, the requirements on the ultra-fine spacing welding plates on the vertically-stacked chips can be satisfied.

Description

Stacked flip-chip packaging structure of ultra-fine pitch pads and underfill manufacturing method

technical field

The invention relates to a stacked flip-chip packaging structure and a manufacturing method, in particular to a stacked flip-chip small-sized thin packaging structure with ultra-fine-pitch pads and a manufacturing method using bottom filling glue.

Background technique

As shown in Figure 1, in a traditional stacked package structure containing two layers of flip chips, the interconnection between the chip pad and the substrate pad is usually the second chip 2 (the chip that is positioned higher and farther away from the substrate) The larger ball-shaped solder bumps are connected to the pads of the substrate 100 , and the first chip 1 (the lower chip) is connected to the pads of the substrate through smaller ball-shaped solder bumps.

In order to overcome the problem that solder bumps cannot be applied to ultra-fine-pitch pads in the traditional two-layer flip-chip stacked packaging structure, a conductive pillar interconnection structure has emerged in recent years, which can be used on the first chip 1. The pillar interconnection structure, or the first chip 1 and the second chip 2 both use the conductive pillar interconnection structure.

If this new type of conductive column interconnection is only used on the first chip 1 and the second chip 2 is still interconnected by ball-shaped solder bumps, it cannot be applied to ultra-fine pitch pads smaller than 150 um.

If the conductive pillar interconnection is used on the first chip 1 and the second chip 2 at the same time, there are many problems. Since the existing technology generally can only achieve conductive pillars with a height of about 70um, after subtracting the thickness of the protective insulating layer on the chip surface and the insulating layer on the substrate surface, the gap d between the chip and the substrate will be less than 50um (see Figure 3). But at the same time, at least 10um of space ( d2 ) needs to be reserved between the back surface of the first chip 1 and the surface of the second chip 2 for connection or filling of underfill glue. Existing chip thinning technologies that can be mass-produced generally have a minimum thickness of 30um, so the thickness Tc of the lower chip 1 is at least 30um, resulting in a gap d1 between the lower chip 1 and the substrate 100 that is less than 10um. This structure is currently difficult to implement.

Contents of the invention

The object of the present invention is to provide a flip-chip stacked packaging structure with ultra-fine-pitch pads, which can simultaneously meet the requirements of ultra-fine-pitch pads for upper and lower stacked flip-chips.

In order to achieve the above object, according to an embodiment of the present invention, a stacked flip-chip packaging structure is provided, wherein the stacked flip-chip packaging structure includes: a substrate on which a plurality of pads are arranged; stacked up and down A plurality of chips, each chip is provided with a pad; a plurality of conductive columns are arranged between the pads of the chip and the substrate, and the substrate pads and the chip pads are electrically connected through the plurality of conductive columns , some of the plurality of conductive columns are stacked up and down, and the uppermost chip is electrically connected to the substrate through the multi-layer conductive column; the bottom filling material is filled in the gap between the chips.

The number of layers of conductive pillars arranged on the chip pad is greater than or equal to the number of layers of conductive pillars arranged on the chip pad below the chip.

The bottom chip is electrically connected to the substrate through a layer of conductive pillars.

Each layer of chips includes pads with a pitch of less than 150um.

The plurality of conductive columns include a first conductive column, a second conductive column and a third conductive column, the second conductive column is stacked above the first conductive column, and the third conductive column is arranged on the chip at the bottom layer.

The connection between the first conductive column and the second conductive column, and between the first conductive column and the third conductive column and the substrate pad is connected by solder, and the solder includes the first solder, the second solder and the third solder.

The substrate pad is connected to one end of the first conductive column through the first solder, the substrate pad is connected to one end of the third conductive column through the third solder, and the first conductive column is connected to the second conductive column through the second solder.

The melting point of the first solder is higher than the melting points of the second solder and the third solder by 50° C. or more.

Materials of the first solder, the second solder and the third solder are lead-free solder.

Among all the solders used for the connection between the conductive pillars of each layer and the connection between the conductive pillars and the substrate pads in the package structure, the solder provided at the lower end of the conductive pillars directly connected with the chips of each layer has the lowest melting point.

The underfill material also fills the gap between the chip and the substrate and coats the various layers of solder and conductive pillars.

Materials of the first conductive column, the second conductive column and the third conductive column are all copper.

A UBM layer is provided between the bonding pad of the chip and a part of the conductive pillars.

According to another aspect of the present invention, there is also provided a method for manufacturing the stacked flip-chip package structure as described above, wherein the method includes: connecting the carrier pre-prepared with the first conductive pillar to the After being placed on the substrate, separate the first conductive column from the carrier, make the first conductive column remain on the substrate pad through the first solder connection, and mount the first chip with the third conductive column preset on the corresponding pad on the substrate , attach the second chip with the second conductive column preset on the corresponding first conductive column on the substrate, reflow soldering again to form interconnection between the chip and the substrate, and then fill the gap between the chip and the chip with an underfill material In the gap and the gap between the chip and the substrate.

Wherein, a protective layer is provided on the surface of the carrier, and before the first conductive pillar is separated from the carrier, the first conductive pillar is plated on the protective layer of the carrier.

Wherein, the bonding force between the first conductive pillar and the first solder and the bonding force between the first solder and the substrate pad are greater than the bonding force between the first conductive pillar and the protective layer of the carrier.

The flip-chip stacked packaging structure using the ultra-fine-pitch pads according to the embodiment of the present invention can simultaneously meet the requirements of the ultra-fine-pitch pads of the upper and lower stacked flip-chips.

Description of drawings

The above and other objects and features of the present invention will become more apparent through the following description in conjunction with the accompanying drawings exemplarily showing an example, wherein:

Fig. 1 is a schematic diagram of a flip-chip structure in which a conventional two-layer chip uses spherical solder bumps;

Fig. 2 is a schematic diagram of the structure where the second chip on the upper layer uses ball-shaped solder bumps and the first chip on the lower layer uses conductive pillars;

Figure 3 is a structural schematic diagram of a single-layer conductive column used for both the upper and lower layers of chips;

4 is a schematic diagram of a package-on-package structure according to an embodiment of the present invention;

Fig. 5 is a schematic diagram of mounting the carrier pre-installed with the first conductive column on the substrate;

6 is a schematic diagram of the connection between the carrier with the first conductive column and the substrate formed after the first reflow;

7 is a schematic diagram of separating the carrier from the first conductive column, wherein the first conductive column is left on the substrate pad;

8 is a schematic diagram of the top of the first conductive post on the substrate side after the carrier is separated from the first conductive post;

9 is a schematic diagram of one side of the carrier after the carrier is separated from the first conductive pillar;

10 is a schematic diagram of attaching the first chip to the corresponding pad position on the substrate with the first conductive column;

Fig. 11 is a schematic diagram of attaching the second chip to the corresponding position of the first conductive column on the substrate;

12 is a schematic diagram of the interconnection between the first chip and the substrate and the second chip and the substrate formed after the second reflow;

FIG. 13 is a schematic diagram of filling the gap between the second chip, the first chip and the substrate with the underfill glue.

Detailed ways

Spatially relative terms such as "beneath," "lower," "above," "upper," etc. may be used herein to readily describe an element or feature shown in the figures in relation to other elements. or feature relations. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of "above" and "beneath". The device may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a schematic diagram of a package-on-package structure according to an embodiment of the present invention. As shown in FIG. 4 , the package-on-package structure according to the embodiment of the present invention includes: a substrate 100, on which a plurality of pads are arranged; two chips 1, 2 stacked up and down (not limited to two, according to the present invention The packaging structure can have more than three chips stacked up and down, which can be called the first chip, the second chip, the third chip, etc. from bottom to top), and both the first chip 1 and the second chip 2 are set There are a plurality of bonding pads; conductive pillars are arranged between the first chip 1 and the substrate 100 and between the second chip 2 and the substrate 100, and the substrate bonding pads and the chip bonding pads are electrically connected through the conductive pillars.

Further, according to an embodiment of the present invention, the first chip 1 is closer to the substrate 100 than the second chip 2 (the first chip 1 can also be described as being below the second chip 2), and the distance between the first chip 1 and the substrate 100 is Only one layer of third conductive pillars 5 is arranged between them, while two layers of conductive pillars may be arranged below the second chip 2, which are first conductive pillars 3 and second conductive pillars 4 respectively.

If the package-on-package structure includes more chips, the chips located higher above can be connected to the substrate through more layers of conductive pillars. According to an embodiment of the present invention, at least the uppermost chip is electrically connected to the substrate through multi-layer conductive pillars. The number of layers of conductive pillars arranged on the bonding pads of any layer of chips is greater than or equal to the number of layers of conductive pillars arranged on chips below this layer of chips.

The cross-sectional shape of the conductive pillar can be square or circular, and there is no special requirement.

Both the first chip 1 and the second chip 2 include ultra-fine-pitch pads with a pitch less than 150um. The substrate pad is connected to one end of the first conductive column 3 through the first solder 6, the other end of the first conductive column 3 is connected to the second conductive column 4 through the second solder 7, and the other end of the second conductive column 4 is connected to the second chip 2. pad connection.

The substrate pad is connected to one end of the third conductive pillar 5 through the third solder 8 , and the other end of the third conductive pillar 5 is connected to the pad of the first chip 1 .

The underfill material 12 is filled into the gap between the chip and the substrate 100, and covers the first solder 6, the first conductive pillar 3, the second solder 7, the second conductive pillar 4, the third solder 8, the third conductive Column 5.

In addition, solder balls may be distributed on the bottom surface of the substrate for electrical connection with other components.

The material of the first conductive pillar material 3 , the second conductive pillar 4 and the third conductive pillar 5 can be Cu.

Both the first and second and third solder materials may be lead-free (ie, the lead content must be reduced to levels below 1000 ppm).

There is a UBM layer 10 (under bump metal) between the pads of the second chip 2 and/or the first chip 1 and some conductive pillars. The UBM layer can ensure the adhesion between the flange and the pad and prevent the interdiffusion between metals.

The melting point of the first solder 6 may be 50° C. or more higher than the melting points of the second solder 4 and the third solder 8 .

5-13 illustrate a method for manufacturing a flip-chip stacked packaging structure with ultra-fine-pitch pads according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of attaching the carrier with the first conductive column to the substrate; Fig. 6 is a schematic diagram of the connection between the carrier with the first conductive column and the substrate after the first reflow; Fig. 7 is the A schematic diagram of the separation of the carrier from the first conductive pillar, wherein the first conductive pillar remains on the substrate bonding pad.

As shown in FIG. 5 , the conductive column carrier 9 pre-prepared with the first conductive column 3 and the first solder 6 is mounted on the substrate. The existing mature flip-chip bump manufacturing process can realize successive plating of conductive pillars and solder on the carrier 9. Specifically, a protective layer that does not produce metallurgical bonding with the metal is pre-set on the surface of the carrier 9, such as coating poly After polymer coating such as imide, the flip-chip bump manufacturing process can be performed to maintain a very low bonding force between the first conductive pillar 3 and the protective layer of the carrier 9 . A strong metallurgical bond between the first solder 6 and the first conductive pillar 3 is then formed through processes such as reflow soldering.

Next, as shown in FIG. 6 , after reflowing again, the carrier 9 with the first conductive pillar 3 and the first solder 6 is connected to the substrate 100 by solder.

As shown in FIG. 7 , the carrier 9 and the first conductive pillar 3 are separated. Specifically, after the reflow soldering process, a firm metallurgical bond is formed between the first conductive pillar 3 and the first solder 6, and between the first solder 6 and the substrate pad, and the bonding force between them is far Far greater than the bonding force between the first conductive pillar 3 and the protective layer of the carrier 9, it is easy to realize the separation between the first conductive pillar 3 and the carrier 9, so that the first conductive pillar 3 remains on the substrate pad. 8 is a schematic view of the top of the first conductive post 3 on the substrate side after the carrier is separated from the first conductive post 3 , and FIG. 9 is a schematic view of the carrier 9 side after the carrier 9 is separated from the first conductive post 3 . FIG. 8 and FIG. 9 are just an example, and the distribution of the first conductive pillars 3 is not limited to the shapes shown in FIG. 8 and FIG. 9 .

Figure 10 is a schematic diagram of attaching the first chip to the corresponding pad position on the substrate with the first conductive column; Figure 11 is a schematic diagram of attaching the second chip to the corresponding first conductive column position on the substrate Schematic diagram; Figure 12 is a schematic diagram of the interconnection between the first chip and the substrate and the second chip and the substrate formed after the second reflow; Figure 13 is the filling of the underfill into the gap between the second chip, the first chip and the substrate schematic diagram.

As shown in FIGS. 10-13 , the first chip 1 pre-prepared with the third conductive pillars 5 is mounted on the substrate with the first conductive pillars 3 . Then the second chip 2 with the second conductive pillars 4 pre-installed is mounted on the substrate with the first conductive pillars 3 , and the mounting process should pay attention to the alignment of the conductive pillars. After reflow soldering, the bonding pads of the chips 1 and 2 are interconnected with the bonding pads of the substrate.

In order to avoid the melting of the first solder 6 during the reflow soldering process and cause the first conductive column 3 to be skewed and unable to be aligned with the second conductive column 4, it may be necessary to make the melting point of the first solder 6 higher than that of the second solder 4 and the third solder 8. The melting point is 50°C or more higher.

Finally, the underfill material is used to fill the gap between each chip, and also fill the gap between the chip and the substrate, and cover the first solder 6, the first conductive column 3, the second solder 7, and the second conductive column. 4. The third solder 8, the third conductive pillar 5, so as to be finally formed.

If it is necessary to make a stacked package structure of three or more layers of chips, it is necessary to stack multiple layers of conductive pillars on the substrate, and then place the first chip, the second chip, the third chip, and the fourth chip in sequence, and so on. By analogy, the underfill is filled last. This involves going through multiple reflow processes. According to the reasons mentioned above, the melting point of the solder set on the conductive pillars directly connected to each layer of chips is the lowest among all solders, because they are in the final reflow process. .

In addition, solder balls may be distributed on the bottom surface of the substrate for electrical connection with other components.

Although the exemplary embodiment of the present invention has been described in detail above, those with common knowledge in the technical field of the present invention can make various modifications, Retouch and Transform. However, it should be understood that such modifications, modifications and variations will still fall within the spirit and scope of the exemplary embodiments of the present invention as defined by the appended claims.

Finally, the steps of all methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

Claims (14)

1. A stacked flip-chip packaging structure, wherein the stacked flip-chip packaging structure comprises: a substrate, a plurality of pads are arranged on the substrate; Multiple chips stacked up and down, each chip is provided with pads, and each layer of chips contains pads with a spacing of less than 150um; A plurality of conductive columns are arranged between the pads of the chip and the substrate, the substrate pads and the chip pads are electrically connected through the plurality of conductive columns, some of the plurality of conductive columns are stacked up and down, The uppermost chip is electrically connected to the substrate through multi-layer conductive pillars; Underfill material, which fills the gaps between individual chips, Among them, the conductive pillars stacked on each other are connected by solder. Among all the solders used for the connection between the conductive pillars of each layer and for the connection between the conductive pillars and the substrate pads of the package structure, the direct connection with the chips of each layer The melting point of the solder provided at the lower end of the conductive post is the lowest. 2. The stacked flip-chip packaging structure according to claim 1, wherein, The number of layers of conductive pillars arranged on the chip pad is greater than or equal to the number of layers of conductive pillars arranged on the chip pad below the chip. 3. The stacked flip-chip packaging structure according to claim 1 or 2, wherein, The bottom chip is electrically connected to the substrate through a layer of conductive pillars. 4. The stacked flip-chip packaging structure according to claim 1 or 2, the plurality of conductive pillars include a first conductive pillar, a second conductive pillar and a third conductive pillar, and the second conductive pillar is stacked on the first conductive pillar Above the pillars, a third conductive pillar is disposed on the bottommost chip. 5. The stacked flip-chip packaging structure according to claim 4, wherein, The connection between the first conductive column and the second conductive column, and between the first conductive column and the third conductive column and the substrate pad is connected by solder, and the solder includes the first solder, the second solder and the third solder. 6. The stacked flip-chip packaging structure according to claim 5, wherein, The substrate pad is connected to one end of the first conductive column through the first solder, the substrate pad is connected to one end of the third conductive column through the third solder, and the first conductive column is connected to the second conductive column through the second solder. 7. The stacked flip-chip packaging structure according to claim 5 or 6, wherein, The melting point of the first solder is higher than the melting points of the second solder and the third solder by 50° C. or more. 8. The stacked flip-chip packaging structure according to claim 5 or 6, wherein, Materials of the first solder, the second solder and the third solder are lead-free solder. 9. The stacked flip-chip packaging structure according to claim 1 or 2, wherein, The underfill material also fills the gap between the chip and the substrate and coats the various layers of solder and conductive pillars. 10. The stacked flip-chip package structure according to claim 1 or 2, wherein, Materials of the first conductive column, the second conductive column and the third conductive column are all copper. 11. The stacked flip-chip package structure according to claim 1 or 2, wherein, A UBM layer is provided between the bonding pad of the chip and a part of the conductive pillars. 12. A method of manufacturing the stacked flip-chip package structure according to any one of claims 1-11, wherein the method comprises: After the carrier pre-installed with the first conductive column is connected to the substrate by reflow soldering, the first conductive column is separated from the carrier, so that the first conductive column remains on the substrate pad through the first solder connection, Attach the first chip with the third conductive column preset on the corresponding pad on the substrate, attach the second chip with the second conductive column preset on the corresponding first conductive column on the substrate, and reflow soldering again After that, the chip and the substrate are interconnected, The chip-to-chip gap and the chip-to-substrate gap are then filled with an underfill material. 13. The method according to claim 12, wherein a protective layer is provided on the surface of the carrier, and before the first conductive pillar is separated from the carrier, the first conductive pillar is plated on the protective layer of the carrier. 14. The method according to claim 13, wherein the bonding force between the first conductive post and the first solder and the bonding force between the first solder and the substrate pad are greater than that between the first conductive post and the protective layer of the carrier. inter-cohesion.