CN101286459A - Stacktable semiconductor apparatus and manufacturing method - Google Patents
Stacktable semiconductor apparatus and manufacturing method Download PDFInfo
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- CN101286459A CN101286459A CNA2007100963555A CN200710096355A CN101286459A CN 101286459 A CN101286459 A CN 101286459A CN A2007100963555 A CNA2007100963555 A CN A2007100963555A CN 200710096355 A CN200710096355 A CN 200710096355A CN 101286459 A CN101286459 A CN 101286459A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
The invention discloses a semiconductor device which can provide stacking and a manufacturing method; a wafer provided with a plurality of chips is provided; the chip and the wafer are provided with an active surface and a non-active surface oppositely; the active surface of each chip is provided with a plurality of pads so as to form a channel between the adjacent chip pads and form a first metal layer connected to the chip pad electrically at the channel; then the non-active surface of the wafer is thinned to the channel so as to expose the first metal layer; a second metal layer electrically connected with the first metal layer is formed at the non-active layer of the wafer, and then the chips are separated so as to form a plurality of semiconductor devices which can provide stacking; next, the first metal layer and the second metal layer formed on the active surface and the non-active surface of the semiconductor device are used for carrying out stacking mutually and electric connection so as to form stacking structure with a plurality of chips, thus integrating more chips in the condition that the stacking area is not increased, and avoiding the problems that the electrical property is poor due to the use of a bonding wire and the manufacture is complex and the cost is high due to the use of silicon through electrode.
Description
Technical field
The present invention relates to a kind of semiconductor device and method for making thereof, relate in particular to a kind of semiconductor device and method for making thereof for vertical stacking.
Background technology
Because communication, becoming more and more important of the trend that various Portable such as network and computer (Portable) electronic product and peripheral product thereof are compact, and described electronic product develops towards multi-functional and high performance direction, to satisfy the package requirements of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), and for asking the performance (ability) that promotes single semiconductor package part and capacity (capacity) to meet miniaturization of electronic products, the trend of big capacity and high speed, existing is with semiconductor package part multi-chip moduleization (Multichip Module, MCM) form presents, to connect the chip of putting more than at least two on the substrate (as substrate or lead frame) of single packaging part.
Consult Fig. 1, promptly show an existing multi-chip semiconductor package of arranging in the horizontal interval mode.As shown in the figure, this semiconductor package part includes a substrate 100; One first chip 110 has relative active surface 110a and non-active surface 110b, and its non-active surface 110b is bonded on this substrate 100, and with first lead 120 the active surface 110a of this first chip 110 is electrically connected to this substrate 100; And one second chip 140, have relative active surface 140a and non-active surface 140b, its non-active surface 140b is bonded to this substrate 100 and the distance certain with this first street, with second lead 150 the active surface 140a of this second chip 140 is electrically connected to this substrate 100 again.
The major defect of above-mentioned existing multi-chip semiconductor package is to avoiding the lead false touch of chip chamber, must come bonding respectively this chip with certain interval, so if need bonding a plurality of chips then to need to lay large-area chip connecting area territory (Die Attachment Area) to be installed with the chip of requirement on substrate, this measure will cause the increase of cost and can't satisfy compact demand.
Consult Fig. 2 again, show existing as United States Patent (USP) the 6th, 538, No. 331 case announcements are spliced first chip 210 and second chip 240 on substrate 200 with stack manner (Stacked), while is this relative lower floor of chip that splices chip off normal (off-set) segment distance respectively, sets bonding wire 220,250 respectively to this substrate 200 to make things convenient for this first and second chip 210,240.
Though the comparable aforementioned technology saving substrate space of arranging the multicore sheet in the horizontal interval mode of the method, but it still must utilize wire soldering technology to electrically connect chip and substrate, makes to electrically connect quality between chip and substrate and be subject to the line length influence of bonding wire and cause electrically not good.Simultaneously because these chips must skew one segment distance when piling up, and add that bonding wire is provided with the influence in space, still may cause chip-stacked area excessive and can't hold more multicore sheet.
For this reason, U.S. Pat 6,642,081,5,270,261 and 6,809,421 disclose and a kind ofly to utilize the silicon through electrode (Through Silicon Via, TSV) technology is able to vertical stacking for a plurality of semiconductor chips and electrically connects mutually.But its manufacture process too complexity and cost is too high, therefore is short of the industry practical value.
Therefore, how to solve above-mentioned existing multi-chip stacking problem, and develop a kind of unlikely increase area and can effectively in packaging part, integrate more the multicore sheet to promote electrical functionality, avoid using wire soldering technology to cause electrically not good simultaneously and because of using silicon through electrode (TSV) to cause manufacture process too complexity and too high multi-chip stacking structure and the method for making of cost, real is the problem of desiring most ardently solution at present.
Summary of the invention
The shortcoming of background technology in view of the above, main purpose of the present invention is to provide a kind of semiconductor device and method for making thereof of Stackable, and being able to is not increasing under the area, integrates more chip in semiconductor package part.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof of Stackable, thereby mode manufacture process that can be easier avoids using silicon through electrode (TSV) to cause manufacture process too complexity and the too high problem of cost.
A further object of the present invention is to provide a kind of semiconductor device and method for making thereof of Stackable, can directly electrically connect for a plurality of semiconductor chips, avoids using wire soldering technology to cause electrically not good problem.
Another purpose of the present invention is to provide a kind of semiconductor device and method for making thereof of Stackable, can supply the direct vertical stacking of a plurality of semiconductor chips.
For reaching above-mentioned purpose and other purposes, the present invention discloses a kind of method for making of semiconductor device of Stackable, comprise: a wafer with a plurality of chips is provided, described chip and wafer have relative active surface and non-active surface, and be provided with a plurality of weld pads in this chip active surface respectively, between the adjacent chips weld pad, to form groove; Form the first metal layer in this groove place, and make this first metal layer be electrically connected to chip pad; The non-active surface of this wafer of thinning is to this groove place, so that this first metal layer exposes to the non-active surface of this wafer relatively; On the non-active surface of this wafer, an insulating barrier is set, and makes this insulating barrier be formed with opening to expose outside this first metal layer; Form second metal level in this insulating barrier opening part, and make this second metal level be electrically connected to this first metal layer; And separate respectively this chip, to form the semiconductor device of a plurality of Stackables.
Follow-up will be wherein the semiconductor device utilize second metal layer stack on its non-active surface and be electrically connected to the first metal layer on second half conductor means active surface, use the stacked structure that constitutes the multicore sheet.
By aforementioned method for making, the present invention also discloses a kind of semiconductor device of Stackable, comprising: chip, described chip have relative active surface and non-active surface, and this active surface is provided with a plurality of weld pads; The first metal layer is located at this chip active surface edge and side, to be electrically connected to this chip pad; Insulating barrier is covered in the non-active surface of this chip, and this insulating barrier is to being formed with the opening that exposes outside this first metal layer in the non-active surface of chip edge; And second metal level, be formed at this insulating barrier opening, and be electrically connected to this first metal layer.
Therefore, the semiconductor device of Stackable of the present invention and method for making thereof, mainly provide a wafer with a plurality of chips, described chip and wafer have relative active surface and non-active surface, and respectively be provided with a plurality of weld pads on this chip active surface, reach the first metal layer that is electrically connected to chip pad in this groove place formation between the adjacent chips weld pad, to form groove, then the non-active surface of this wafer of thinning exposes this first metal layer to this groove place, and form second metal level that is electrically connected to this first metal layer in the non-active surface of this wafer, separate respectively this chip at last again, to form the semiconductor device of a plurality of Stackables.
Follow-up this semiconductor device can being connect with second metal level on the non-active surface put and is electrically connected on the chip bearing member, and utilize second metal level on its non-active surface to connect the first metal layer of putting and being electrically connected on this previous semiconductor device active surface second half conductor means, use the stacked structure that constitutes the multicore sheet.So, can pile up in unlikely increase and effectively integrate more the multicore sheet under the area situation, and avoid using wire soldering technology to cause electrically not good simultaneously and too complexity and cost are crossed problems such as height because of use silicon through electrode (TSV) causes manufacture process to promote electrical functionality.
Description of drawings
Fig. 1 is existing multi-chip semiconductor package generalized section of arranging in the horizontal interval mode;
Fig. 2 is a United States Patent (USP) the 6th, 538, and No. 331 case disclosed carries out the semiconductor package part generalized section of multi-chip stacking with stack manner;
Fig. 3 A to 3I is the generalized section of the semiconductor device and method for making first embodiment thereof of Stackable of the present invention;
The generalized section of Fig. 4 for semiconductor device of the present invention is piled up;
Fig. 5 is the generalized section of semiconductor device second embodiment of Stackable of the present invention; And
Fig. 6 A to 6D is the generalized section of the semiconductor device and method for making the 3rd embodiment thereof of Stackable of the present invention.
The main element symbol description
100 substrates
110 first chips
The 110a active surface
The non-active surface of 110b
120 bonding wires
140 second chips
The 140a active surface
The non-active surface of 140b
150 bonding wires
200 substrates
210 first chips
220 bonding wires
240 second chips
250 bonding wires
30 chips
300 wafers
301 active surfaces
302 non-active surfaces
303 weld pads
304 grooves
304 ' groove
31,31 ' conductive layer
310 polymerization glue-lines
32,32 ' resist layer
320,320 ' resist layer opening
34 the first metal layers
341 thick copper
342 nickel
343 scolding tin
35 adhesion coatings
36 bearing parts
37 insulating barriers
370 insulating barrier openings
38 second metal levels
381 nickel or copper
382 scolding tin
40 chips
401 active surfaces
402 non-active surfaces
41,41 ' conductive layer
44 the first metal layers
48 second metal levels
The width of W opening
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, the person of ordinary skill in the field can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
First embodiment
Consult Fig. 3 A to 3I, be the semiconductor device and the method for making schematic diagram thereof of Stackable of the present invention.
As shown in Figure 3A, one wafer 300 with a plurality of chips 30 is provided, described chip 30 and wafer 300 have relative active surface 301 and non-active surface 302, and respectively are being provided with a plurality of weld pads 303 on this chip active surface 301, to form groove 304 in 303 of adjacent chips weld pads.
Shown in Fig. 3 B to 3D, on this wafer active surface 301, utilize as modes such as sputters and form conductive layer 31 just like titanium/copper (Ti/Cu), titanizing tungsten/copper (TiW/Cu) or titanizing tungsten/gold (TiW/Au) or aluminium/nickel vanadium/copper (Al/NiV/Cu) or nickel vanadium/copper (NiV/Cu) or titanium/nickel vanadium/copper (Ti/NiV/Cu) or titanizing tungsten/nickel vanadium/copper (TiW/NiV/Cu), cover a resist layer 32 again, and this resist layer 32 is formed with opening 320 that should groove 304.
Then electroplate manufacture process again, form the first metal layer 34 in regular turn with groove 304 positions, and make this first metal layer 34 be electrically connected to chip pad 303 as thick copper (about 10～30 μ m) 341, nickel dam (about 2～5 μ m) 342 and scolding tin 343 in this resist layer opening 320.
Be removable this resist layer 32 and the conductive layer 31 that covered thereof afterwards.
Shown in Fig. 3 E, with this wafer 300 with its active surface 301 adhesion coatings 35 and being adhered on the bearing part 36 just like glass at interval, for these wafer 300 non-active surfaces 302 of thinning to these groove 304 places, so that this first metal layer 34 exposes to the non-active surface 302 of this wafer relatively, and the thickness after these wafer 300 thinnings is about 25～75 μ m.
Shown in Fig. 3 F, on the non-active surface 302 of this wafer, an insulating barrier 37 is set, and makes this insulating barrier 37 be formed with opening 370 to expose outside this first metal layer 34; Wherein this insulating barrier 37 for example be thick about 5 μ m benzocyclobutene (Benzo-Cyclo-Butene, BCB) or polyimides (Polyimide, PI), the width W of this opening 370 is advisable with the width that is slightly less than this groove 304.
Shown in Fig. 3 G and 3H, on these wafer 300 non-active surfaces 302 and insulating barrier 37, utilize as the conductive layer 31 ' of sputtering way formation as Ti/Cu or TiW/Cu, and in this conductive layer 31 ' last covering one resist layer 32 ', and make this resist layer 32 ' be formed with opening 320 ' to expose outside this conductor layer 31 '.
Then by plating mode, include second metal level 38 of nickel for example or copper 381 and scolding tin 382 with formation in this resist layer opening 320 ' in, and make this second metal level 38 be electrically connected to this first metal layer 34.The conductive layer 31 ' that removes this resist layer 32 ' again and covered afterwards.
Shown in Fig. 3 I, remove this loading plate 36, and cut along 30 of described chips, separating respectively this chip 30, thereby form the semiconductor device of a plurality of Stackables.
By aforementioned method for making, the present invention also discloses a kind of semiconductor device of Stackable, comprising: chip 30, and described chip 30 has relative active surface 301 and non-active surface 302, and this active surface 301 is provided with a plurality of weld pads 303; The first metal layer 34 is located at this chip active surface 301 edges and side, to be electrically connected to this chip pad 303; Insulating barrier 37 is covered in the non-active surface 302 of this chip, and 37 pairs of this insulating barriers should be formed with the opening that exposes outside this first metal layer 34 in the non-active surface of chip 302 edges; And second metal level 38, be formed at this insulating barrier 37 openings, and be electrically connected to this first metal layer 34.
Consult Fig. 4 again, the follow-up soldering tin material that semiconductor device wherein can be utilized second metal level 38 on the non-active surface 302 of its chip, and pile up and be electrically connected to the soldering tin material of the first metal layer 34 on the chip active surface 301 of second half conductor means by the reflow operation, use the stacked structure that constitutes the multicore sheet.In addition, also can directly utilize hot pressing (thermalcompression) mode with the aforementioned a plurality of semiconductor devices that make, make the wherein semiconductor device second metal level hot pressing and be electrically connected to the first metal layer of second half conductor means, to form the stacked structure of multicore sheet.
Second embodiment
Consult Fig. 5, be the generalized section of semiconductor device second embodiment of Stackable of the present invention.The semiconductor device and the previous embodiment of present embodiment are roughly the same, its main difference is that the first metal layer 44 that is formed on chip 40 active surfaces 401 of semiconductor device is gold (Au), it is electroplated in the conductive layer 41 (for example being TiW/Au (titanizing tungsten/gold)) of this active surface by sputter in advance and forms, and its thickness is about 15～30 μ m; Be tin (Sn) or gold (Au) with respect to second metal level 48 on the non-active surface 402 of this chip in addition, it is electroplated in the conductive layer 41 ' (for example being Ti/Cu (titanium/copper) or TiW/Cu (titanizing tungsten/copper) or TiW/Au (titanizing tungsten/gold)) of this non-active surface 402 by sputter in advance and forms, and its thickness is about 20～40 μ m.
So, when piling up, can directly utilize hot pressing mode, to form common golden structure, use the simplification manufacture process to the first metal layer (for example being gold) of second half conductor means to incite somebody to action wherein second metal level of semiconductor device (for example being tin) hot pressing.
Therefore, the semiconductor device of Stackable of the present invention and method for making thereof, mainly provide a wafer with a plurality of chips, described chip and wafer have relative active surface and non-active surface, and be provided with a plurality of weld pads in this chip active surface respectively, reach the first metal layer that is electrically connected to chip pad in this groove place formation between the adjacent chips weld pad, to form groove, then the non-active surface of this wafer of thinning exposes this first metal layer to this groove place, and form second metal level that is electrically connected to this first metal layer in the non-active surface of this wafer, separate respectively this chip at last again, to form the semiconductor device of a plurality of Stackables.Follow-up this semiconductor device can being connect with second metal level on the non-active surface put and is electrically connected on the chip bearing member, and utilize second metal level on its non-active surface to connect the first metal layer of putting and being electrically connected on this previous semiconductor device active surface second half conductor means, use the stacked structure that constitutes the multicore sheet; So, can pile up in unlikely increase and effectively integrate more the multicore sheet under the area situation, and avoid using wire soldering technology to cause electrically not good simultaneously and too complexity and cost are crossed problems such as height because of use silicon through electrode (TSV) causes manufacture process to promote electrical functionality.
The 3rd embodiment
Consult Fig. 6 A to 6D again, be the semiconductor package part of Stackable of the present invention and the schematic diagram of method for making the 3rd embodiment thereof.For simplifying this accompanying drawing, the same or analogous element of corresponding above-mentioned first embodiment adopts same numeral to represent in the present embodiment simultaneously.
The semiconductor package part of the Stackable of present embodiment and method for making thereof and this first embodiment are roughly the same, main difference is after 303 of adjacent chips weld pads form groove 304, also can in this groove 304, form the insulating barrier of polymerization glue-line 310, and make this polymerization glue-line 310 form groove 304 ', form conductive layer 31 in this wafer active surface 301 and this groove 304 ' last utilization as modes such as sputters again, to make this polymerization glue-line 310 be formed between described chip 30 and this conductive layer 31, the material of this polymerization glue-line 310 is the polymeric gel of polyimides or benzocyclobutene for example, is formed between described chip 30 and this conductive layer 31 to increase the insulating properties and the tack of described chip 30 and this conductive layer 31 by this polymerization glue-line 310; Then, its follow-up method for making is identical with this first embodiment, to form the semiconductor package part of a plurality of Stackables.
Above-described specific embodiment, only release characteristics of the present invention and effect in order to example, but but not in order to limit practical range of the present invention, do not breaking away under above-mentioned spirit of the present invention and the technical scope, the disclosed content of any utilization and the equivalence finished changes and modify all still should be the claim of enclosing and contains.
Claims (27)
1. the method for making of the semiconductor device of a Stackable comprises:
One wafer with a plurality of chips is provided, and described chip and wafer have relative active surface and non-active surface, and are provided with a plurality of weld pads in this chip active surface respectively, to form groove between the adjacent chips weld pad;
Form the first metal layer in this groove place, and make this first metal layer be electrically connected to chip pad;
The non-active surface of this wafer of thinning is to this groove place, so that this first metal layer exposes to the non-active surface of this wafer relatively;
On the non-active surface of this wafer, an insulating barrier is set, and makes this insulating barrier be formed with opening to expose outside this first metal layer;
Form second metal level in this insulating barrier opening part, and make this second metal level be electrically connected to this first metal layer; And
Separate respectively this chip, to form the semiconductor device of a plurality of Stackables.
2. the method for making of the semiconductor device of Stackable according to claim 1, wherein, the method for making of this first metal layer comprises:
On this wafer active surface, form a conductive layer;
On this conductive layer, cover a resist layer, and this resist layer is formed with opening that should groove;
Electroplate manufacture process, form the first metal layer with groove position, and make this first metal layer be electrically connected to chip pad in this resist layer opening; And
The conductive layer that removes this resist layer and covered.
3. the method for making of the semiconductor device of Stackable according to claim 2, wherein, this conductive layer is one of them of titanium/copper (Ti/Cu), titanizing tungsten/copper (TiW/Cu), titanizing tungsten/gold (TiW/Au), aluminium/nickel vanadium/copper (Al/NiV/Cu), nickel vanadium/copper (NiV/Cu), titanium/nickel vanadium/copper (Ti/NiV/Cu) and titanizing tungsten/nickel vanadium/copper (TiW/NiV/Cu).
4. the method for making of the semiconductor device of Stackable according to claim 2, wherein, this first metal layer comprises thick copper layer, nickel dam and soldering tin material.
5. the method for making of the semiconductor device of Stackable according to claim 2, wherein, this first metal layer is a gold.
6. the method for making of the semiconductor device of Stackable according to claim 1, wherein, before the non-active surface of this wafer of thinning, with this wafer with its active surface adhesion coating and being adhered on the bearing part at interval, for the non-active surface of this wafer of thinning to this groove place.
7. the method for making of the semiconductor device of Stackable according to claim 1, wherein, the method for making of this second metal level comprises:
On non-active surface of this wafer and insulating barrier, form conductive layer;
On this conductive layer, cover a resist layer, and make this resist layer be formed with opening to expose outside this insulating barrier opening;
Then,, and make this second metal level be electrically connected to this first metal layer with formation second metal level in this resist layer opening by plating mode; And
The conductive layer that removes this resist layer and covered.
8. the method for making of the semiconductor device of Stackable according to claim 7, wherein, this conductive layer is one of them of titanium/copper (Ti/Cu), titanizing tungsten/copper (TiW/Cu), titanizing tungsten/gold (TiW/Au), aluminium/nickel vanadium/copper (Al/NiV/Cu), nickel vanadium/copper (NiV/Cu), titanium/nickel vanadium/copper (Ti/NiV/Cu) and titanizing tungsten/nickel vanadium/copper (TiW/NiV/Cu).
9. the method for making of the semiconductor device of Stackable according to claim 7, wherein, this second metal level includes nickel, copper layer and soldering tin material.
10. the method for making of the semiconductor device of Stackable according to claim 7, wherein, this second metal level is the tin layer.
11. the method for making of the semiconductor device of Stackable according to claim 1, also comprise and semiconductor device wherein utilized second metal layer stack on the non-active surface of its chip and be electrically connected to the first metal layer on the chip active surface of second half conductor means, use the stacked structure that constitutes the multicore sheet.
12. the method for making of the semiconductor device of Stackable according to claim 11, wherein, the electric connection of this second metal level and the first metal layer be by reflow in conjunction with and the hot pressing wherein mode that forms common golden structure finish.
13. the method for making of the semiconductor device of Stackable according to claim 1, wherein, after forming groove between the adjacent chips weld pad, also can in this groove, form the insulating barrier of polymerization glue-line, and make this polymerization glue-line form groove, on this wafer active surface and this groove, form the first metal layer again.
14. the method for making of the semiconductor device of Stackable according to claim 13, wherein, the material of this polymerization glue-line is one of them of polyimides and benzocyclobutene.
15. the semiconductor device of a Stackable comprises:
Chip, described chip have relative active surface and non-active surface, and this active surface is provided with a plurality of weld pads;
The first metal layer is located at this chip active surface edge and side, to be electrically connected to this chip pad;
Insulating barrier is covered in the non-active surface of this chip, and this insulating barrier is to being formed with the opening that exposes outside this first metal layer in the non-active surface of chip edge; And
Second metal level is formed at this insulating barrier opening, and is electrically connected to this first metal layer.
16. the semiconductor device of Stackable according to claim 15, wherein, this first metal layer and chip chamber also comprise a conductive layer.
17. the semiconductor device of Stackable according to claim 16, wherein, this conductive layer is one of them of titanium/copper (Ti/Cu), titanizing tungsten/copper (TiW/Cu), titanizing tungsten/gold (TiW/Au), aluminium/nickel vanadium/copper (Al/NiV/Cu), nickel vanadium/copper (NiV/Cu) or titanium/nickel vanadium/copper (Ti/NiV/Cu), titanizing tungsten/nickel vanadium/copper (TiW/NiV/Cu).
18. the semiconductor device of Stackable according to claim 15, wherein, this first metal layer comprises thick copper layer, nickel dam and soldering tin material.
19. the semiconductor device of Stackable according to claim 15, wherein, this first metal layer is a gold.
20. the semiconductor device of Stackable according to claim 15, wherein, this second metal level and chip chamber also comprise a conductive layer.
21. the semiconductor device of Stackable according to claim 20, wherein, this conductive layer is one of them of titanium/copper (Ti/Cu), titanizing tungsten/copper (TiW/Cu).
22. the semiconductor device of Stackable according to claim 15, wherein, this second metal level includes nickel, copper layer and soldering tin material.
23. the semiconductor device of Stackable according to claim 15, wherein, this second metal level is the tin layer.
24. the semiconductor device of Stackable according to claim 15, also include second half conductor means, by second metal layer stack on the non-active surface of its chip and be electrically connected to the first metal layer on the chip active surface of this semiconductor device, use the stacked structure that constitutes the multicore sheet.
25. the semiconductor device of Stackable according to claim 24, wherein, the electric connection of this second metal level and the first metal layer be by reflow in conjunction with and the hot pressing wherein mode that forms common golden structure finish.
26. the semiconductor device of Stackable according to claim 15 wherein, also is formed with the insulating barrier of polymerization glue-line between the first metal layer and the described chip.
27. the semiconductor device of Stackable according to claim 26, wherein, the material of this polymerization glue-line is one of them of polyimides and benzocyclobutene.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100963555A CN101286459A (en) | 2007-04-13 | 2007-04-13 | Stacktable semiconductor apparatus and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100963555A CN101286459A (en) | 2007-04-13 | 2007-04-13 | Stacktable semiconductor apparatus and manufacturing method |
Publications (1)
| Publication Number | Publication Date |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894815A (en) * | 2009-05-20 | 2010-11-24 | 瑞萨电子株式会社 | Semiconductor device and manufacture method thereof |
| CN101937892A (en) * | 2009-06-29 | 2011-01-05 | 三星电子株式会社 | Semiconductor chip, method of fabricating the same, and stack module and memory card |
| CN103199071A (en) * | 2013-03-29 | 2013-07-10 | 日月光半导体制造股份有限公司 | Stacking type packaging structure and manufacturing method thereof |
| CN104955277A (en) * | 2014-03-24 | 2015-09-30 | 深南电路有限公司 | Production method for thick-copper circuit board |
| CN108389912A (en) * | 2018-01-12 | 2018-08-10 | 武汉高芯科技有限公司 | A kind of non-refrigerated infrared detector chip and its encapsulating structure and preparation method |
-
2007
- 2007-04-13 CN CNA2007100963555A patent/CN101286459A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894815A (en) * | 2009-05-20 | 2010-11-24 | 瑞萨电子株式会社 | Semiconductor device and manufacture method thereof |
| CN101894815B (en) * | 2009-05-20 | 2015-07-29 | 瑞萨电子株式会社 | Semiconductor device and manufacture method thereof |
| CN101937892A (en) * | 2009-06-29 | 2011-01-05 | 三星电子株式会社 | Semiconductor chip, method of fabricating the same, and stack module and memory card |
| CN101937892B (en) * | 2009-06-29 | 2015-08-12 | 三星电子株式会社 | Semiconductor chip and manufacture method, stack module and storage card |
| CN103199071A (en) * | 2013-03-29 | 2013-07-10 | 日月光半导体制造股份有限公司 | Stacking type packaging structure and manufacturing method thereof |
| CN104955277A (en) * | 2014-03-24 | 2015-09-30 | 深南电路有限公司 | Production method for thick-copper circuit board |
| CN104955277B (en) * | 2014-03-24 | 2018-02-23 | 深南电路有限公司 | A kind of heavy copper circuit board preparation method |
| CN108389912A (en) * | 2018-01-12 | 2018-08-10 | 武汉高芯科技有限公司 | A kind of non-refrigerated infrared detector chip and its encapsulating structure and preparation method |
| CN108389912B (en) * | 2018-01-12 | 2020-02-28 | 武汉高芯科技有限公司 | Uncooled infrared detector chip and packaging structure and preparation method thereof |
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