CN101452860B - Multi-chip stacking structure and preparation thereof - Google Patents
Multi-chip stacking structure and preparation thereof Download PDFInfo
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- CN101452860B CN101452860B CN2007101865475A CN200710186547A CN101452860B CN 101452860 B CN101452860 B CN 101452860B CN 2007101865475 A CN2007101865475 A CN 2007101865475A CN 200710186547 A CN200710186547 A CN 200710186547A CN 101452860 B CN101452860 B CN 101452860B
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention discloses a multichip stacking structure and a method for manufacturing the same. The multi-chip stacking structure provides a chip bearing piece with a first surface and a second surface; a first chip and a second chip are connected to the first surface of the chip bearing piece and are in electric connection with the chip bearing piece through welding wires; a third chip is alternate with an adhesive layer and is simultaneously stacked on the first chip and the second chip, wherein the third chip is connected with the first chip in a stepped mode and avoids being contacted with the welding wires of the first chip and the second chip; and the third chip is in electric connection the chip bearing piece through the welding wires, thereby saving the use space of the chip bearing piece so as to be favorable for minitype of the whole structure.
Description
Technical field
The present invention relates to a kind of semiconductor structure and method for making thereof, particularly a kind of multi-chip stacking structure and method for making thereof.
Background technology
Because the microminiaturization of electronic product and the increase of high speed of service demand, and be to improve the performance of single semiconductor package and capacity to meet the demand of miniaturization of electronic products, semiconductor package is into a trend with multi-chip moduleization (Multichip Module), thereby whereby with two or more chip portfolios in single encapsulating structure, with reduction electronic product integrated circuit structural volume, and promote electrical functionality.That is multichip packaging structure can pass through two or more chip portfolios in single encapsulating structure the restriction of system running speed to be minimized; In addition, multichip packaging structure can reduce the length of chip chamber connection line and reduce signal delay and access time.
Common multichip packaging structure is for adopting side-by-side (side-by-side) multichip packaging structure, and it is the main installed surface that plural chip is installed on each other abreast a common substrate.Being connected between the conducting wire generally is to reach by wire bonds mode (wire bonding) on chip and the common substrate.Yet to be packaging cost too high and the encapsulating structure size is too big for the shortcoming of this side-by-side multichip package structure, because of the area of this common substrate can increase along with the increase of core number.
For solving above-mentioned prior art problems, in recent years for using rectilinear stacking method that the chip that is increased is installed, its mode of piling up is according to the design of its chip, the routing processing procedure is had nothing in common with each other, but if this chip is designed to weld pad when concentrating on one side, set flash chip (flash memory chip) or DRAM (Dynamic Random Access Memory) chip (Dynamic Random Access Memory in the electronic installation of memory card for example, DRAM) etc., convenience for routing, its stack manner is to carry out with stair-stepping form, United States Patent (USP) the 6th shown in Figure 1A and Figure 1B, 538, the multi-chip stacking structure that is disclosed for No. 331 (wherein this Figure 1B is the vertical view of corresponding Figure 1A), be on chip bearing member 10, to have piled up a plurality of memory chips, so that first memory chip 11 is installed on the chip bearing member 10, it is to be scalariform under the principle to be stacked on this first memory chip 11 that second memory chip 12 does not hinder the routing operation of first memory chip, 11 weld pads with the distance of a skew, in addition, in the electronic installation of this memory card, be provided with control chip (controller) 13 again, the periphery of this control chip 13 is provided with a plurality of weld pads, and by many bonding wires 15 with this first and second memory chip 11,12 and control chip 13 be electrically connected to this chip bearing member 10.
And be to save the substrate usage space, this control chip 13 can be stacked on this second memory chip 12, but so will increase integrally-built height; Moreover since the planar dimension of general control chip 13 much smaller than the planar dimension of this first and second memory chip 11,12, therefore when utilizing bonding wire 15 that this control chip 13 is electrically connected to this chip bearing member 10, those bonding wires 15 certainly will be crossed over first and second memory chip 11,12 of these control chip 13 belows, so promptly easily cause bonding wire 15 touching to first and second memory chip 11,12 and the problem that is short-circuited, also increase the degree of difficulty of bonding wire operation simultaneously.
Relatively, this control chip 13 is placed on the chip bearing member 10 for connecing the zone of putting first and second memory chip 11,12, can increase the usable floor area of chip bearing member 10 again, unfavorable integrally-built miniaturization as desire.
Therefore, how a kind of structure and method for making thereof of stacked multichip are provided, integrate a plurality of chips and do not need additionally to increase encapsulating structure area, highly again to reach, to be applicable to thin type electronic device, reduce bonding wire operational difficulty degree simultaneously and avoid the problem of being short-circuited, real target for demanding urgently at present reaching.
Summary of the invention
In view of above prior art shortcoming, a purpose of the present invention provides a kind of multi-chip stacking structure and method for making thereof, thereby can carry out piling up of multilayer chiop additionally not increasing under encapsulating structure area and the height principle.
Another object of the present invention provides a kind of multi-chip stacking structure and method for making thereof, goes for thin type electronic device.
Another purpose of the present invention provides a kind of multi-chip stacking structure and method for making thereof, is minimized bonding wire operational difficulty degree and avoids bonding wire to touch chip and the problem that is short-circuited.
For achieving the above object, the invention provides a kind of method for making of multi-chip stacking structure, comprise: a tool first and second surperficial chip bearing member relatively is provided, place this chip bearing member first surface so that one first chip and one second chip are connect, and be electrically connected to this chip bearing member by bonding wire; One the 3rd street, one adhesion layer is stacked on this first and second chip simultaneously, and wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and avoids contacting the bonding wire to this first and second chip; And utilize bonding wire to electrically connect the 3rd chip and chip bearing member.This first, second and third chip is provided with a plurality of weld pads in monolateral surface, and this first and the 3rd chip for example is a memory chip, and this second chip for example is a control chip, and this adhesion layer is the adhesive tape (tape) for insulating for example.
By aforementioned method for making, the present invention also provides a kind of multi-chip stacking structure, comprising: tool is first and second surperficial chip bearing member relatively; First chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire; Second chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire; And the 3rd chip, an adhesion layer and being stacked in simultaneously on this first and second chip at interval, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and avoids contacting the bonding wire to this first and second chip.
In addition, can on the 3rd chip, pile up the four-core sheet again in the scalariform mode.In addition those chips generally the routing mode or oppositely welding (Reverse Wire Bonding) mode and with this chip bearing member electric connection, wherein this reverse welding manner is that the weldering earlier of bonding wire outer end is tied to this chip bearing member, again its inner is soldered to this chip, use and reduce the bank height, so that more frivolous multi-chip stacking structure to be provided.
This first, the 3rd and the four-core sheet be provided with a plurality of weld pads (for example for memory chip) in monolateral surface, and a side of corresponding its tool weld pad is to depart from square chip one predefined distance down, and stepped piling up.This second chip also is provided with a plurality of weld pads (for example for control chip) in monolateral surface, and the planar dimension of this second chip less than first, the 3rd and four-core plate plane size.
Moreover, when this second chip when polygon surface has weld pad, can be prior to utilizing circuit rearrangement layer (Redistribution layer on this second chip, RDL) technology, weld pad on this second chip is concentrated on monolateral surface, to electrically connect this second chip pad and chip bearing member by bonding wire, when avoiding simultaneously piling up the 3rd chip on this first and second chip, the 3rd chip is urged to the bonding wire of first and second chip.
Therefore, multi-chip stacking structure of the present invention and method for making thereof, first and second chip connect place the chip bearing member surface, and utilize bonding wire to be electrically connected to this chip bearing member, piling up simultaneously on this first and second chip has the 3rd chip again, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and avoid contacting bonding wire to this first and second chip, and be electrically connected to chip bearing member by bonding wire, use avoid prior art with this planar dimension when second chip (control chip) of the first and the 3rd chip (memory chip) planar dimension is stacked in the 3rd chip, increase integrally-built height, and can avoid bonding wire to cross over and touching is short-circuited to the first and the 3rd chip (memory chip) and increases bonding wire operational difficulty degree problem, moreover, because of this second chip is directly to connect to place on the chip bearing member and by the 3rd street one adhesion layer to be stacked on this first and second chip, so can save the chip bearing member usage space, in order to integrally-built miniaturization.
Description of drawings
Figure 1A and Figure 1B are United States Patent (USP) the 6th, 538, No. 331 disclosed multi-chip stacking structure sections and floor map;
Fig. 2 A to Fig. 2 C is the generalized section of multi-chip stacking structure of the present invention and method for making first embodiment thereof;
Fig. 3 is the generalized section of multi-chip stacking structure of the present invention and method for making second embodiment thereof;
Fig. 4 is the generalized section of multi-chip stacking structure of the present invention and method for making the 3rd embodiment thereof; And
Fig. 5 A to Fig. 5 C is the generalized section of multi-chip stacking structure of the present invention and method for making the 4th embodiment thereof.
The main element symbol description:
10 chip bearing members
11 first memory chips
12 second memory chips
13 control chips
15 bonding wires
20 chip bearing members
21 first chips
22 second chips
23 the 3rd chips
210,220,230 weld pads
251,252,253 bonding wires
26 adhesion layers
30 chip bearing members
31 first chips
32 second chips
33 the 3rd chips
34 four-core sheets
354 bonding wires
40 chip bearing members
41 first chips
42 second chips
43 the 3rd chips
410,420,430 weld pads
451,452,453 bonding wires
50 chip bearing members
51 first chips
52 second chips
53 the 3rd chips
551,552,553 bonding wires
56 adhesion layers
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
See also Fig. 2 A to Fig. 2 C, be the generalized section of multi-chip stacking structure of the present invention and method for making first embodiment thereof.
Shown in Fig. 2 A, relatively first and second surperficial chip bearing member 20 of a tool is provided, so that being connect, at least one first chip 21 and at least one second chip 22 place this chip bearing member 20 first surfaces.
This first chip 21 and second chip 22 for example are memory chip and control chip, these second chip, 22 planar dimensions are less than first chip, 21 planar dimensions, and these first chip, 21 monolateral marginal surfaces are provided with a plurality of weld pads 210, these second chip, 22 monolateral marginal surfaces are provided with a plurality of weld pads 220 again, to be electrically connected to this chip bearing member 20 by bonding wire 251,252 respectively.
On this chip bearing member 20, connect and put this first and second chip at 21,22 o'clock, this 21,22 of first and second chip is approaching as far as possible mutually, but should avoid contact, use and reduce the chip bearing member usable floor area, and then saving manufacturing cost, and a side of these first chip, 21 tool weld pads 210 be with a side of these second chip, 22 tool weld pads 220 mutually away from, to carry out the routing operation.This chip bearing member 20 can be a spherical grid array type (BGA) substrate, planar gate array (LGA) substrate or lead frame.
Shown in Fig. 2 B and Fig. 2 C, at least one the 3rd chip 23 interval one adhesion layers 26 are stacked on this first and second chip 21,22 simultaneously, wherein the 3rd chip 23 is to be the scalariform mode to connect and place on this first chip 21, and avoids contacting the bonding wire 251,252 to this first and second chip 21,22.
Then, utilize bonding wire 253 to electrically connect the 3rd chip 23 and chip bearing member 20.
The 3rd chip 23 for example is the memory chip of the monolateral weld pad of tool, the 3rd chip 23 monolateral marginal surfaces are provided with a plurality of weld pads 230, and be stacked on this first and second chip 21,22 to depart from these first chip, 21 weld pads, 210 1 predefined distances, make and be able to be electrically connected to this chip bearing member 20 for this first and the 3rd chip 21,23 in the unlikely weld pad 210 that keeps off first chip 21 of the 3rd chip 23 zone vertically upward by many bonding wires 251,253.This adhesion layer 26 for example can use general insulating tape (tape), and with the saving manufacturing cost, and its thickness is about the 10-25 micron.
Moreover, when this second chip 22 (control chip) in polygon when having weld pad, can utilize circuit rearrangement layer (Redistribution layer, RDL) technology, weld pad on this second chip is concentrated on monolateral surface, to electrically connect this second chip pad and chip bearing member by bonding wire, when avoiding simultaneously piling up the 3rd chip on this first and second chip, the 3rd chip is urged to the bonding wire of first and second chip.
So comparing prior art piles up a plurality of chips merely, the application connects first chip 21 to place on the chip bearing member 20 together with second chip 22, again the 3rd chip 23 interval one adhesion layers 26 are stacked in this first and second chip 21 simultaneously, on 22, and make the 3rd chip 23 be the scalariform mode to be stacked on this first chip 21, and avoid contact to this first and second chip 21,22 bonding wire 251,252, to reach compact purpose, can avoid connecting second chip 22 simultaneously and cross over and touch to the first and the 3rd chip 21 with the bonding wire 252 of chip bearing member 20,23 and be short-circuited and increase bonding wire operational difficulty degree problem.
By aforementioned method for making, the present invention discloses a kind of multi-chip stacking structure again, comprising: a tool is first and second surperficial chip bearing member 20 relatively; First chip 21 connects and places this chip bearing member 20 first surfaces, and is electrically connected to this chip bearing member 20 by bonding wire 251; Second chip 22 connects and places this chip bearing member 20 first surfaces, and is electrically connected to this chip bearing member 20 by bonding wire 252; And the 3rd chip 23, an adhesion layer 26 and being stacked in simultaneously on this first and second chip 21,22 at interval, and be electrically connected to this chip bearing member 20 by bonding wire 253, wherein the 3rd chip 23 is to be the scalariform mode to connect and place on this first chip 21, and avoids contacting the bonding wire 251,252 to this first and second chip 21,22.
Therefore, multi-chip stacking structure of the present invention and method for making thereof, be first and second chip to be connect place the chip bearing member surface, and utilize bonding wire to be electrically connected to this chip bearing member, piling up simultaneously on this first and second chip has the 3rd chip again, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and avoid contacting bonding wire to this first and second chip, and be electrically connected to chip bearing member by bonding wire, use avoid prior art with this planar dimension when second chip (control chip) of the first and the 3rd chip (memory chip) planar dimension is stacked in the 3rd chip, increase integrally-built height, and can avoid bonding wire to cross over and touching is short-circuited to the first and the 3rd chip (memory chip) and increases bonding wire operational difficulty degree problem, moreover, because of this second chip is directly to connect to place on the chip bearing member and by the 3rd street one adhesion layer to be stacked on this first and second chip, so can save the chip bearing member usage space, in order to integrally-built miniaturization.
Second embodiment
See also Fig. 3 again, be the schematic diagram of multi-chip stacking structure of the present invention and method for making second embodiment thereof.Present embodiment and previous embodiment are roughly the same, main difference is to connect on the 3rd chip 33 that places first and second chip 31,32, must continue to pile up four-core sheet 34 as memory chip in the scalariform mode, and be electrically connected to chip bearing member 30 by bonding wire 354, to promote integrally-built memory capacity.
The 3rd embodiment
See also Fig. 4 again, be the schematic diagram of multi-chip stacking structure of the present invention and method for making the 3rd embodiment thereof.Present embodiment and previous embodiment are roughly the same, main difference is first chip 41 and second chip 42 that places on chip bearing member 40 first surfaces connecing, and be stacked in this first and second chip 41, the 3rd chip 43 on 42 is can adopt reverse welding manner (ReverseWire Bonding) and be electrically connected to chip bearing member 40, also be about in order to connect first, second and third chip 41,42,43 with the bonding wire 451 of chip bearing member 40,452,453 outer ends are burnt the ball bonding knot earlier to first, second and third chip 41,42,43 weld pad 410,420,430, to form a projection (stud), again from chip bearing member 40 welding, on draw and be soldered on this projection, with with bonding wire 451,452, (Stitch Bond) sewed up to this projection in 453 the inners, so, can reduce the bank height that electrically connects between chip and chip bearing member, with the height of further reduction integral stacked structure.
The 4th embodiment
See also Fig. 5 A to Fig. 5 C again, be the schematic diagram of multi-chip stacking structure of the present invention and method for making the 4th embodiment thereof.The present embodiment and first embodiment are roughly the same, main difference be finish chip connect put operation after, carry out the routing operation again.
Shown in Fig. 5 A, relatively first and second surperficial chip bearing member 50 of a tool is provided, so that being connect, at least one first chip 51 and at least one second chip 52 place this chip bearing member 50 first surfaces.
Shown in Fig. 5 B, with at least one the 3rd chip 53 adhesion layers 56 and being stacked in simultaneously on this first and second chip 51,52 at interval, wherein the 3rd chip 53 is to be the scalariform mode to connect and place on this first chip 51.
Shown in Fig. 5 C, carry out the routing operation, be electrically connected to chip bearing member 50 by bonding wire 551,552,553 respectively for this first, second and third chip 51,52,53.
That is, be this first, second and third chip successively to be connect to place on this chip bearing member earlier in present embodiment, utilize bonding wire to electrically connect those first, second and third chip and chip bearing members more simultaneously, thereby can simplify fabrication steps and order, accelerate processing procedure speed, simultaneously also can avoid utilizing bonding wire to electrically connect first, second chip and chip bearing member earlier, the 3rd chip is connect when placing on this first and second chip, the 3rd chip false touch is to the bonding wire problem of first and second chip again.
Above-described specific embodiment, only release characteristics of the present invention and effect in order to example, but not in order to limit the category of implementing of the present invention, do not breaking away under above-mentioned spirit of the present invention and the technology category, the disclosed content of any utilization and the equivalence finished changes and modify, the scope that all still should be claims contains.
Claims (18)
1. the method for making of a multi-chip stacking structure comprises:
One tool first and second surperficial chip bearing member relatively is provided, so that being connect, one first chip and second chip place this chip bearing member first surface, and be electrically connected to this chip bearing member by bonding wire, this first chip is a memory chip, this second chip is a control chip, and this first chip does not contact each other with second chip and has the gap;
One the 3rd street, one adhesion layer is stacked on this first and second chip simultaneously, be not filled with this adhesion layer in this gap, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and avoid contacting bonding wire to this first and second chip, the 3rd chip is a memory chip, and this second chip planar dimension is less than first chip and the 3rd chip planar dimension; And
Utilize bonding wire to electrically connect the 3rd chip and chip bearing member.
2. the method for making of multi-chip stacking structure according to claim 1, wherein, the monolateral marginal surface of this first, second and third chip is provided with a plurality of weld pads.
3. the method for making of multi-chip stacking structure according to claim 1, wherein, this chip bearing member is wherein one of spherical grid array type substrate, planar gate array substrate and a lead frame.
4. the method for making of multi-chip stacking structure according to claim 1 is included in again on the 3rd chip and piles up the four-core sheet in the scalariform mode.
5. the method for making of multi-chip stacking structure according to claim 1, wherein, this first, second and third chip selects to utilize wherein one of general routing mode and reverse welding manner, and is electrically connected to this chip bearing member.
6. the method for making of multi-chip stacking structure according to claim 1, wherein, this adhesion layer is an insulating tape.
7. the method for making of a multi-chip stacking structure comprises:
One tool first and second surperficial chip bearing member relatively is provided, so that being connect, one first chip and second chip place this chip bearing member first surface, this first chip is a memory chip, and this second chip is a control chip, and this first chip does not contact each other with second chip and has the gap;
One the 3rd street, one adhesion layer is stacked on this first and second chip simultaneously, be not filled with this adhesion layer in this gap, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, the 3rd chip is a memory chip, and this second chip planar dimension is less than first chip and the 3rd chip planar dimension; And
Utilize bonding wire to electrically connect this first, second and third chip and chip bearing member.
8. the method for making of multi-chip stacking structure according to claim 7, wherein, the monolateral marginal surface of this first, second and third chip is provided with a plurality of weld pads.
9. the method for making of multi-chip stacking structure according to claim 7, wherein, this chip bearing member is wherein one of spherical grid array type substrate, planar gate array substrate and a lead frame.
10. the method for making of multi-chip stacking structure according to claim 7 is included in again on the 3rd chip and piles up the four-core sheet in the scalariform mode.
11. the method for making of multi-chip stacking structure according to claim 7, wherein, this first, second and third chip selects to utilize wherein one of general routing mode and reverse welding manner, and is electrically connected to this chip bearing member.
12. the method for making of multi-chip stacking structure according to claim 7, wherein, this adhesion layer is an insulating tape.
13. a multi-chip stacking structure comprises:
Tool is first and second surperficial chip bearing member relatively;
First chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire, and this first chip is a memory chip;
Second chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire, and this second chip is a control chip, and this first chip does not contact each other with second chip and has the gap; And
The 3rd chip, an adhesion layer and being stacked in simultaneously on this first and second chip at interval, be not filled with this adhesion layer in this gap, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and avoid contacting bonding wire to this first and second chip, the 3rd chip is a memory chip, and this second chip planar dimension is less than first chip and the 3rd chip planar dimension.
14. multi-chip stacking structure according to claim 13, wherein, the monolateral marginal surface of this first, second and third chip is provided with a plurality of weld pads.
15. multi-chip stacking structure according to claim 13, wherein, this chip bearing member is wherein one of spherical grid array type substrate, planar gate array substrate and a lead frame.
16. multi-chip stacking structure according to claim 13 includes the four-core sheet again, is stacked on the 3rd chip in the scalariform mode.
17. multi-chip stacking structure according to claim 13, wherein, this first, second and third chip selects to utilize wherein one of general routing mode and reverse welding manner, and is electrically connected to this chip bearing member.
18. multi-chip stacking structure according to claim 13, wherein, this adhesion layer is an insulating tape.
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| CN2007101865475A CN101452860B (en) | 2007-12-07 | 2007-12-07 | Multi-chip stacking structure and preparation thereof |
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| US10049953B2 (en) | 2015-09-21 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors |
| US9917072B2 (en) | 2015-09-21 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process |
| WO2017049585A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Method, apparatus and system to interconnect packaged integrated circuit dies |
| CN107301981B (en) * | 2016-04-15 | 2020-07-10 | 台湾积体电路制造股份有限公司 | Integrated fan-out package and method of manufacture |
| KR102576764B1 (en) * | 2016-10-28 | 2023-09-12 | 에스케이하이닉스 주식회사 | Semiconductor packages of asymmetric chip stacks |
| US20180233484A1 (en) * | 2017-02-14 | 2018-08-16 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
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| CN1485914A (en) * | 2002-09-29 | 2004-03-31 | 矽品精密工业股份有限公司 | Window opening type multi-chip semiconductor package |
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| CN1485914A (en) * | 2002-09-29 | 2004-03-31 | 矽品精密工业股份有限公司 | Window opening type multi-chip semiconductor package |
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