CN107301981B

CN107301981B - Integrated fan-out package and method of manufacture

Info

Publication number: CN107301981B
Application number: CN201710219639.2A
Authority: CN
Inventors: 余振华; 余国宠; 蔡豪益; 郭庭豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2016-04-15
Filing date: 2017-04-06
Publication date: 2020-07-10
Anticipated expiration: 2037-04-06
Also published as: CN107301981A; US20230114652A1

Abstract

Embodiments of the present invention disclose a method comprising forming a first via from a first conductive pad of a first device die and forming a second via from a second conductive pad of a second device die. The first and second conductive pads are at the top surfaces of the first and second device dies, respectively. The first and second conductive pads may serve as seed layers. A second device die is adhered to the top surface of the first device die. The method also includes encapsulating the first and second device dies and the first and second vias into an encapsulation material, and encapsulating the first and second device dies and the first and second vias in the same encapsulation process. The encapsulation material is planarized to expose the first and second vias. A redistribution line is formed to electrically connect the first via and the second via. Embodiments of the invention relate to an integrated fan-out package and a method of manufacturing.

Description

Integrated fan-out package and method of manufacture

Technical Field

Embodiments of the invention relate to an integrated fan-out package and a method of manufacturing.

Background

Stacked dies are commonly used in three-dimensional integrated circuits. By stacking the dies, the footprint (form factor) of the package is reduced. In addition, the formation by stacking dies significantly simplifies the metal lines routed in the dies.

In some applications, multiple dies are stacked to form a die stack, where the multiple dies include through-substrate vias (TSVs, sometimes referred to as through-silicon vias). The total number of stacked die can sometimes reach eight or more. When forming such a die stack, the first die is first bonded to the package substrate by flip-chip bonding, wherein the lands or solder balls are reflowed to bond the first die to the package substrate. A first underfill is dispensed into a gap between the first die and the package substrate. The first underfill is then cured. Then, tests are performed to ensure that the first die is properly connected to the package substrate and that the first die and the package substrate function as intended.

Next, the second die is bonded to the first die by flip-chip bonding, wherein the lands/balls are reflowed to bond the second die to the first die. A second underfill is dispensed into the gap between the second die and the first die. The second underfill is then cured. Then, tests are performed to ensure that the second die is properly connected to the first die and the package substrate and that the first die, the second die, and the package substrate function as intended. The third die is then bonded to the second die by the same process steps used to bond the second die to the first die. This process is repeated until all of the dies are bonded.

Disclosure of Invention

According to an embodiment of the present invention, there is provided a method of manufacturing a fan-out package, including: forming a first via from a first conductive pad of a first device die, wherein the first conductive pad is located at a top surface of the first device die; forming a second via from a second conductive pad of a second device die, wherein the second conductive pad is located at a top surface of the second device die; adhering the second device die to the top surface of the first device die; encapsulating the first and second device dies and the first and second vias in an encapsulation material, wherein the first and second device dies and the first and second vias are encapsulated in the same encapsulation process; planarizing the encapsulation material to expose the first and second vias; and forming a redistribution line over and electrically connected to the first via and the second via.

There is also provided, in accordance with another embodiment of the present invention, a method of manufacturing a fan-out package, including: forming a first via on a first conductive pad of a first device die; forming a second via on a second conductive pad of a second device die; placing the first device die and the second device die over a carrier; forming a third via on a third conductive pad of a third device die; and forming a fourth via on the fourth conductive pad of the fourth device die; adhering the third device die and the fourth device die to a top surface of the first device die and a top surface of the second device die, respectively; simultaneously encapsulating the first device die, the second device die, the third device die, and the fourth device die and the first via, the second via, the third via, and the fourth via in an encapsulation material; planarizing the encapsulation material to expose the first, second, third, and fourth vias; and forming redistribution lines over and electrically connected to the first, second, third, and fourth vias.

According to still another embodiment of the present invention, there is also provided a package including: a first device die; a first via having a first bottom surface in contact with a top surface of a first conductive pad of the first device die; a second device die comprising a first portion overlapping a portion of the first device die; a second via comprising: a lower portion at a same level as the first device die, wherein the lower portion has a second bottom surface in contact with a top surface of a second conductive pad of the second device die; and an upper portion at the same level as the second device die, wherein the lower portion is continuously connected to the upper portion and there is no discernible interface between the upper portion and the lower portion; an encapsulation material encapsulating the first device die, the second device die, the first via, and the second via in the encapsulation material; a redistribution line over and electrically connected to the first via and the second via.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1I illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments.

Fig. 2A-2I illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments.

Fig. 3A-3J illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments.

Fig. 4A-4J illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments.

Fig. 5-10 illustrate cross-sectional views of fan-out packages according to some embodiments.

FIG. 11 illustrates a top view of a fan-out package according to some embodiments.

Fig. 12 illustrates a process flow for forming a fan-out package according to some embodiments.

Fig. 13A-13C illustrate some top structures for connecting respective device dies with overlying redistribution layers according to some embodiments.

Fig. 14 illustrates exemplary symbols representing the structures illustrated in fig. 13A-13C, according to some embodiments.

Fig. 15A-15K illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments.

Fig. 16A and 16B illustrate cross-sectional and top views, respectively, of a fan-out package according to some embodiments.

Fig. 17A and 17B illustrate cross-sectional and top views, respectively, of a fan-out package according to some embodiments.

Fig. 18A-18C respectively illustrate cross-sectional views of a fan-out package including a memory cube, according to some embodiments.

Fig. 19 illustrates a process flow for forming a fan-out package using a single molding process, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spatial relational terms, such as "below," "beneath," "lower," "above," "over," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.

An integrated fan-out package and a method of forming an integrated fan-out package are provided according to various exemplary embodiments. An intermediate stage of forming a fan-out package is illustrated. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various views and exemplary embodiments.

Fig. 1A-1I illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments. The steps shown in fig. 1A to 1I are also schematically illustrated in the process flow as shown in fig. 12. In the discussion that follows, the process steps illustrated in fig. 1A through 1I are discussed with reference to the process steps of fig. 12.

Referring to fig. 1A, a device die 10 (which is a portion of a respective wafer 2 having a plurality of device dies) is provided. According to some embodiments of the invention, device die 10 is a logic die, which may be a Central Processing Unit (CPU) die, a Micro Control Unit (MCU) die, an input-output (IO) die, a baseband (BB) die, or an Application Processor (AP) die. Although not shown, device die 10 may include a semiconductor substrate with active devices, such as transistors and/or diodes, formed on a top surface of the semiconductor substrate. In addition, metal lines and vias (not shown) are formed in an interconnect structure (not shown) of device die 10 over the semiconductor substrate to interconnect the integrated circuit devices in device die 10.

Metal pads 12 are formed at the top surface 10A of the device die 10. The top surface 10A of device die 10 is also referred to as the front surface. Device die 10 has a back surface 10B, which may also be the back surface of a respective semiconductor substrate in device die 10. The metal pads 12 may be aluminum pads, copper pads, aluminum copper pads, or the like. Metal pads 12 may be formed in a first surface area of device die 10 and a second surface area of device die 10 has no metal pads formed therein. For example, according to some exemplary embodiments as shown in fig. 1A, the right surface region has a metal pad 12 therein, while the left surface region has no metal pad.

Fig. 1B to 1C illustrate the formation of the through-hole 14. The corresponding step is illustrated as step 202 in the process step shown in fig. 12. According to some embodiments, as shown in fig. 1B, a photoresist 16 is formed over the wafer 2 and then patterned to form openings 15, exposing a portion of each metal pad 12 through the openings 15. The through holes 14 are then plated in the openings 15. The photoresist 16 is then removed, resulting in the structure of FIG. 1C. According to some embodiments of the present invention, no seed layer is formed on wafer 2 prior to plating, and thus metal pads 12 act as a seed layer. According to an alternative embodiment, a seed layer (not shown) is formed prior to the formation of photoresist 16, and vias 14 are plated over the seed layer. After removal of photoresist 16, the portions of the seed layer not directly under vias 14 are removed in an etching process. Thus, the remaining portion of the seed layer becomes the bottom portion of the via 14.

Next, referring to fig. 1D, device die 20 is adhered to device die 10 by Die Attach Film (DAF) 22. The corresponding step is illustrated as step 204 in the process step shown in fig. 12. The back surfaces of device dies 20 are adhered to the front surfaces of device dies 10, and thus the respective die stacks are face-to-back stacks. According to some embodiments of the invention, device die 20 is a memory die, which may be a Flash memory (Flash) die, a Static Random Access Memory (SRAM) die, a low power Double Data Rate (DDR) die, or the like. Although not shown, the device die 20 may be a single memory die or stacked memory dies. Likewise, device die 20 may also include a semiconductor substrate, where active devices such as transistors and/or diodes are formed on a top surface of the semiconductor substrate. Also, metal lines and vias (not shown) are formed in the interconnect structure of device die 20 to interconnect the integrated circuit devices in device die 20. The back surface of device die 20 may also be the back surface of a semiconductor substrate in device die 20.

Fig. 11 shows an exemplary top view of device die 10 and corresponding overlying device die 20 and vias 14. In some exemplary embodiments, device die 20 overlaps corner regions of device die 10, and vias 14 are adjacent to both sidewalls of device die 20. According to an alternative embodiment, device die 20 overlaps a central region of device die 10, and via 14 surrounds device die 20. Device die 20 and vias 14 may also be laid out using other layout schemes.

The DAF22 is an adhesive film, and may be formed of a polymer. According to some embodiments of the invention, the DAF22 has a low thermal conductivity, which may be lower than about 0.5W/m × K.

Referring back to fig. 1D, device die 20 includes conductive pillars 28, which may be metal pillars formed in surface dielectric layer 26. The metal posts 28 may be formed of copper, nickel, palladium, gold, multilayers thereof, and/or alloys thereof. The surface dielectric layer 26 may be formed of Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The underlying metal pillar 28 may be located at the metal pad 24, which may be formed of copper, aluminum, or other metal.

Referring to fig. 1E, encapsulation material 30 is encapsulated over device die 20 and vias 14. The corresponding step is illustrated as step 206 of the process step shown in fig. 12. The potting material 30 is dispensed as a fluid and then compressed and cured (e.g., in a thermal curing process). Encapsulation material 30 fills the gap between device die 20 and vias 14. The encapsulation material 30 may include a molding compound, a molded underfill, an epoxy, or a resin. After the encapsulation process, the top surface of the encapsulation material 30 is higher than the top ends of the metal posts 28 and vias 12.

Next, a planarization step, such as mechanical grinding, Chemical Mechanical Polishing (CMP), and/or combinations thereof, is performed to planarize the encapsulation material 30, the vias 14, the surface dielectric layer 26, and the metal posts 28. The corresponding step is illustrated as step 206 in the process step shown in fig. 12. The resulting structure is also shown in FIG. 1E. Due to the planarization, the top surface of the via 14 is flush (coplanar) with the top surface of the metal pillar 28, and flush (coplanar) with the top surface of the encapsulation material 30.

Referring to fig. 1F, one or more dielectric layers 32 and respective redistribution layers (RD L) 34 are formed over the encapsulation material 30, the vias 14, and the metal pillars 28, the corresponding steps are illustrated as step 208 of the process steps shown in fig. 12, the dielectric layers 32 are formed of a polymer such as PBO, polyimide, BCB, and the like, in accordance with some embodiments of the present invention.

RD L is formed in electrical connection with metal pillars 28 and vias 14 note that the example throughout all of fig. RD L is schematic, for example RD L may actually be patterned into a plurality of discrete portions separated from each other by respective dielectric layers, each of the discrete portions in RD L is connected to a respective underlying metal pillar 28 and/or via 14. RD L may also interconnect some of metal pillars 28 with a respective via 14. RD L34 may include metal traces (metal lines) and vias located below and connected with the metal traces.

Fig. 1G shows the back side grinding of device die 10 from the back side (bottom side of the example) of device die 10. The corresponding step is illustrated in step 210 of the process steps shown in fig. 12. Thus, as shown in fig. 1G, device die 10 has a thickness that decreases from thickness T1 (fig. 1F) to thickness T2.

FIG. 1H illustrates the formation of an electrical connector 36 according to some exemplary embodiments of the invention, the corresponding steps are illustrated as step 212 in the process steps shown in FIG. 12. the electrical connector 36 is electrically connected to RD L, metal post 28, and/or via 14. the formation of the electrical connector 36 may include placing a solder ball over RD L34 and then reflowing the solder ball. according to an alternative embodiment of the invention, the formation of the electrical connector 36 includes performing a plating step to form a solder land over RD L34 and then reflowing the solder ball. the electrical connector 36 may also include a metal post, or a metal post and a solder cap, which may also be formed by plating.

Additionally, an Integrated Passive Device (IPD)39 may be bonded to RD L. IPD39 may be used to tune the performance of the resulting package and may include, for example, a capacitor according to some alternative embodiments, no IPD39 is bonded throughout the description, the structure including the combination of device dies 10 and 20, vias 14, encapsulation material 30, RD L34, and dielectric layer 32 will be referred to as a composite wafer 38, and composite wafer 38 may be a composite wafer including multiple device dies 10 and 20.

In a subsequent step, composite wafer 38 is sawed into a plurality of packages 40, each package including one of device dies 10, one of device dies 20, and a respective via 14. The corresponding step is illustrated as step 214 in the process step shown in fig. 12. Package 40 is thus formed in a separate packaging (molding) process, although package 40 includes two layers of device dies stacked together, according to some embodiments. This is in contrast to conventional device stacking processes that use a two-package process to package two-layered device dies. In addition, a package substrate is not used in the package 40. This results in an advantageous reduction in the thickness of package 40, and thus package 40 is suitable for mobile applications requiring very thin packages.

According to some embodiments, although package 40 is a fan-out package, because RD L extends beyond the edge of device die 20, the footprint (top view area) of package 40 is as large as the top view area of device die 10, provided that the top view area of device die 10 is suitable for placement of all electrical connectors 36.

Also, device die 10, which may be a logic die, typically generates more heat than a memory die, such as device die 20. Memory die suffer from severe performance degradation due to heat. In accordance with some embodiments of the present invention, DAF22, which has a low thermal conductivity coefficient, is used to reduce the heat generated by device die 10 while avoiding directing the heat to device die 20. Instead, heat in device die 10 may be conducted through vias 14 to electrical connectors 36. Some of vias 14 may also be designed as dummy vias that are not used for electrical connection between device die 10 and electrical connectors 36. The dummy vias 14 may be electrically floating and serve to conduct heat in the die device 10 to the electrical connectors 36.

Fig. 2A-4J illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments. Unless otherwise specified, the materials and methods of formation of these components are substantially the same as those indicated by like reference numerals in the embodiment illustrated in FIG. 1A. Thus, details regarding the formation processes and materials of the components illustrated in fig. 2A through 4J (and the embodiments of fig. 5 through 10) may be found or appreciated from the discussion of the embodiments illustrated in fig. 1A through 1H.

Fig. 2A and 2B illustrate initial steps of some embodiments, which are substantially the same as the process steps illustrated in fig. 1A-1C. Vias 14 are formed over metal pads 12 of device die 10. Next, the wafer 2 is sawed into individual device dies 10.

Referring to fig. 2C, device die 10 is adhered to carrier 46 by an adhesive film. According to some embodiments of the present invention, carrier 46 is a glass carrier. Although one device die 10 is shown, there are multiple device dies 10 disposed on a carrier 46, and the device dies 10 may be arranged in an array. Device die 20 is then adhered to the front surface of die 10 by DAF22, as shown in fig. 2D. In a subsequent step, as shown in fig. 2E, encapsulation material 30 is dispensed to encapsulate device dies 10 and 20. Unlike the embodiment shown in fig. 1E, device die 10 is also packaged. Unlike the embodiment shown in fig. 1E, device die 10 is also packaged. Because the packaging of device dies 10 and 20 is accomplished in a single packaging process, there is no discernible interface between the upper portion of the packaging material (used to package device die 20) and the lower portion (used to package device die 10).

In a subsequent step, as shown in FIG. 2F, dielectric layer 32 and RD L34 are formed over encapsulation material 34, and RD L34 is electrically connected to metal pillars 28 and vias 14, RD L34 expands beyond the edges of device dies 10 and 20 according to some exemplary embodiments, therefore, the embodiment shown in FIG. 2F (as compared to FIG. 1F) may not be used for embodiments where the top view area of device die 10 is large enough to accommodate all of electrical connectors 36 (FIG. 2I), and thus RD L34 fan-out from device die 10 is required.

Carrier 46 is then stripped from the overlying structure to form the structure shown in fig. 2G, backside grinding is then performed to remove adhesive film 14 and thin device die 10, and thus the resulting structure is shown in fig. 2H, in fig. 2I IPD39 may (or may not) be bonded to RD L34, the resulting composite wafer 38 is sawn into individual packages 40, composite wafer 38 including device die 10, device die 20, encapsulation material 30, vias 14, RD L34 and dielectric layer 32.

Fig. 3A through 3J illustrate the formation of a fan-out package 40 according to some embodiments. Referring to fig. 3A, a wafer 4 is formed, wafer 4 including device dies 20 in wafer 4. Conductive pads (such as metal pads) 24 are formed at the front surface 20A of the device die 20. Device die 20 has a back surface 20B, which back surface 20B may be the back surface of each semiconductor substrate in device die 20. Next, referring to fig. 3B, a via 14 is formed, wherein the forming process may be similar to the process shown in fig. 1B and 1C. The wafer 4 is then sawed into individual device dies 20.

Referring to fig. 3C, device die 20 (including 20-1 and 20-2) is picked up and placed onto carrier 46 and overlying adhesive film 44. adhesive layer 44 may be formed of photo-thermal conversion (L THC) material. additionally, DAF 50 may be used to adhere device die 20 to adhesive film 44. the distance between device die 20-1 and 20-2 is selected such that the distance between vias 14 above device die 20-1 and vias 14 above device die 20-2 is large enough to accommodate device die 10 (fig. 3D.) according to some embodiments of the invention, device die 20-1 and 20-2 are identical to each other and device die 20-1 is rotated 180 degrees relative to device die 20-2. according to alternative embodiments, device die 20-1 and 20-2 are partially identical to each other, lower portion 20-1-L (of device die 20-1) such as active devices and interconnect structures (not shown) and lower portion 20-2-L of device 20-2 (of device die 20-1) and lower portion 20-2 such as active devices and interconnect structures (not shown) such as a multi-die 20-2-a multi-die-chip-stacked with a single chip-die 20, such as a multi-die-2-integrated chip, and a multi-die 20, such as a multi-die 20-2-die-2, which may be used in a multi-die-2-integrated chip stacked-die-chip stacked-die, and may include a multi-die-integrated chip-die-2-die-2-integrated chip (not shown, and may be used in accordance with a multi-die.

Next, referring to fig. 3D, device 10 is placed over device die 20 and adhered to the front surface of device die 20 by DAF 22. A portion of device die 10 also overlaps the gap between device die 20. According to some embodiments, device die 10 includes metal pillars 52 over metal pads 12, and no dielectric layer surrounds metal pillars 52. According to an alternative embodiment, there is a dielectric layer at the same horizontal level as metal pillars 52, and the dielectric layer surrounds metal pillars 52. According to still further alternative embodiments, no metal pillar is formed over metal pad 12, and metal pad 12 is the top conductive component of device die 10.

Fig. 3E shows device dies 10 and 20 and vias 14 encapsulated in encapsulation material 30, then mechanically ground, Chemically Mechanically Polished (CMP), and/or a combination thereof to expose metal pillars 52 and vias 14 in a subsequent step, dielectric layer 32 and RD L34 are formed, RD L34 is electrically connected to metal pillars 52 and vias 14, as shown in fig. 3F, then device die 41 may optionally be bonded to RD L34 (fig. 3G), and electrical connectors 36 are formed to connect to RD L34 (fig. 3H), device die 41 may include vias (also sometimes referred to as through-silicon vias or through-substrate vias) through the semiconductor substrate in device die 41, IPD may also be bonded to RD L34 according to some embodiments electrical connectors 36 may include a ball grid array for soldering to a Printed Circuit Board (PCB), electrical connectors 36 may also be flip-chip bumps such as C4 solder bumps, copper pillar bumps, etc. for bonding to a package substrate (not shown).

The carrier 46 is then stripped from the overlying structure and the final structure is shown in fig. 3I. In subsequent steps, device dies 20-1 and 20-2 are ground from the backside and DAF 50 is removed by grinding. Fig. 3J shows the resulting structure. Fig. 3J further illustrates the attachment of the lid 54 to the device die 20, for example, by a Thermal Interface Material (TIM) 56. The thermal conductivity coefficient of the TIM56 is greater than that of the DAF22 (FIGS. 1I, 2I, and 3J). For example, the thermal conductivity coefficient of the TIM56 may be higher than about 1W/m × K or even higher. The cover 54 may be formed of a material having a good thermal conductivity coefficient. According to some exemplary embodiments, the cover 54 comprises a metal such as aluminum, copper, aluminum/copper alloy, stainless steel, or the like.

Fig. 4A through 4J illustrate the formation of a package 40 (fig. 4J) according to some embodiments. These embodiments are substantially the same as the embodiments shown in fig. 3A through 3J, except that device die 10 does not have metal pillars 52 formed over metal pads 12 (fig. 3J). A brief discussion of the formation process is provided below. Details of these embodiments may be found in the embodiments of fig. 3A through 3J and are not repeated here.

The steps shown in fig. 4A to 4C are substantially the same as those shown in fig. 3A to 3C. Next, as shown in fig. 4D, device die 10 is adhered to device die 20 (including 20-1 and 20-2). Device die 10 includes metal pads 12 as top surface conductive features, and no metal pillars are formed over metal pads 12. Device 10 is also placed between via 14 directly over device die 20-1 and via 14 directly over device die 20-2.

Fig. 4E shows the direct formation of encapsulation material 30 without planarization exposing metal pads 12 and vias 14. The process steps illustrated in fig. 4F to 4J are substantially the same as those illustrated in fig. 3F to 3J, and thus, the details are not repeated here.

Fig. 5 through 10 illustrate packages formed according to some embodiments of the invention the formation process may be understood from the embodiments in fig. 1A through 4J the package 40 illustrated in fig. 5 is similar to the package illustrated in fig. 1I except that in fig. 5, no metal pillars are formed and the metal pads 24 are the top conductive components of the die 20. RD L34 includes vias that are in physical contact with the metal pads 24.

Package 40 shown in fig. 6 is similar to the package shown in fig. 2I, except that in fig. 6, no metal pillars are formed and metal pad 24 is the top conductive component of die 20. RD L34 includes vias in physical contact with metal pad 24.

Fig. 7 shows a package 40 that is similar to package 40 in fig. 2I, except that device die 20 is partially offset relative to device die 10. Due to the partial offset, the first portion of device die 20 overlaps a portion of encapsulation material 30 and does not overlap any portion of device die 10. The second portion of device die 20 overlaps a portion of the device die. Thus, the first portion of device die 20 is suspended without the underlying support of device 10. The partial offset of device die 20 relative to device die 10 advantageously reduces the overlap area of device dies 10 and 20. Thus, an increased percentage of the top surface area of device die 10 can be used to form metal pads 12 and vias 14, rather than overlapping device die 20. However, according to some embodiments, the offset of device die 20 from device die 10 does not result in an undesirable increase in the form factor (top view area) of package 40. For example, when the top view area of package 40 is determined by the area required to accommodate all electrical connectors 36, a partial offset of device die 20 relative to device die 10 will not result in an increase in form factor (top view area) as long as the total footprint of device dies 10 and 20 does not exceed the area required to accommodate all electrical connectors 36. Fig. 8 shows a package 40 similar to that shown in fig. 7, except that no metal posts are formed over the metal pads 24.

Fig. 9 illustrates a package 40 according to some embodiments, where there are two device dies 10 and two device dies 20 that are partially offset with respect to respective device dies 10. Each device die 10 has a first portion that overlaps a portion of a respective underlying device die 20 and has a second portion that is offset relative to the respective underlying device die 20. Vias 14 are formed directly on metal pads 24 of each of device dies 20.

Fig. 10 illustrates a package 40 in which there are four device dies 20 (including 20-3 and 20-4) and one device die 10, according to some embodiments. The four device dies 20 include two higher level device dies 20-4 and two lower level device dies 20-3 located below the two higher level device dies 20-4. Each of the higher level device dies 20-4 has a first portion that overlaps a portion of the respective lower level device die 20-3 and has a second portion that is offset relative to the respective lower level device die 20-3. Four device dies 20 are encapsulated in a first encapsulation material 30A in a first encapsulation process.

Device die 10 is located above a higher level device die 20-4 and is encapsulated in a second encapsulation material 30B in a second encapsulation process. Device die 10 is offset relative to the two higher level device die portions. For example, device die 10 has a first portion that overlaps portions of higher level device dies 20-4, and a second portion that overlaps gaps between higher level device dies 20-4.

The encapsulating

materials

30A and 30B may be the same as each other or different from each other. Via 14A is formed directly on metal pad 24A of lower level device die 20-3. Some of the vias 14B are formed directly on the metal pads 24B of the higher level device die 20-4. As a result of CMP of the top surface of encapsulation material 30A, the interfaces of

encapsulation materials

30A and 30B may be discernible from one another, which results in some of the spherical filler 58 in encapsulation material 30 being ground to have a flat (rather than spherical) top surface. On the other hand, the spherical filler 60 in the encapsulating material 30B and in contact with the encapsulating material 30A is kept to have a circular shape. Also, due to the nature of the formation process of

vias

14A and 14B, each of

vias

14A and 14B has a top width that is greater than the respective bottom width. The transition of the vias 14B to the respective underlying vias 14A will also exhibit discontinuities, and the top width of the vias 14A may be greater than the bottom width of the respective overlying vias 14B.

In fig. 9 and 10, the offset of the higher level die relative to the lower level die results in an advantageous growth in the surface area of the lower level die 20-3, where the surface area of the lower level die 20-3 can be used to form metal pads and vias. On the other hand, the warpage of the package is not severe because the lower level of die 20-3 occupies most of the top view area of package 40.

Fig. 13A, 13B and 13C illustrate the structure of a top conductive feature in a device die in some embodiments according to the invention. Referring to fig. 13A, a device die S1 is shown. According to some embodiments, device die S1 is a logic die having a GPU die, a CPU die, a GPU-CPU combined function die, an MCU die, an IO die, a BB die, or an AP die. Although not shown, device die S1 may include a semiconductor substrate, which may be a silicon substrate according to some embodiments, with active elements (not shown), such as transistors and/or diodes, formed at a top surface of the semiconductor substrate. Also, metal lines and vias (not shown) are formed in interconnect structures (not shown) that are located above the semiconductor substrate to interconnect the integrated circuit devices in device die S1.

Metal pads 104 are formed in device die S1. According to some embodiments of the invention, metal pads 104 are aluminum pads, but may also include some copper therein. Metal pads 104 are electrically connected to integrated circuit devices, such as active devices, in device die S1.

The passivation layer 106 is formed to have portions covering edge portions of the metal pad 104. A central portion of metal pad 104 is exposed through an opening in passivation layer 106. The passivation layer 106 may be a single layer or a composite layer, and may be formed of a non-porous material. According to some embodiments of the present invention, the passivation layer 106 is a composite layer including a silicon oxide layer (not shown) and a silicon nitride layer (not shown) over the silicon oxide layer. The passivation layer 106 may also be formed of other non-porous dielectric materials, such as Undoped Silicate Glass (USG), silicon oxynitride, and the like.

A dielectric layer 108 is formed over the passivation layer 106. The dielectric layer 108 may be a polymer layer formed of a polymer such as polyimide, PBO, BCB, or the like. The formation method of the dielectric layer 108 may include, for example, spin coating. The dielectric layer 108 may be dispensed in liquid form and then cured. Above the dielectric layer 108 may reside a dielectric layer 110, the dielectric layer 110 may be formed of a material selected from the same candidate materials used to form the dielectric layer 108, which may include polyimide, PBO, BCB, and the like. According to some embodiments, the

dielectric layers

108 and 110 are formed of different materials. For example, the dielectric material 108 may be formed of polyimide, while the dielectric layer 110 may be formed of PBO.

Conductive posts 112 are formed over metal pads 104 and connected to metal pads 104. The conductive posts 112 are also sometimes referred to as metal posts or metal posts. According to some embodiments, the conductive posts 112 are formed of a metallic material such as copper, nickel, gold, alloys thereof, or multilayers thereof. Conductive posts 112 extend into

dielectric layers

106, 108, and 110. According to some embodiments, the dielectric layer 110 includes a portion that covers the metal posts 112. After molding device die S1, the portion of dielectric layer 110 overlying metal posts 112 may be removed in a grinding process, which will be discussed in subsequent processes.

Fig. 13B schematically illustrates the structure of a top conductive element in a device die S1 according to some alternative embodiments in some embodiments, the top element of the device die S1 includes a metal pad 104 and a passivation layer 106, wherein a central portion of the metal pad 104 is exposed.

Fig. 13C schematically illustrates the structure of a top conductive feature in a device die S1 in accordance with an alternative embodiment. The device die S1 according to these embodiments is similar to the device die shown in fig. 13A, except that the dielectric layer 110 in fig. 13A is omitted in fig. 13C. Thus, dielectric layer 108, which is the top dielectric layer in device die S1, has a top surface that is lower than the top surface of metal posts 112.

Fig. 14 shows a symbolic view of device die S1. Throughout the description, when device die S1 shown in fig. 14 is illustrated, the illustrated device die D1 may actually have a structure as shown in any of fig. 13A, 13B, or 13C. For example, the conductive features 114 illustrated in the device die S1 may represent the metal pillars 112 in fig. 13A or 13C, or the metal pads 114 in fig. 13B. Also, the dielectric layer 116 illustrated in fig. 14 may represent the

dielectric layers

106, 108, and 110 in fig. 13A, the dielectric layer 106 in fig. 13B, or the

dielectric layers

106 and 108 in fig. 13C.

Fig. 15A-15J illustrate cross-sectional views of intermediate stages of forming a fan-out package, according to some embodiments. Referring to fig. 15A, a wafer 120 is formed. Wafer 120 includes a plurality of device dies M1 therein. According to some embodiments of the invention, device die M1 is a logic die that includes logic circuits, memory die, analog die, sensor die, and the like. For example, when device die M1 is a memory die, device die M1 may be a flash memory die, an SRAM memory die, a low power DDR die, or the like. Although not shown, the device die M1 may include a semiconductor substrate with active devices, such as transistors and/or diodes, formed on a top surface of the semiconductor substrate. Also, metal lines and vias (not shown) are formed in the interconnect structure of device die M1 to interconnect the integrated circuit devices in the respective device die M1. The back side of device die M1 may also be the back side of the semiconductor substrate in the respective device die M1. Also, the back side of device die M1 is adhered to DAF 22.

Metal pads 122 are formed on the top (front) surface of device die M1. The metal pads 122 may be aluminum pads, copper pads, aluminum copper pads, etc. In each of device dies M1, metal pads 122 may be offset with respect to respective device dies M1. For example, metal pads 122 may be formed on the illustrated left side of the respective device die M1, while the right side of device die M1 has no metal pads formed therein.

Vias 124 are formed on the top surface of device die M1. The corresponding step is illustrated as step 302 in the process flow 300 shown in fig. 19. According to some embodiments of the present invention, vias 124 are formed using similar methods as illustrated in fig. 1B and 1C. Also, the material of the via 123 may be selected from the same candidate materials used to form the via in fig. 1C. Thus, the details are not repeated here. Because the vias 124 are formed in a single formation process (e.g., plating) and each of the vias 124 is formed in a single opening (similar to opening 15 in fig. 1B), there is no visible interface between the upper portion and the corresponding lower portion of the vias 124. Also, the edge of each of the through holes 124 may be substantially straight, and the inclination angle of the edge is not abrupt. The side profile of the through-hole 124 may be vertical or tapered, and the top view cross-sectional shape of the through-hole 124 may be circular and/or non-circular, such as oval, hexagonal, octagonal, and the like. For the sake of simplicity, the components discussed for the vias 124 are applicable to all other vias throughout the present invention.

According to some embodiments of the present invention, vias 124 are formed directly on metal pads 122. thus, a seed layer may or may not be used for the formation of vias 124, and the material of vias 124 is homogenous according to an alternative embodiment, RD L (not shown) may be formed proximate to the top surface of device die M1, where RD L is used to reroute electrical connections, e.g., to the left side of the respective device die M1. vias 124 are then formed on top of RD L. in subsequent steps, device die M1 is separated from wafer 120 into discrete device dies.

Fig. 15B illustrates the formation of wafer 128, wafer 128 including device die M2 in wafer 128. According to some embodiments, device dies M1 and M2 are the same type of device die. For example, device dies M1 and M2 may both be SRAM dies. Also, device dies M1 and M2 may have the same structure at the bottom. For example, the structure and layout of device dies M1 and M2, including a low-k dielectric layer (not shown), metal lines and vias (not shown) in the low-k dielectric layer, transistors, and memory devices (not shown), may be identical to each other. The top wire portions of device die M1 may be different from the top wire portions of device die M2 such that electrical connections of device die M2 are routed to the right side of the respective device die M2 opposite device die M1.

The back side of device die M2 may also be adhered to DAF 22. Device die M2 also has metal pads 122 formed in device die M2. Vias 124 are formed over metal pads 122, for example, by plating. The corresponding step is illustrated as step 304 in the process flow 300 shown in fig. 19. The material and formation process of metal pad 122 may be found in reference to the discussion of fig. 15A and thus will not be repeated here. Device die M2 is then separated from wafer 128 into discrete device dies.

Referring to fig. 15C, a wafer 130 is formed. Wafer 130 includes a plurality of device dies M3 in wafer 130. According to some embodiments of the invention, device die M3 is a logic die that includes logic circuits, memory die, analog die, sensor die, and the like. When device die M3 is a memory die, device die M3 may be a flash memory die, an SRAM memory die, a low power DDR die, or the like. Additionally, device die M3 may have the same or different structure as device die M1 and/or M2.

Metal pads 132 are formed at the top surface (front surface) of device die M3 and may be aluminum pads, copper pads, aluminum copper pads, or the like. Similar to device die M1, metal pads 132 may also be offset with respect to the center of respective device die M3. For example, metal pads 132 may be formed in the illustrated left side of the respective device die M3, while the right side of device die M3 has no metal pads formed therein.

Vias 134 are formed on the top surface of device die M3 and may be formed using similar methods (and similar materials) as shown in fig. 1B and 1C corresponding steps are illustrated as step 306 in process flow 300 shown in fig. 19 according to some embodiments of the present invention, vias 134 are formed directly on metal pads 132 accordingly, a seed layer may or may not be used in the formation of vias 134 according to an alternative embodiment, RD L (not shown) is formed proximate to the top surface of device die M3, where RD L is used to reroute electrical connections, such as the left side of the respective device die M3, then vias 134 are formed over rerouted RD L device die M3 is separated from wafer 130 into discrete device dies.

Fig. 15D illustrates the formation of wafer 138, wafer 138 including device die M4 in wafer 138. According to some embodiments, device dies M3 and M4 are the same type of device die. Also, the relationship between device dies M3 and M4 is similar to the relationship between device dies M1 and M2. The back side of device die M4 may also be adhered to DAF 22. Device die M4 also has metal pads 132 formed in device die M4. A via 134 is formed on metal pad 132. The corresponding step is illustrated as step 308 in the process flow 300 shown in fig. 19. The materials and formation processes of metal pad 132 and via 134 may be found in reference to the discussion of fig. 15A and thus will not be repeated here. Device die M4 is then singulated from wafer 138 into discrete device dies.

Next, referring to fig. 15E, device dies M1 and M2 are picked up and placed over adhesive film 44, which adhesive film 44 is positioned over carrier 46 (e.g., a glass carrier). The corresponding step is illustrated as step 310 in the process flow 300 shown in fig. 19. Device die M1 is placed to the left of device die M2 and further vias 124 in device die M1 are located to the left of device die M1. Further, via 124 in device die M2 is located to the right of device die M2. The device dies M1 and M2 are separated from each other by a distance D1.

Next, as shown in fig. 15F, device dies M3 and M4 are picked up and placed and adhered to the front sides of device dies M1 and M2, respectively, by DAF 22. The corresponding step is illustrated as step 312 in the process flow 300 shown in fig. 19. According to some embodiments of the present invention, device die M3 overlaps the right portion of the respective underlying device die M1, and may or may not overlap the center of device die M1 or the center of device die M1. Also, the vias 134 of device die M3 are on the left side of the respective device die M2. Device die M4 overlaps the left portion of the respective underlying device die M2, and may or may not overlap the center of device die M2 or the center of device die M2. Also, the vias 134 of device die M4 are to the right of the respective device die M4.

According to some embodiments of the invention, device die M3 has a right portion that extends beyond the right edge of device die M1. The right portion of device die M3 overhangs. According to an alternative embodiment of the present invention, the entirety of device die M3 overlaps device die M1 and does not overhang. The device dies M3 and M4 have a distance D2, and the distance D2 may be less than, equal to, or greater than the distance D1 between the device dies M1 and M2.

Next, referring to fig. 15G, device die S1 is picked and placed over device dies M3 and M4 and adhered to the front surfaces of the two device dies M3 and M4 by DAF 22. The corresponding step is illustrated as step 314 in the process flow 300 shown in fig. 19. A portion of the device die S1 also overlaps the gap between the device dies M3 and M4. According to some embodiments of the invention, as shown in fig. 14, device die S1 includes conductive features 114 and surface dielectric layer 116, which represent the features shown in fig. 13A, 13B, or 13C. According to some embodiments, the top surfaces of

vias

124 and 134 are higher or lower than the top surface of device die S1, or flush with the top surface of device die S1.

Fig. 15H shows the encapsulation of device dies M1, M2, M3, M4, S1 and vias 124 and 134 in encapsulation material 30, followed by mechanical polishing, CMP, and/or a combination thereof to expose conductive features 114 and vias 124 and 134. The corresponding step is illustrated as step 316 in the process flow 300 shown in fig. 19. Because device dies M1, M2, M3, M4, S1 and vias 124 and 134 are encapsulated by a single encapsulation process, there are no identifiable interfaces (e.g., horizontal interfaces) in encapsulation material 30. For example, the filler in the encapsulation material 30 (which may include spherical particles (such as Al) may be because a single planarization process is performed on the top surface of the encapsulation material 30 and thus no grinding is performed on the lower portion of the encapsulation material 30₂O₃Particles) will remain spherical. However, the spherical particles that are ground (be ground) in the planarization process of the encapsulation material 30 will have an upper portion that is removed during the grinding process and a bottom portion that remains with a flat top surface and a rounded bottom surface.

As shown in fig. 15H, each of device dies M3, M4, and S1 may include a first portion that overlaps a respective underlying die M1/M2, and M3/M4, respectively, and a second portion that overlaps encapsulation material 30. The second portion may not have any device die directly under the second portion. Due to the stacking, the height of the vias of device dies M3 and M4 is less than the height of the vias of device dies M1 and M2.

In subsequent steps, dielectric layer 32 and RD L34 are formed, and RD L34 is electrically connected to conductive element 114 and vias 124 and 134, as shown in FIG. 15I, corresponding steps are illustrated as step 318 in process flow 300 shown in FIG. 19, then, device die C1 may be optionally bonded to RD L34 (FIG. 15J) by, for example, flip-chip bonding, hybrid bonding, or surface mounting, device die C1 may be an Integrated Passive Device (IPD), memory die, Application Specific Integrated Circuit (ASIC) die, etc., device die C1 may include vias (sometimes referred to as through-silicon vias or through-substrate vias) through the semiconductor substrate in device die C1, the IPD may also be bonded to RD L34, then, with reference to FIG. 15K, electrical connectors 36 are formed to connect with RD L34, corresponding steps are illustrated as step 320 in process flow 300 shown in FIG. 19.

The carrier 46 is then peeled away from the structure above and the final structure is shown in fig. 15K. In subsequent steps, the heat spreading lid 54 is adhered to the final package, for example, by TIM 56. The corresponding step is illustrated as step 322 in the process flow 300 shown in fig. 19. The heat dissipation cover 54 may be formed of a material having a good thermal conductivity coefficient. According to some exemplary embodiments, the heat sink cap 54 comprises a metal such as aluminum, copper, aluminum/copper alloy, stainless steel, or the like. Thus forming package 40.

Fig. 16A and 16B illustrate cross-sectional and top views, respectively, of a multi-layer fan-out package 40 according to some embodiments. These embodiments are similar to those of fig. 15K, except that device dies M3 and M4 are laid out differently than in fig. 15K. The formation process of the package 40 shown in fig. 16A and 16B is substantially the same as that shown in fig. 15A to 15K, and thus is not repeated here.

Referring to fig. 16B, a first line 140 interconnecting the centers of device dies M1 and M2 is in the X direction. A second straight line 142 interconnecting the centers of device dies M3 and M4 is in the Y direction. Thus, the alignment direction of device dies M1 and M2 is perpendicular to the alignment direction of device dies M3 and M4. An advantageous feature of this layout is that less of device dies M3 and M4 overlap device dies M1 and M2, which provides more surface area of device dies M1 and M2 for forming vias 124. Also, this configuration may result in a symmetrical package layout for better warpage control and mechanical reliability/stability. Fig. 16A shows a cross-sectional view of package 40, where the cross-sectional view is taken along the line 16A-16A in fig. 16B.

In contrast, in the embodiment shown in fig. 15A, in the top view (not shown) of package 40 shown in fig. 15K, a first line (not shown) interconnecting the centers of device dies M1 and M2 may be parallel to a second line (not shown) interconnecting the centers of device dies M1 and M2.

Fig. 17A and 17B illustrate cross-sectional and top views, respectively, of a multi-layer fan-out package 40 according to some embodiments. These embodiments are similar to the embodiments in fig. 16A and 16B, except that additional device dies S2 and/or S3 are disposed to overlap device dies M3 and M4, respectively. The formation process of the package 40 shown in fig. 17A and 17B is substantially similar to that shown in fig. 15A to 15K, and thus is not repeated here. Each of device dies S2 and S3 may be a logic die, a memory die, an IPD, etc. Also, the top conductive features of the device dies S2 and S3 may be selected from any of the structures shown in fig. 13A, 13B, and 13C.

Fig. 18A, 18B, and 18C illustrate a fan-out package 40 according to some embodiments. These embodiments are similar to the embodiment shown in fig. 1I, except that device die 20 in fig. 1I is replaced by a device cube in fig. 18A, 18B, and 18C. In fig. 18A, vias 14 are distributed on opposite sides of device cube 144. In fig. 18B, vias 14 are distributed on one side (e.g., the right side as shown) of device cube 144, rather than the opposite side. Also, as shown in fig. 18A and 18B, the entire device cube 144 overlaps device die S1. In fig. 18C, vias 14 are distributed on one side (e.g., the right side as shown) of device cube 144 rather than the opposite side. Also, as shown in fig. 18C, device cube 144 extends beyond the left edge of device die S1 to overlap encapsulation material 30, thus providing more space for forming metal pads 12 and vias 14.

In fig. 18A, 18B, and 18C, each of device cubes 144 includes a plurality of device dies MC1, which may be device dies according to some embodiments. The device die MC1 may have the same or different structure and vias (not shown) penetrate the semiconductor substrate therein. The top conductive features of the memory cube 144 may also take any of the configurations shown in FIGS. 13A, 13B, and 13C. The device cube 144 may include stacked multiple chips, for example, 2 chips to 9 chips. In each stacked structure, all of the stacked chips may be homogeneous functional chips such as memory functional chips and/or heterogeneous functional chips such as logic functional controller chips and a plurality of homogeneous memory chips (not shown). The stacked chips may have through-silicon vias (TSVs) depending on design needs and may form, for example, High Bandwidth Memory (HBM) cubes.

Embodiments of the present invention have some advantageous features. By forming the via directly on the metal pad of the lower die without using a package substrate, the resulting package is thin. The thermal decoupling of the logic die and the memory die by using the ADF prevents the memory die from degrading due to heat generated in the logic die. The top view area of the package is minimized. The upper level die and the lower level die may be packaged by the same packaging process and thus reduce the cost and warpage of the package.

According to some embodiments of the invention, a method includes forming a first via from a first conductive pad of a first device die and forming a second via from a second conductive pad of a second device die. The first and second conductive pads are at the top surfaces of the first and second device dies, respectively. The first and second conductive pads are used as seed layers. A second device die is adhered to the top surface of the first device die. The method also includes encapsulating the first device die and the second device die and the first and second vias in an encapsulation material, and encapsulating the first and second device dies and the first and second vias in the same encapsulation process. The encapsulation material is planarized to expose the first and second vias. A redistribution line is formed to be electrically connected to the first and second vias.

According to some embodiments of the present invention, a method includes forming a first via on a first conductive pad of a first device die, forming a second via on a second conductive pad of a second device die, placing the first device die and the second device die over a carrier, forming a third via on a third conductive pad of a third device die, and forming a fourth via on a fourth conductive pad of a fourth device die. The method also includes adhering a third device die and a fourth device die to the top surfaces of the first device die and the second device die, respectively, and simultaneously encapsulating the first, second, third, and fourth device dies and the first, second, third, and fourth vias in an encapsulation material. The encapsulation material is planarized to expose the first, second, third, and fourth vias. A redistribution line is formed over the first, second, third and fourth vias and electrically connected to the first, second, third and fourth vias.

According to some embodiments of the present invention, a method includes placing a first device die and a second device die over a carrier, where the first device die includes a first via and the second device die includes a second via. A third device die is disposed over the first device die. The third device die includes a first portion overlapping the gap between the first device die and the second device die, a second portion overlapping a portion of the first device die, and a third via higher than the first portion of the third device die. The first, second and third device dies and the first, second and third vias are encapsulated in an encapsulation material in the same encapsulation process. The encapsulation material is planarized to expose the first via, the second via, and the third via. The redistribution line is formed over and electrically connected to the first, second, and third vias.

In accordance with some embodiments of the present invention, a package includes a first device die, a first via having a first bottom surface in contact with a top surface of a first conductive pad of the first device die, a second device die, a portion of the second device die overlapping a portion of the first device die, and a second via. The second via includes a lower portion at a same level as the first device die and an upper portion at a same level as the second device die. The lower portion has a second bottom surface in contact with a top surface of a second conductive pad of the second device die. The top surface of the upper portion is coplanar with the top surface of the first through hole, and the lower portion is continuously connected to the upper portion with no discernible interface between the upper and lower portions. The package also includes an encapsulation material encapsulating the first device die, the second device die, the first via, and the second via therein, and a redistribution line over and electrically connected to the first via and the second via.

In the above method, all vias formed on the first device die are offset to one side of the first device die.

In the above method, further comprising adhering a third device die to the top surface of the second device die, wherein the third device die is encapsulated by the same encapsulation process and in the encapsulation material.

In the above method, the second device die includes a first portion overlapping a portion of the first device die and a second portion overlapping a portion of the encapsulation material.

In the above method, the third device die includes a first portion overlapping a portion of the second device die and a second portion overlapping an additional portion of the encapsulation material.

In the above method, the third device die includes an electrically conductive feature exposed after planarizing the encapsulation material, and the electrically conductive feature is a metal stud or a metal pad.

In the above method, the third device die includes an electrically conductive feature exposed after planarizing the encapsulation material, and a top surface of the electrically conductive feature is coplanar with a top surface of the first via and a top surface of the second via.

In the above method, the first through-hole has a straight edge continuously extending from a top surface to a bottom surface of the first through-hole.

In the above method, further comprising attaching a heat spreading cap to a bottom of the first device die and a bottom of the second device die.

In the above method, the first device die and the second device die are separated from each other by a first gap, and the third device die and the fourth device die are separated from each other by a second gap smaller than the first gap.

In the above method, a portion of the third device die overlaps a gap between the first device die and the second device die.

In the above method, further comprising: adhering a fifth device die to a top surface of the third device die and a top surface of the fourth device die, wherein the fifth device die is encapsulated by the encapsulation material.

In the above method, the fifth device die overlaps a gap between the third device die and the fourth device die.

In the above method, in a top view of the third device die and the fourth device die, a first line interconnecting a center of the third device die and a center of the fourth device die is perpendicular to a second line interconnecting a center of the first device die and a center of the second device die.

In the above package, the second device die further includes a second portion, and a bottom surface of the second portion is in contact with a top surface of the portion of the encapsulation material.

In the above package, further comprising a third device die overlapping a portion of the second device die, wherein a top surface of the third device die is coplanar with the top surface of the upper portion of the second via.

In the above package, the upper portion of the second via has a top surface that is coplanar with a top surface of the first via, and wherein the encapsulation material extends continuously from a top level to a bottom level, and the top level is coplanar with the top surface of the first via, and the bottom level is coplanar with a bottom surface of the first device die.

In the above package, further comprising an integrated passive device bonded to the redistribution line.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a fan-out package, comprising:

forming a first via from a first conductive pad of a first device die, wherein the first conductive pad is located at a top surface of the first device die;

forming a second via from a second conductive pad of a second device die, wherein the second conductive pad is located at a top surface of the second device die;

forming a third via from a third conductive pad of a third device die, wherein the third conductive pad is located at a top surface of the third device die;

forming a fourth via from a fourth conductive pad of a fourth device die, wherein the fourth conductive pad is located at a top surface of the fourth device die;

adhering the second device die and the fourth device die to top surfaces of the first device die and the third device die, respectively;

encapsulating the first, second, third, and fourth device dies and the first, second, third, and fourth vias in an encapsulation material, wherein the first, second, third, and fourth device dies and the first, second, third, and fourth vias are encapsulated in the same encapsulation process;

planarizing the encapsulation material to expose the first and second vias; and

forming a redistribution line over and electrically connected to the first via and the second via,

wherein, in a top view of the second device die and the fourth device die, a first line interconnecting a center of the second device die and a center of the fourth device die is perpendicular to a second line interconnecting a center of the first device die and a center of the third device die.

2. The method of claim 1, wherein all vias formed on the first device die are offset to one side of the first device die.

3. The method of claim 1, further comprising adhering a fifth device die to the top surface of the second device die, wherein the fifth device die is packaged by the same packaging process and in the packaging material.

4. The method of claim 3, wherein the second device die includes a first portion overlapping a portion of the first device die and a second portion overlapping a portion of the encapsulation material.

5. The method of claim 4, wherein the fifth device die includes a first portion overlapping a portion of the second device die and a second portion overlapping an additional portion of the encapsulation material.

6. The method of claim 3, wherein the fifth device die includes conductive features that are exposed after planarizing the encapsulation material, and the conductive features are metal posts or metal pads.

7. The method of claim 3, wherein the fifth device die includes an electrically conductive member exposed after planarizing the encapsulation material, and a top surface of the electrically conductive member is coplanar with a top surface of the first via and a top surface of the second via.

8. The method of claim 1, wherein the first via has a straight edge that extends continuously from a top surface to a bottom surface of the first via.

9. The method of claim 1, further comprising attaching a heat spreading cap to a bottom of the first device die.

10. A method of manufacturing a fan-out package, comprising:

forming a first via on a first conductive pad of a first device die;

forming a second via on a second conductive pad of a second device die;

placing the first device die and the second device die over a carrier;

forming a third via on a third conductive pad of a third device die; and

forming a fourth via on a fourth conductive pad of a fourth device die;

adhering the third device die and the fourth device die to a top surface of the first device die and a top surface of the second device die, respectively;

simultaneously encapsulating the first device die, the second device die, the third device die, and the fourth device die and the first via, the second via, the third via, and the fourth via in an encapsulation material;

planarizing the encapsulation material to expose the first, second, third, and fourth vias; and

forming redistribution lines over and electrically connected to the first, second, third, and fourth vias,

wherein, in a top view of the third device die and the fourth device die, a first line interconnecting a center of the third device die and a center of the fourth device die is perpendicular to a second line interconnecting a center of the first device die and a center of the second device die.

11. The method of claim 10, wherein the first device die and the second device die are separated from each other by a first gap, and the third device die and the fourth device die are separated from each other by a second gap that is smaller than the first gap.

12. The method of claim 10, wherein a portion of the third device die overlaps a gap between the first device die and the second device die.

13. The method of claim 10, further comprising:

adhering a fifth device die to a top surface of the third device die and a top surface of the fourth device die, wherein the fifth device die is encapsulated by the encapsulation material.

14. The method of claim 13, wherein the fifth device die overlaps a gap between the third device die and the fourth device die.

15. The method of claim 10, wherein the first via has a straight edge that extends continuously from a top surface to a bottom surface of the first via.

16. A package, comprising:

a first device die;

a first via having a first bottom surface in contact with a top surface of a first conductive pad of the first device die;

a second device die comprising a first portion overlapping a portion of the first device die;

wherein the first via hole includes:

a lower portion at a same level as the second device die, wherein a lower portion of the first via has the first bottom surface in contact with a top surface of a first conductive pad of the first device die; and

an upper portion above the second device die, wherein a lower portion of the first via is continuously connected to an upper portion of the first via and there is no discernible interface between the upper portion of the first via and the lower portion of the first via;

a third device die at the same level as the first device die;

a third via having a third bottom surface in contact with a top surface of a third conductive pad of the third device die;

a fourth device die comprising a first portion overlapping a portion of the third device die;

wherein the third through hole includes:

a lower portion at a same level as the fourth device die, wherein a lower portion of the third via has the third bottom surface in contact with a top surface of a third conductive pad of the third device die; and

an upper portion above the fourth device die, wherein a lower portion of the third via is continuously connected to an upper portion of the third via and there is no discernible interface between the upper portion of the third via and the lower portion of the third via;

an encapsulation material encapsulating the first device die, the second device die, the first via, and the third via in the encapsulation material;

a redistribution line over and electrically connected to the first via and the third via,

17. The package of claim 16, wherein the second device die further comprises a second portion, and a bottom surface of the second portion is in contact with a top surface of the portion of the encapsulation material.

18. The package of claim 16, further comprising a fifth device die overlapping a portion of the second device die, wherein a top surface of the fifth device die is coplanar with the top surface of the upper portion of the first via.

19. The package of claim 16, wherein the upper portion of the first via has a top surface that is coplanar with a top surface of a second via of the second device die, and wherein the encapsulation material extends continuously from a top level to a bottom level, and the top level is coplanar with the top surface of the first via and the bottom level is coplanar with a bottom surface of the first device die.

20. The package of claim 16, further comprising an integrated passive device bonded to the redistribution line.

21. A method of manufacturing a semiconductor device, comprising:

placing a first device die and a second device die over a carrier, wherein the first device die includes a first via and the second device die includes a second via;

placing a third device die over the first device die, wherein the third device die comprises:

a first portion overlapping a gap between the first device die and the second device die;

a second portion overlapping a portion of the first device die; and

a third via higher than the first portion of the third device die;

packaging the first, second, and third device dies and the first, second, and third vias in a packaging material in a same packaging process;

placing a fourth device die over the first device die and the second device die;

planarizing the encapsulation material to expose the first, second, and third vias; and

forming redistribution lines over and electrically connected to the first, second, and third vias,

22. The method of claim 21, further comprising forming the first via comprises:

forming a photoresist over the first device die;

patterning the photoresist to form an opening, and a portion of the conductive pad of the first device die is exposed to the opening;

plating a conductive material in the opening to form the first via; and

and removing the photoresist.

23. The method of claim 21, further comprising bonding an integrated passive device to the redistribution line.

24. The method of claim 21, wherein the encapsulation material is in contact with edges of the first, second, and third vias.

25. The method of claim 21, wherein the encapsulation material comprises a molding compound.