CN101364550A - Multi-chip stacking structure having silicon channel and preparation thereof - Google Patents

Multi-chip stacking structure having silicon channel and preparation thereof Download PDF

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Publication number
CN101364550A
CN101364550A CNA2007101402914A CN200710140291A CN101364550A CN 101364550 A CN101364550 A CN 101364550A CN A2007101402914 A CNA2007101402914 A CN A2007101402914A CN 200710140291 A CN200710140291 A CN 200710140291A CN 101364550 A CN101364550 A CN 101364550A
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China
Prior art keywords
chip
silicon passage
tool
metal column
stacking structure
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CNA2007101402914A
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Chinese (zh)
Inventor
江政嘉
黄建屏
张锦煌
邱启新
黄荣彬
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority to CNA2007101402914A priority Critical patent/CN101364550A/en
Publication of CN101364550A publication Critical patent/CN101364550A/en
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

The invention relates to a multi-chip stacking structure with a silicon channel and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a wafer comprising a plurality of first chips, forming a plurality of pores on a first surface of each first chip and forming a metal post and a soldering pad on each pore so as to form a silicon channel structure, forming at least one groove of the metal post which protrudes out of the silicon channel on a second surface of the first chip, stacking at least one second chip on the first chip, accommodating the second chip inside the groove and electronically connecting the second chip with the metal post of the silicon channel protruding out of the groove, filling an insulating material for coating the second chip inside the groove, arranging an electroconductive element on the soldering pad on the first surface of the first chip, cutting and picking up the wafer, and jointing the stacked second chip and the first chip via the electroconductive element and electronically connecting to a chip load-supporting element. The wafer which comprises a plurality of the first chips and is not subjected to integral thinning is used as a load-supporting frame, so as to avoid the problems in the prior art.

Description

The multi-chip stacking structure and the method for making thereof of tool silicon passage
Technical field
The present invention relates to a kind of semiconductor device and method for making thereof, refer to structure and method for making thereof that a kind of multicore sheet utilizes the silicon passage to pile up especially.
Background technology
Because communication, network, and the becoming more and more important of the compact trend of various Portable (Portable) electronic product such as computer and peripheral product thereof, and described electronic product is to develop towards multi-functional and high performance direction, to satisfy the package requirements of the high integration of semiconductor package part (Integration) and microminiaturized (Miniaturization), and for asking the performance (ability) that promotes single semiconductor package part and capacity (capacity) to meet miniaturization of electronic products, the trend of big capacity and high speed, prior art is with semiconductor package part multi-chip moduleization (Multi-chipModule; MCM) form presents, to connect the chip of putting more than at least two on the substrate of single packaging part.
The semiconductor package part of existing multi-chip moduleization is to arrange a plurality of chips in the horizontal interval mode on a substrate, and be electrically connected to this substrate by bonding wire, the semiconductor package part major defect of this kind multi-chip moduleization is, for avoiding the lead false touch of chip chamber, must come respectively this chip of gluing with certain interval, so if need a plurality of chip of gluing then to need to lay large-area chip connecting area territory (Die Attachment Area) to be installed with the chip of requirement on substrate, this measure will cause the increase of substrate usable floor area and processing procedure cost.
United States Patent (USP) the 6th in addition, 538, then openly first chip and second chip are spliced on substrate for No. 331 with folded crystal type (Stacked), respectively this chip that splices is relative lower floor's chip off normal (off-set) segment distance simultaneously, sets bonding wire respectively to this substrate to make things convenient for this first and second chip.
Though the technology that the method can be more aforementioned be arranged the multicore sheet in the horizontal interval mode is saved substrate space, but it still must utilize wire soldering technology to electrically connect chip and substrate, make between chip and substrate and to electrically connect quality and be subject to the line length influence of bonding wire and cause electrically not good, simultaneously because those chips must be offset a segment distance when piling up, and add that bonding wire is provided with the influence in space, still may cause chip-stacked area excessive and can't hold more multicore sheet.
In view of foregoing problems, see also Figure 1A to Fig. 1 G, U.S. Pat 5,270,261 and 5,202,754 disclose and a kind ofly utilize the silicon passage (Through Silicon Via, TSV) technology is for a plurality of semiconductor chip vertical stackings and the structure and the method for making that mutually electrically connect.
Its method for making mainly provides the first wafer 11a of relative first surface 111 of tool and second surface 112, this first wafer 11a includes a plurality of first chips 11, wherein this first surface 111 is formed with a plurality of holes 110, and in this hole 110, form metal column 13, to constitute silicon passage (TSV) structure, and in this metal column 13 exposed junctions formation weld pad 131, so that this first wafer 11a first surface 111 is sticked on the support plate 151 that places just like glass by gluing layer 141, thereby provide the required support strength of processing procedure (shown in Figure 1A) by this support plate 151; Utilize grinding operation, the second surface 112 of this first wafer 11a is carried out thinning, to expose outside this metal column 13 (shown in Figure 1B); On the metal column 13 that exposes outside this second surface 112, form weld pad 132, put and be electrically connected at by metal column 16 vertical junction of its silicon passage for another second wafer 12a that is formed with a plurality of second chips 12 of tool of silicon passage on the second surface 112 of this first wafer 11a (shown in Fig. 1 C); Then repeat aforementioned processing procedure, grind the second wafer 12a of a plurality of second chips 12 of this tool of thinning, with the metal column 16 that exposes outside this silicon passage, and in this metal column 16 exposed junctions formation weld pad 136 (shown in Fig. 1 D); Follow-up for electrically connecting for first and second chip 11,12 and external device (ED), need to plant a plurality of soldered balls in the first surface of this first wafer, promptly need utilize again this moment another as the support plate 152 of glass putting on it this first and second wafer 11a, 12a are glutinous by gluing layer 142, and expose outside the first surface 111 (shown in Fig. 1 E) of this first wafer 11a; Thereby on the weld pad 131 of this first wafer first surface 111, plant soldered ball 17 (shown in Fig. 1 F); Then cut first and second wafer that this piles up, to form first and second chip 11,12 of a plurality of mutual vertical stackings, again through picking up and being electrically connected to substrate 18, to form the semiconductor package part (shown in Fig. 1 G) of multi-chip moduleization by soldered ball 17.
Yet in aforesaid processing procedure, must additionally use a plurality of support plates 151,152, and with many glutinous repeatedly placing on the support plate 151,152 of first and second wafer 11a, 12a, but this not only increases the processing procedure cost, also cause the raising of process complexity, moreover, when if employed gluing layer 141,142 is the macromolecular material of for example epoxy resin (epoxy), in forming sputter (sputtering) that this weld pad 131,136 carried out and follow-up Wet-type etching (strip) operation, very easily cause the pollution on the processing procedure and cause to produce and be difficult for.
Be with, how to solve the problem that the piece installing of above-mentioned existing multi-chip module semiconductor device is produced in processing procedure, and develop a kind of multi-chip stacking structure and the method for making thereof that must not use support plate and gluing layer, to simplify processing procedure and to reduce cost, and avoid because of using macromolecule gluing layer that pollution problem takes place, real in desiring most ardently the problem of solution at present.
Summary of the invention
The shortcoming of background technology in view of the above, a purpose of the present invention is to provide a kind of multi-chip stacking structure and the method for making thereof that must not use the tool silicon passage of support plate and gluing layer in processing procedure.
Another object of the present invention is to provide a kind of processing procedure simply and have the multi-chip stacking structure and the method for making thereof of silicon passage cheaply.
A further object of the present invention is to provide a kind of multi-chip stacking structure and method for making thereof of tool silicon passage, avoids because of using macromolecule gluing layer that pollution problem takes place.
For reaching above-mentioned and other purpose, the invention provides a kind of method for making of multi-chip stacking structure of tool silicon passage, comprise: a wafer that includes a plurality of first chips is provided, this wafer and first chip have first and second relative surface, wherein the first surface of this first chip is formed with a plurality of holes, and this hole is formed with metal column and weld pad, to constitute silicon passage (TSV) structure; Form at least one groove in the second surface of this first chip respectively, and make the metal column of this silicon passage be revealed in this bottom portion of groove; And it is chip-stacked on this first chip and be electrically connected to the metal column of this silicon passage that exposes outside this groove with at least one second.
This method for making comprises again: fill the insulating material that coats second chip in the groove of this first chip; This insulating material of leveling flushes with the second surface of this first chip to make this insulating material; On the weld pad of this first chip first surface, plant conducting element; This wafer is cut, to separate respectively this first chip; And will pile up first chip that second chip is arranged and connect by this conducting element and put and be electrically connected on the chip bearing member.
In addition, be formed with silicon passage (TSV) in this second chip again, on this second chip, pile up and electrically connect the 3rd chip for follow-up, moreover, also can on the weld pad of the first surface of this first chip, pile up the four-core sheet, by the increase of core number, to strengthen integrally-built electrical functionality.
By aforementioned method for making, the present invention provides a kind of multi-chip stacking structure of tool silicon passage again, comprise: first chip, it has first and second relative surface, this first surface is formed with a plurality of holes, and be formed with metal column and weld pad in this hole, to constitute silicon passage (TSV) structure, this second surface is formed with at least one groove to expose outside the metal column of this silicon passage; And at least one second chip, be stacked on this first chip and be electrically connected to the metal column of the silicon passage that exposes outside this groove.
The multi-chip stacking structure of this tool silicon passage comprises again: insulating material is filled in the groove of this first chip and coats second chip; Conducting element plants in the weld pad of this first chip first surface; And chip bearing member, second chip that confession is piled up and first chip connect to put on it and form by this conducting element and electrically connect.
Moreover in another embodiment, the multi-chip stacking structure of this tool silicon passage includes the 3rd chip again, is stacked on this second chip, and is formed with silicon passage (TSV) in this second chip, for electrically connecting with the 3rd chip.In another embodiment, this multi-chip stacking structure includes the four-core sheet again, connects the weld pad of putting and be electrically connected to this first chip first surface.
Therefore, the multi-chip stacking structure and the method for making thereof of tool silicon passage of the present invention, mainly be that wafer first surface at a plurality of first chips of tool is formed with a plurality of holes, and form metal column and weld pad in this hole, to constitute the silicon channel design, second surface in this first chip is formed with at least one groove that exposes outside this silicon passage metal column again, with chip-stacked on this first chip and be placed in this groove with at least one second, and be electrically connected to the metal column of the silicon passage that exposes outside this groove, to form the vertical stacking of first and second chip, then can in this groove, fill the insulating material that coats second chip, and this insulating material of leveling, to make its second surface flush with this first chip, on the weld pad of this first chip first surface, plant conducting element again and carry out the wafer cutting, use and to pile up first chip that second chip is arranged and connect by this conducting element and put and be electrically connected on the chip bearing member, thereby the wafer by utilizing a plurality of first chips of this tool without whole thinning is as the ongoing carrying framework of processing procedure, avoid existing utilize a plurality of chips of silicon channel design vertical stacking and those chips connect must repeatedly use support plate and gluing layer when placing on the chip bearing member, the processing procedure that is produced is numerous and diverse, problems such as cost is high and may be polluted.
Description of drawings
Figure 1A to Fig. 1 G is existing U.S. Pat 5,270,261 and 5,202,754 disclosed schematic diagrames by a plurality of semiconductor chips of silicon passage (TSV) technology vertical stacking;
Fig. 2 A to Fig. 2 F is the schematic diagram of multi-chip stacking structure of the present invention and method for making first embodiment thereof;
Fig. 2 D ' and Fig. 2 E ' are the schematic diagram of the second chip differing heights among corresponding diagram 2D and Fig. 2 E;
Fig. 3 A to Fig. 3 D is the schematic diagram of multi-chip stacking structure of the present invention and method for making second embodiment thereof; And
Fig. 4 is the schematic diagram of multi-chip stacking structure of the present invention and method for making the 3rd embodiment thereof.
The component symbol explanation
11 first chips, 111 first surfaces
112 second surfaces, 110 holes
12 second chips, 13,16 metal columns
131,132,136 weld pads, 141,142 gluing layers
151,152 support plates, 17 soldered balls
18 substrates, 21 first chips
210 holes, 211 first surfaces
212 second surfaces, 23 metal columns
231 weld pads 23 " insulating barrier
23 ' barrier layer, 2120 grooves
22 second chips, 223 metal columns
2231 weld pads, 2232 circuit rearrangement layers
24 four-core sheets, 25 insulating material
26 the 3rd chips, 27 conducting elements
28 chip bearing members
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, the technical staff in the technical field can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
First embodiment
See also Fig. 2 A to Fig. 2 F, be the multi-chip stacking structure of tool silicon passage of the present invention and the schematic diagram of method for making first embodiment thereof.
Shown in Fig. 2 A, the one wafer 21a that includes a plurality of first chips 21 is provided, this wafer 21a reaches respectively, and this first chip 21 has opposite first 211 and second surface 212, wherein these first chip, 21 first surfaces 212 are formed with a plurality of holes 210, with to should hole 210 places forming metal column 23 and weld pad 231, and constitute silicon passage (TSV) structure.
23 of the hole 210 of this silicon passage and metal columns are provided with the insulating barrier 23 as silicon dioxide or silicon nitride ", and this insulating barrier 23 " and 23 barrier layers 23 ' that are provided with as nickel of metal column, and the material of this metal column 23 for example is copper, gold, aluminium etc.
Shown in Fig. 2 B, second surface 212 to this first chip 21 utilizes as deep layer etching (Deep Reactive Ion Etching, DRIE) mode etching forms at least one groove 2120, and the metal column 23 that makes this silicon passage is revealed in this groove 2120 bottoms, and wherein this metal column 23 can protrude from this groove 2120 bottoms.
Shown in Fig. 2 C, be stacked at least one second chip 22 on this first chip 21 and be placed in this groove 2120, and be electrically connected to the metal column 23 of the silicon passage that exposes outside this groove 2120.
Shown in Fig. 2 D and Fig. 2 E, in this groove 2120, fill the insulating material 25 (for example being packing colloid) that coats second chip 22, then, utilize grinding operation, flush with the second surface 212 of this first chip 21 to make these insulating material 25 outer surfaces with this insulating material 25 of leveling.
Second surface 212 height that highly can select less than this first chip 21 are put in connecing of this second chip 22, and still make this second chip 22 be coated on (shown in Fig. 2 E) in this insulating material 25 behind this insulating material 25 of leveling; Also or connecing of this second chip 22 put second surface 212 height that this first chip 21 can be selected to equal or be slightly larger than to height, and behind this insulating material 25 of leveling, make this second chip 22 expose outside this insulating material (shown in Fig. 2 D ' and Fig. 2 E ').
Shown in Fig. 2 F, on the weld pad 231 of the first surface 211 of this first chip 21, plant conducting element 27, and this wafer 21a carried out cutting operation to separate respectively this first chip 21, and pick up operation, connect by this conducting element 27 with second chip 22 that will pile up and first chip 21 and put and be electrically connected on the chip bearing member 28.
By aforementioned method for making, the present invention also provides a kind of multi-chip stacking structure of tool silicon passage, comprise: first chip 21, this first chip, 21 tool opposite first 211 and second surface 212, this first surface 211 is formed with hole 210, and form metal column 23 and weld pad 231 in this hole 210, to constitute the silicon channel design, this second surface 212 is formed with the metal column 23 of at least one groove 2120 to expose outside this silicon passage; And at least one second chip 22, be stacked on this first chip 21 and be electrically connected to the metal column 23 of the silicon passage that exposes outside this groove 2120.
The multi-chip stacking structure of this tool silicon passage includes again: insulating material 25 is filled in the groove 2120 of this first chip 21 and coats second chip 22; Conducting element 27 plants in the weld pad 231 of these first chip, 21 first surfaces 211; And chip bearing member 28, second chip 22 that confession is piled up and first chip 21 connect to put on it and form by this conducting element 27 and electrically connect.
Therefore, the multi-chip stacking structure and the method for making thereof of tool silicon passage of the present invention, mainly the wafer first surface at a plurality of first chips of tool is formed with a plurality of holes, and form metal column and weld pad in this hole, to constitute the silicon channel design, second surface in this first chip is formed with at least one groove that exposes outside this silicon passage metal column again, with chip-stacked on this first chip and be placed in this groove with at least one second, and be electrically connected to the metal column of the silicon passage that exposes outside this groove, to form the vertical stacking of first and second chip, then can in this groove, fill the insulating material that coats second chip, and this insulating material of leveling, to make its second surface flush with this first chip, on the weld pad of this first chip first surface, plant conducting element again and carry out the wafer cutting, use and to pile up first chip that second chip is arranged and connect by this conducting element and put and be electrically connected on the chip bearing member, thereby the wafer by utilizing a plurality of first chips of this tool without whole thinning is as the ongoing carrying framework of processing procedure, avoid existing utilize a plurality of chips of silicon channel design vertical stacking and those chips connect must repeatedly use support plate and gluing layer when placing on the chip bearing member, the processing procedure that is produced is numerous and diverse, problems such as cost is high and may be polluted.
Second embodiment
See also Fig. 3 A to Fig. 3 D, be the multi-chip stacking structure of tool silicon passage of the present invention and the schematic diagram of method for making second embodiment thereof.For simplifying accompanying drawing, corresponding aforementioned same or analogous element adopts same numeral to represent in the present embodiment simultaneously.
The multi-chip stacking structure of the tool silicon passage of present embodiment and method for making thereof and previous embodiment are roughly the same, main difference is to be formed with in second chip silicon passage (TSV), use on this second chip vertical stacking and electrically connect the 3rd chip, thereby the increase by chip-stacked number is to strengthen integrally-built electrical functionality.
As shown in Figure 3A, on the wafer 21a of a plurality of first chips 21 of tool, at least one second chip 22 is stacked in the groove 2120 of these first chip, 21 second surfaces 212, and be electrically connected to the metal column 23 of first chip, the 21 silicon passages that expose outside this groove 2120, wherein be formed with metal column 223 in this second chip 22 to constitute the silicon passage, and in this groove 2120 fill insulant 25, and through as the leveling operation of grinding and make the metal column 223 of these second chip, 22 silicon passages expose outside this insulating material 25.
Shown in Fig. 3 B, for example utilizing, the mode of sputter (sputtering) forms weld pad 2231 in metal column 223 tops of second chip, the 22 silicon passages that expose.
Shown in Fig. 3 C, the 3rd chip 26 connect place on this second chip 22, and be electrically connected to the weld pad 2231 of this second chip 22.
In addition, see also Fig. 3 D again, also can utilize sputtering way in the circuit rearrangement layer 2232 (RDL) that forms the metal column 223 that is electrically connected to these second chip, 22 silicon passages on this second chip 22 and even on this insulating material 25 and first chip, 21 second surfaces 212, and be formed with weld pad 2231 in the terminal of this circuit rearrangement layer 2232, be electrically connected to this weld pad 2231 for the 3rd chip 26.
Follow-uply can on the first surface of this first chip, plant conducting element, and this wafer is cut to separate respectively this first chip, connect by this conducting element for first, second and third chip that piles up and put and be electrically connected on the chip bearing member.
The 3rd embodiment
See also Fig. 4, be the multi-chip stacking structure of tool silicon passage of the present invention and the schematic diagram of method for making the 3rd embodiment thereof.For simplifying accompanying drawing, corresponding aforementioned same or analogous element adopts same numeral to represent in the present embodiment simultaneously.
The multi-chip stacking structure of present embodiment and method for making thereof and previous embodiment are roughly the same, main difference is can connect again on the first surface 211 of first chip 21 puts at least one four-core sheet 24, and make this four-core sheet 24 be electrically connected to the weld pad 231 of first chip, 12 first surfaces 211, thereby the increase by chip-stacked number is to strengthen integrally-built electrical functionality.
Above-described specific embodiment, only release characteristics of the present invention and effect in order to example, but not in order to limit the category of implementing of the present invention, do not breaking away under above-mentioned spirit of the present invention and the technology category, the disclosed content of any utilization and the equivalence finished changes and modify, the scope that all still should be claims of the present invention contains.

Claims (34)

1. the method for making of the multi-chip stacking structure of a tool silicon passage comprises:
The wafer of a plurality of first chips of tool is provided, this wafer and first and second relative surface of the first chip tool, the first surface of this first chip is formed with a plurality of holes, and this hole place forms metal column and weld pad to constitute silicon passage (TSV) structure;
Second surface in this first chip forms at least one groove, and makes the metal column of this silicon passage be revealed in this bottom portion of groove; And
Chip-stacked on this first chip and be electrically connected to the metal column of the first chip silicon passage that exposes outside this groove with at least one second.
2. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 1 wherein, is provided with insulating barrier again between this hole and metal column, be provided with barrier layer between this insulating barrier and metal column again.
3. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 2, wherein, this insulating barrier is wherein one of silicon dioxide and a silicon nitride, and this barrier layer is a nickel, and the material of this metal column is one of copper, gold, aluminium institute cohort group person.
4. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 1 comprises again:
In the groove of this first chip, fill the insulating material that coats second chip; And
This insulating material of leveling flushes with the second surface of this first chip to make this insulating material.
5. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 4 comprises again:
On the weld pad of this first chip first surface, plant conducting element; And
This wafer is cut to separate respectively this first chip.
6. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 5 comprises again that second chip that will pile up and first chip connect by this conducting element to put and be electrically connected on the chip bearing member.
7. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 4, wherein, the second surface height of height less than this first chip put in connecing of this second chip, and behind this insulating material of leveling, this second chip is coated in this insulating material.
8. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 4, wherein, the second surface height that highly equals or be slightly larger than this first chip is put in connecing of this second chip, and behind this insulating material of leveling, makes one of this second chip surface exposedly go out this insulating material.
9. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 1 wherein, connects on the first surface of this first chip and is equipped with the four-core sheet, and makes this four-core sheet be electrically connected to the weld pad of the first chip first surface.
10. the method for making of the multi-chip stacking structure of a tool silicon passage comprises:
The wafer of a plurality of first chips of tool is provided, this wafer and first and second relative surface of the first chip tool, the first surface of this first chip is formed with a plurality of holes, and this hole place forms metal column and weld pad to constitute silicon passage (TSV) structure;
Second surface in this first chip forms at least one groove, and makes the metal column of this silicon passage be revealed in this bottom portion of groove;
Be formed with the second chip-stacked on this first chip and be electrically connected to the metal column of the first chip silicon passage that exposes outside this groove of silicon passage (TSV) with at least one;
Fill insulant in this groove, and this insulating material of leveling, and make the metal column of this second chip silicon passage expose outside this insulating material;
On this second chip, form the weld pad of the metal column that is electrically connected to the second chip silicon passage that exposes outside this insulating material; And
On this second chip, connect and put the 3rd chip, and make the 3rd chip be electrically connected to weld pad on this second chip.
11. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 10 wherein, is provided with insulating barrier again between this hole and metal column, be provided with barrier layer between this insulating barrier and metal column again.
12. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 11, wherein, this insulating barrier is wherein one of silicon dioxide and a silicon nitride, and this barrier layer is a nickel, and the material of this metal column is one of copper, gold, aluminium institute cohort group person.
13. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 10 comprises again:
On the first surface weld pad of this first chip, plant conducting element; And
This wafer is cut to separate respectively this first chip.
14. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 13 comprises again that first chip, second chip and the 3rd chip that will pile up connect by this conducting element to put and be electrically connected on the chip bearing member.
15. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 10, wherein, the weld pad on this second chip directly is formed at the metal column top of this second chip silicon passage.
16. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 10, wherein, the weld pad on this second chip is connected to the metal column of this second chip silicon passage by circuit rearrangement layer (RDL).
17. the method for making of the multi-chip stacking structure of tool silicon passage according to claim 10, wherein, the weld pad on this second chip forms by sputtering way.
18. the multi-chip stacking structure of a tool silicon passage comprises:
First chip, first and second surface that this first chip tool is relative, this first surface is formed with a plurality of holes, and this hole place is formed with metal column and weld pad to constitute silicon passage (TSV) structure, and this second surface is formed with at least one groove to expose outside the metal column of this silicon passage; And
At least one second chip is stacked on this first chip and is electrically connected to the metal column of the silicon passage that exposes outside this groove.
19. the multi-chip stacking structure of tool silicon passage according to claim 18 includes insulating material again, is filled in the groove of this first chip.
20. the multi-chip stacking structure of tool silicon passage according to claim 19, wherein, this insulating material flushes with the second surface of this first chip to make this insulating material through leveling.
21. the multi-chip stacking structure of tool silicon passage according to claim 20, wherein, the height of this second chip is less than the second surface height of this first chip, and this second chip is coated in this insulating material.
22. the multi-chip stacking structure of tool silicon passage according to claim 20, wherein, the height of this second chip equals or is slightly larger than the second surface height of this first chip, and behind this insulating material of leveling, makes one of this second chip surface exposedly go out this insulating material.
23. the multi-chip stacking structure of tool silicon passage according to claim 18 includes conducting element again, plants in the weld pad of this first chip first surface.
24. the multi-chip stacking structure of tool silicon passage according to claim 23 includes chip bearing member again, second chip that confession is piled up and first chip connect by this conducting element puts and is electrically connected to this chip bearing member.
25. the multi-chip stacking structure of tool silicon passage according to claim 18 wherein, is provided with insulating barrier again between this hole and metal column, be provided with barrier layer between this insulating barrier and metal column again.
26. the multi-chip stacking structure of tool silicon passage according to claim 25, wherein, this insulating barrier is wherein one of silicon dioxide and a silicon nitride, and this barrier layer is a nickel, and the material of this metal column is one of copper, gold, aluminium institute cohort group person.
27. the multi-chip stacking structure of tool silicon passage according to claim 18 wherein, connects on this first chip first surface and is equipped with the four-core sheet, and make this four-core sheet be electrically connected to the weld pad of this first chip first surface.
28. the multi-chip stacking structure of a tool silicon passage comprises:
First chip, first and second surface that this first chip tool is relative, this first surface is formed with a plurality of holes, and this hole place is formed with metal column and weld pad to constitute silicon passage (TSV) structure, and this second surface is formed with at least one groove to expose outside the metal column of this silicon passage;
At least one second chip that is formed with silicon passage (TSV) is stacked on this first chip and is electrically connected to the metal column of the first chip silicon passage that exposes outside this groove;
Insulating material in this groove, and makes the metal column of this second chip silicon passage expose outside this insulating material;
Weld pad is formed on this second chip and is electrically connected to the metal column of the second chip silicon passage that exposes outside this insulating material; And
The 3rd chip connects and places on this second chip, and is electrically connected to the weld pad on this second chip.
29. the multi-chip stacking structure of tool silicon passage according to claim 28 wherein, is provided with insulating barrier again between this hole and metal column, be provided with barrier layer between this insulating barrier and metal column again.
30. the multi-chip stacking structure of tool silicon passage according to claim 29, wherein, this insulating barrier is wherein one of silicon dioxide and a silicon nitride, and this barrier layer is a nickel, and the material of this metal column is one of copper, gold, aluminium institute cohort group person.
31. the multi-chip stacking structure of tool silicon passage according to claim 28 includes conducting element again, plants on the first surface weld pad of this first chip.
32. the multi-chip stacking structure of tool silicon passage according to claim 31 includes chip bearing member again, connects by this conducting element for first, second and third chip that piles up and puts and be electrically connected on this chip bearing member.
33. the multi-chip stacking structure of tool silicon passage according to claim 28, wherein, the weld pad on this second chip directly is formed at the metal column top of the silicon passage of this second chip.
34. the multi-chip stacking structure of tool silicon passage according to claim 28, wherein, the weld pad on this second chip is connected to the metal column of the silicon passage of this second chip by circuit rearrangement layer (RDL).
CNA2007101402914A 2007-08-08 2007-08-08 Multi-chip stacking structure having silicon channel and preparation thereof Pending CN101364550A (en)

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