CN103098204B - There is the semiconductor chip of redundancy silicon through hole - Google Patents

Abstract

Disclose a kind of semiconductor chip with conductive through hole and manufacture method thereof.Described method is included in one layer (80) of the first semiconductor chip (15) and forms more than first conductive through hole (115,120,125).Described more than first conductive through hole includes the first end (127) and the second end (129).First conductive pad (65) is formed as described first end (127) Ohmic contact with described more than first conductive through hole.

Description

There is the semiconductor chip of redundancy silicon through hole

Technical field

The present invention is broadly directed to semiconductor processes, and relates more specifically to be incorporated to the semiconductor core of silicon through hole Sheet and preparation method thereof.

Background of invention

Before a period of time, semiconductor chip design person starts by multiple semiconductor grains (dice) (i.e. " crystal grain (dies) ") vertical stacking is more multi-functional to obtain, and without required base plate for packaging or circuit board The corresponding increase in region.Multiple technologies have been used for electrically connecting as adjacent grain this stack arrangement.One The engagement pad that the technology of kind is directed to use with from a crystal grain guides the line of the corresponding contact pad to adjacent grain Engage.The another kind of technology introduced closer to the phase is directed to use with so-called silicon through hole (TSV).Typically TSV is depending on the presence or absence of any conductors pad on of chip or another first type surface And extend the conductive through hole that the most maybe may pass completely through semiconductor chip.

Typical tradition TSV provides the electrical wiring between the corresponding main surfaces of semiconductor chip.In side On, tradition TSV is connected to certain form of input/output structure (I/O), and it is typically to be designed to The welding block with base plate for packaging solder joints is formed during flip chip re-flow welds.TSV is not directly connected to Welding block and be coupled to some intermediary agent structures, such as such as the outermost metallization structure of block pad.Another of TSV End or dorsal part end are generally connected to some form of dorsal part I/O structure through some middle conductor structures.Pass The TSV configuration of system includes the single TSV of metallurgical, bond extremely single piece of pad.

Tradition TSV suffers Joule heating and problems of electromigration, and its intensity depends on power level, heat pipe Reason, grain size and other factors and change.Man-to-man TSV examines to the configuration of block pad according to this environment Consider.

The present invention relates to the overcoming or reduce of effect of one or more disadvantages mentioned above.

Brief summary of the invention

According to an aspect of the present invention, it is provided that be included in one layer of the first semiconductor chip formation first The manufacture method of multiple conductive through holes.More than first conductive through hole includes the first end and the second end.The One conductive pad is formed as the first end Ohmic contact with more than first conductive through hole.

According to another aspect of the present invention, it is provided that be included in one layer of the first semiconductor chip formation the The manufacture method of more than one conductive through hole.More than first conductive through hole includes the first end and the second end. First semiconductor chip has the first side and second and opposite side.First conductive pad is formed as neighbouring first side And with the first end Ohmic contact of more than first conductive through hole.Second conductor be formed as neighbouring second side and The second end Ohmic contact with more than first conductive through hole.

According to another aspect of the present invention, it is provided that a kind of equipment, it includes the first semiconductor chip, institute State the first semiconductor chip there is one layer and coupled to the first conductive pad of described first semiconductor chip.The More than one conductive through hole through described layer and has the first end and the second end.First end and first is led Body pad Ohmic contact.

Accompanying drawing is sketched

Reading be described in detail below and with reference to accompanying drawing time can be appreciated that above and other advantages of the present invention, its In:

Fig. 1 is the exemplary reality of the semiconductor chiop including installing semiconductor chip on circuit boards Execute the decomposition diagram of scheme；

Fig. 2 is the sectional view of the Fig. 1 obtained on the 2-2 of cross section；

Fig. 3 is the sectional view of the Fig. 2 obtained on the 3-3 of cross section；

Fig. 4 is such as Fig. 3 but is connected to the Alternative exemplary embodiment of multiple TSV of underlying conductors pad Sectional view；

Fig. 5 is that such as Fig. 3 but plurality of TSV are connected to the Alternative exemplary embodiment of underlying conductors pad Sectional view；

Fig. 6 is that the Alternative exemplary if Fig. 2 but plurality of TSV are the semiconductor chips of multicompartment is implemented The sectional view of scheme；

Fig. 7 is the sectional view of the semiconductor chip experiencing exemplary photoetching treatment；

Fig. 8 is such as 7 but to describe the sectional view of the exemplary formation of TSV trench；

Fig. 9 illustrates the sectional view of the part of depiction 8 under bigger amplification；

Figure 10 is the sectional view formed such as Fig. 8 but depicted example TSV；

Figure 11 is the sectional view of the exemplary thinning describing semiconductor chip such as Figure 10；

Figure 12 is that Figure 11 such as describes the sectional view of the semiconductor chip after thinning；With

Figure 13 is such as Fig. 2 but to describe to be incorporated to have the alternative exemplary of multiple TSV of conductive pole input/output The sectional view of property semiconductor chip.

Detailed description of the invention

The different embodiment party of the semiconductor chiop including two or more stacking substrates described herein Case.One example includes at least one semiconductor chip with multiple TSV.But, multiple TSV Be formed as and give conductor structure (such as block or post pad) Ohmic contact.There is redundancy TSV to the company of pad In the case of connecing, the fault of given TSV will not make pad open circuit.Additional details is now described.

In following accompanying drawing, reference number generally weight in the case of similar elements occurs in multiple accompanying drawing Multiple.Description and with particular reference to Fig. 1, there is shown the quasiconductor including being arranged on circuit board 20 The decomposition diagram of the exemplary of the semiconductor chiop 10 of chip 15.Semiconductor chip 15 Being adapted to have other semiconductor chip one or more, one illustrates and is labeled as 25, pacifying thereon Dress is stack arrangement.Semiconductor chip 15 can via multiple interconnection structures (its can be conductive pole, solder joint or Other type of interconnection) and interface with circuit board 20 electricity.In this illustrative embodiment, quasiconductor Chip 15 can be via including the metallurgical, bond semiconductor chip to the corresponding solder structure 30 of circuit board 20 Multiple solder joints of the corresponding solder structure (invisible) of 15 interface with circuit board 20.Circuit board 20 can connect Via multiple input/output structures and another electronic installation (such as another circuit board or other dress Put) electricity interfaces with.In this illustrative embodiment, input/output structure includes soldered ball 35 array. But, skilled craftsman should be appreciated that and is used as other type of interconnection structure, such as pin grid array, Land grid array or other interconnection structure.

The example arrangement of semiconductor chip 15 disclosed herein does not relies on specific electronic function.Therefore, Semiconductor chip 15 and semiconductor chip 25 can be the countless different types of electricity used in electronic installation Any one of road device, such as, such as microprocessor, graphic process unit, combination microprocessor/figure Processor, special IC, storage arrangement, active optics device, such as laser or the like is also And can be monokaryon or multinuclear or even laterally stacked additional dies.Additionally, semiconductor chip 15 and 25 One or both of can be configured to the intermediary layer with or without some logic circuits.Therefore, term " core Sheet " include intermediary layer.Semiconductor chip 15 and 25 can be by bulk semiconductor (such as silicon or germanium) or exhausted Edge body semiconductor-on-insulator material (such as silicon-on-insulator material or other chip material) forms.

The example arrangement of semiconductor chip 15 disclosed herein does not relies on specific electronic circuitry plate function. Therefore, circuit board 20 can be semiconductor die package substrate, circuit card or other type actually any Printed circuit board (PCB).Although single chip architecture can be used as circuit board 20, but more typically configuration can use long-pending Layer design.In this regard, circuit board 20 can include being formed on it one or more laminations and thereunder shape Become the central core of additional one or more laminations.Central core itself can include the stacking of one layer or more.As Fruit is embodied as semiconductor die package substrate, then the number of plies in circuit board 20 can be changed to 16 from four layers Layer or more, but can use less than four layers.It is used as what is called " non-stop layer layer " design.Circuit board 20 layers of insulant that can include being scattered with metal interconnecting piece, the most various known epoxy resin.Can use Multi-layer configuration in addition to lamination.Optionally, circuit board 20 can be by known ceramics or be applicable to base plate for packaging Or other material composition of other printed circuit board (PCB).Circuit board 20 be provided with many conductive traces and through hole and its Its structure (invisible) to provide semiconductor chip 15 and 25 and another device, the most such as another Electric power, ground connection and signal transmission between individual circuit board.Circuit board 20 can be all via input/output array BGA is electrically connected to another device (not shown) as depicted.BGA includes that metallurgy connects It is bonded to above-mentioned multiple soldered balls 35 of corresponding ball pad (not shown).Ball pad (not shown) is via multiple interconnection The different conductor pad that trace and through hole and other structure unshowned are connected in circuit board 20 mutually.

The subsidiary details of semiconductor chip 15 will describe in conjunction with Fig. 2, and described Fig. 2 is to take along cross section 2-2 The sectional view of the Fig. 1 obtained.Before Fig. 2 is discussed, notice that the cross section 2-2 of Fig. 1 is through semiconductor chip The fraction of 15.Under described background, referring now to Fig. 2.As briefly mentioned above, semiconductor chip 15 can wrap Include the multiple input/input structures being designed to interconnection structure 30 metallurgical, bond with circuit board 20.A pair This exemplary interconnection structure can include corresponding welding block 40 and 45.Welding block 40 and 45 can be by different types of Solder, such as without lead-in wire or solder based on lead-in wire composition.The example of suitable lead-free solder include stannum- Silver (about 97.3%Sn2.7%Ag), stannum-copper (about 99%Sn1%Cu), tin-silver-copper are (greatly About 96.5%Sn3%Ag0.5%Cu) or the like.The example of solder based on lead-in wire includes eutectic Stannum lead-in wire solder of ratio or nearly eutectic ratio or the like.As it has been described above, soldered ball 40 and 45 can root Replace according to needs conductive pole or other type of interconnection structure.Herein, welding block 40 and 45 coupling respectively It is bonded under block (UBM) structure 50 and 55 that metallizes.UBM structure 50 and 55 is formed at passivating structure On 60 and in passivating structure 60, it can be monolithic or the stack membrane of insulant.UBM structure 50 He 55 are then connected to conductor structure or pad 65 and 70.Conductive pad 65 and 70 can include being actually formed conduct The conductive pad of part including the metal layer 75 of interlayer dielectric and metal level (not shown).Should be appreciated that figure 2 is the most schematic because conductive pad 65 and 70 and metal layer 75 show not in scale Go out.Under any circumstance, the interlayer dielectric layer (not shown) as metal interconnecting layer 75 can include known Silicon dioxide, other type of silicate glass, low-k dielectric film or the like.Layer 75 and metal Metallization structure in pad 65 and 70 and UBM structures 50 and 55 can be made up of different conductor, such as The alloy of copper, silver, nickel, platinum, gold, aluminum, palladium or these materials or lamination or the like.Conductive pad 65 Can be placed by known materials with 70 and patterning techniques is formed, such as plating, chemical gaseous phase deposition Or similar techniques and being lithographically formed by chemical etching laser ablation or similar techniques (CVD).

Semiconductor chip 15 is multiple structure, it is possible to there is bulk layers 80, wherein can form a large amount of crystalline substance The device layers 85 of body pipe, capacitor and other circuit arrangement and metal layer 75.Metal layer 75 can shape Become a series of metal layers being clipped between the interlayer dielectric layer being deposited in continuously in device layers 85.Because Semiconductor chip 15 is configured to have stacking another semiconductor chip thereon, such as semiconductor chip 25, so providing back-side metallization scheme.In this regard, redistributing layer (RDL) 90 may be formed at half On conductor layer 80.RDL90 can be and the one or more RDL metals that can be at identical or different level Change one or more layers accumulation of structure intertexture or the monolithic of the insulant of other deposition or laminated construction.? In this illustrative embodiment, RDL metallization structure 95 and 100 is visible.RDL90 top has Insulation or passivation layer 105 and multiple input/output structure 110.Passivation layer 105 can be monolithic or multiple The lamination of dielectric film and can be by the same type for passivating structure layer 60 described elsewhere herein Material forms.Input/output structure 110 is probably conductive pole, pad, solder joint or the like and for building The electricity founding the semiconductor chip 25 described with Fig. 2 interfaces with.Interconnection structure 110 can be by different conductor group Become, such as copper, silver, nickel, platinum, gold, aluminum, palladium, the alloy of these materials or lamination, solder or class Like thing.RDL structure 95 and 100 is connectable to the one or more of interconnection structure 110.

In order to set up between the opposite side 112 and 113 of semiconductor chip 15 and more specifically RDL structure Conductive path between 95 and 100 and conductive pad 65 and 70, seen from multiple TSV(its three and mark Note is 115,120 and 125) may be formed in semiconductor layer 80 to extend through device layers 85 and metal Change layer 75 and RDL structure 95 is bonded to conductive pad 65.In this way, the respective ends of TSV 127 contact conductive pads 65 and its opposing end portions 129 contact RDL structure 95.Similar multiple TSV 130,135 and 140 can be by RDL structure 100 electric interlock to conductive pad 70.Should be appreciated that term " TSV " and " quasiconductor " is used generally in this article, i.e. semiconductor layer 80 can be by the material beyond silicon Material and even insulant (such as silicon dioxide, tetraethyl ortho silicate or other material) composition.With Each weld pad uses the conventional semiconductor chip design difference of single TSV, embodiments disclosed herein Multiple TSV, such as TSV115,120 and 125 and conductive pad 65 are used for given conductive pad. For given conductive pad use multiple TSV provide improve thermal stress spread and reduce current concentrated and because of This Joule heating, it can strengthen electromigration and there is the time.It is connected to the multiple of given conductive pad using In the case of TSV, because the fault of one of the TSV of such as stress migration fracture can be remained TSV by other Compensate.TSV115,120,125,130,135 and 140 can be made of a variety of materials, such as copper, Tungsten, graphite, aluminum, gold, palladium, the alloy or the like of these materials.Imagination coat structure.

The subsidiary details of TSV115,120 and 125 now can be by understanding with reference to Fig. 3, and described Fig. 3 is edge The sectional view of Fig. 2 that cross section 3-3 obtains.Before conscientious reference cross section 3-3, it should be noted that the 3-3 of cross section Through the TSV115 near conductive pad 65,120 and 125.Referring now to Fig. 3.Note because of cross section 3-3's Position, TSV115,120 and 125 occur in cross section but underlying conductors pad 65 is metallized layer 75 and hides Keep off and be therefore shown as dotted line.Be connected to the TSV of conductive pad 65 than three TSV115,120 and 125 More and the most actually can include other six TSV being jointly labeled as 145.In this explanation In property embodiment, TSV115,120,125 and 145 can be configured to substantially follow the trail of underlying conductors pad 65 The array of trace.But, skilled craftsman should be appreciated that the real space of the TSV being connected to given conductive pad Configuration can present the multiple difformity that can present such as conductive pad 65.It is also noted that TSV115,120,125 With 145 structure may be about monolithic.But and such as combine the alternate embodiment that Fig. 4 is described Described, it be also possible to use other configuration.

Referring now to Fig. 4, it is such as Fig. 3 but is connected to the replacement of multiple TSV115' of underlying conductors pad 65 The sectional view of exemplary.Herein, conductive pad 65 is shown as dotted line again, because it is actual fixed Position is below metal layer 75.As just mentioned, the configuration in addition to monolithic configures can be used as giving TSV.Therefore, TSV115' can include sheath 150 and polymer core 155.Sheath 150 can by copper, Tungsten, graphite, aluminum, platinum, gold, palladium, alloy or the like the composition of these materials.Polymer core 155 Can be made up of conduction or nonconducting multiple polymers as required.Example includes Namics119, known Epoxy resin or the like.These so-called annular TSV can be by closely controlling via during electroplating process The carefully customization that electric field generates is electroplated and is formed.

As it has been described above, be that the configuration of the TSV to given conductive pad can be changed greatly.In this regard, existing With reference to Fig. 5, its be as Fig. 3 but plurality of TSV115'' be connected to underlying conductors pad 65(its again because of Its position below metal layer 75 and be shown as dotted line) the sectional view of Alternative exemplary embodiment. Herein, the cross that TSV115'' is configured to not necessarily mate with the somewhat rectangular foot print of conductive pad 65 is joined Put.Again, various configurations perhaps can be used and still realize being the technology of the multiple TSV to given conductive pad Benefit.

In illustrative above embodiment, different TSV are made as the continuous structure from top to bottom, I.e. through the semiconductor device layer 85 shown in Fig. 2 and metal layer 75.But, skilled craftsman should be appreciated that Multiple structure can be used as TSV.In this regard, referring now to Fig. 6, its be as Fig. 2 but can substantial configuration such as Semiconductor chip 15 described elsewhere herein but there are the semiconductor chip 15' of some obvious exceptions Alternative exemplary embodiment.Herein, multiple TSV160,162 and 164 are connectable to UBM knot Structure 50 and multiple TSV166,168 and 169 are connectable to UBM structure 55.But, TSV160 Connect via corresponding TSV extension 170 and 172 with 164 and TSV166 and 169 is via corresponding TSV Extension 174 and 176 connects.Herein, TSV extension 170,172,174 and 176 can pass through Passivating structure 60 is formed.

The example process forming multiple TSV now can be by with reference to Fig. 7, Fig. 8, Fig. 9, Figure 10, figure 11 and Figure 12 and initial reference Fig. 7 understand, described Fig. 7 is in the quasiconductor of starting stage processed The sectional view of chip 15.In this stage, device layers 85 has used many known treatment steps to make. Metal layer 75 also can completely or partially complete before TSV is formed or be not fully complete.Now, semiconductor core Sheet 15 has the thickness Z mainly occupied by semiconductor layer 80, its more than as shown in Figure 2 formed TSV and Final thickness after RDL90.Now, suitable mask 178 can apply to device layers 85 and light Carving and pattern to set up opening 180,184,188,192,196 and 198, it is corresponding to being subsequently formed The desired location of TSV115,120,125,130,135 and 140.Mask 178 can by just adjusting or The negative known photoresist composition adjusted.Optionally, noncontact or even hard mask can be used.

Referring now to Fig. 8, after mask 178 patterns, material removal processes can be used at semiconductor layer Deep trench 200,205,210,215,220 and 225 is formed in 80.Groove 200,205,210, 215,220 and 225 can be removed by the chemical etching strengthened with or without plasma or other material Technology is formed.Laser ablation can be used, it should be noted that avoid superheated.Certainly, in mask 178 Opening 180,184,188,192,196 and 198 be patterned as that there is the groove ultimately formed 200, the wanted trace of 205,210,215,220 and 225.Depend on the group of the TSV subsequently formed Become, it may be necessary in groove 200,205,210,215,220 and 225, form inner lining film to promote To the adhesion of semiconductor layer 80 and prevent the atom of TSV, molecule or major part from migrating to quasiconductor In layer 80 and device layers 85.Fig. 9 illustrates with the sectional view of the groove 200 shown in bigger amplification.In Lining 230 may be formed in groove 200 and the not only sidewall of coat trench 200 but also apparatus for coating layer The sidewall of 85.Inner liner 230 can be made of a variety of materials, such as silicon dioxide.With or without etc. The known CVD technology that ion strengthens can be used for depositing inner liner 230.Identical process can be for other groove 205,210,215,220 and 225 complete.Mask 178 shown in Fig. 8 can be formed at inner liner 230 Before or after by ashing, solvent back extraction or similar techniques removes or use noncontact mask feelings Peel off under condition.

After removing the etching mask 178 shown in Fig. 7 and Fig. 8, TSV115,120,125,130, 135 and 140 can be formed at respective grooves 200,205,210,215,220 and 225 as shown in Figure 10 In.As is described elsewhere herein, TSV115,120,125,130,135 and 140 can be according to need Respective grooves 200,205,210,215,220 and 225 to be formed as completeness in column or annular TSV.Electroplating process can be as required single stage skew electroplating process can be maybe not offset crystal seed layer Electroplating process, is skew electroplating process afterwards.

Follow-up in order to make TSV115,120,125,130,135 and 140 can set up with shown in Fig. 2 The Ohmic contact of the structure in formation RDL90, semiconductor layer 80 can thinning as shown in figure 11.Herein In, the part 227 of semiconductor layer 80 can remove advantageous by chemical-mechanical planarization (CMP), but It is to may replace or combine CMP to use other material removal technique.TSV115,120,125, 130,135 and 140 as shown in figure 12 expose in the case of, the RDL90 that Fig. 2 is described can use can Depend on RDL90 complexity and count the known insulative material deposition of multilamellar and conductor material deposition and Patterning techniques makes.Similarly, the making of passivating structure 95 and interconnection structure 110 can be at RDL90 After formation.

Referring again to Fig. 1, semiconductor chip 25 may be stacked on semiconductor chip 15 and depends on institute Use chip extremely chip interface type and be electrically connected to it by Reflow Soldering, compression engagement or other technology On.Skilled craftsman should be appreciated that semiconductor chip 25 can be stacked on by wafer scale or die level as required and partly leads On body chip 15.Semiconductor chip 15 and 25 can single or integral installation to circuit board 20.

Any exemplary disclosed herein can be embodied as being placed in computer-readable medium Instruction in (such as, such as quasiconductor, disk, CD or other storage medium) or computer data Signal.Instruction or software may can synthesize with or simulate circuit structure disclosed herein.Exemplary In embodiment, electric design automation program, such as Cadence APD, Cadence Spectra, Encore or similar program can be used for synthesizing disclosed circuit structure.It is public that gained code can be used for making institute The circuit structure opened.

Although the present invention is likely to be of different amendment and alternative form, but particular is at accompanying drawing In illustrate via citing and describe in detail the most wherein.However, it should be understood that the present invention is not intended to limited In particular forms disclosed.But, covering is belonged to as hereafter appended claims define by the present invention The spirit and scope of the present invention in all modifications example, equivalent and alternative.

Claims (21)

1. a semiconductor device manufacturing method, comprising:

More than first conductions are formed logical in one layer (80) of the first semiconductor chip (15) Hole (115,120,125), described more than first conductive through hole includes the first end (127) and the second end (129)；

Described first of outermost the first conductive through hole in described more than first conductive through hole The first conductive through hole extension is formed on end；With

Metallization (UBM) structure (50) under first piece is made to be formed as and described first conduction First of other the first conductive through holes in through hole extension and described more than first conductive through hole End Ohmic contact.

Method the most according to claim 1, it is included in described layer (80) and is formed More than second conductive through hole (130,135,140), described more than second conductive through hole includes Three-termination and the 4th end,

The described three-termination of the outermost conductive through hole in described more than second conductive through hole Upper formation the second conductive through hole extension；With

Metallization (UBM) structure (55) under second piece is made to be formed as and described second conduction The 3rd of other the second conductive through holes in through hole extension and described more than second conductive through hole End Ohmic contact.

Method the most according to claim 1, it includes making conductor structure (90) be formed For the described second end Ohmic contact with described more than first conductive through hole.

Method the most according to claim 3, wherein said conductor structure includes redistribution Rotating fields.

Method the most according to claim 1, it includes input/output structure (40) It coupled to described first piece of lower metallization structure.

Method the most according to claim 5, wherein said input/output structure includes weldering Block (40) or conductive pole (240).

Method the most according to claim 1, it includes the second semiconductor chip (25) it is stacked on described first semiconductor chip.

Method the most according to claim 1, it includes described first semiconductor chip It is arranged on circuit board (20).

Method the most according to claim 1, wherein said more than first conductive through hole leads to Cross and in described first semiconductor chip, form groove (200,205,210) and by conductor Material is placed and is formed in the trench.

10. a semiconductor device manufacturing method, comprising:

More than first conductions are formed logical in one layer (80) of the first semiconductor chip (15) Hole (115,120,125), described more than first conductive through hole includes the first end (127) and the second end (129), this first semiconductor chip has the first side (112) With relative the second side (113)；

Described first of outermost the first conductive through hole in described more than first conductive through hole Conductive through hole extension is formed on end；

Metallization (UBM) structure (50) under first piece is made to be formed as neighbouring described first side And with in described conductive through hole extension and described more than first conductive through hole other first First end Ohmic contact of conductive through hole；With

The second conductor structure (90) is made to be formed as neighbouring described second side and with described first The described second end Ohmic contact of multiple conductive through holes.

11. methods according to claim 10, wherein said second conductor structure includes Redistributing layer structure.

12. methods according to claim 10, it includes input/output structure (40) it coupled to described first piece of lower metallization structure.

13. methods according to claim 12, wherein said input/output structure includes Welding block (40) or conductive pole (240).

14. methods according to claim 10, it includes the second semiconductor chip (25) it is stacked on described first semiconductor chip.

15. 1 kinds of semiconductor equipments, comprising:

First semiconductor chip (15), it includes one layer (80)；

First piece of lower metallization structure (50), it coupled to described first semiconductor chip；

More than first conductive through hole (115,120,125), it is through described layer and has the One end (127) and the second end (129)；With

Conductive through hole extension, it is formed at the outermost in described more than first conductive through hole On described first end of the first conductive through hole, described conductive through hole extension and described first First end of other the first conductive through holes in multiple conductive through holes with described first piece under gold Genusization structure Ohmic contact.

16. semiconductor equipments according to claim 15, wherein said equipment includes coupling It is bonded to second piece of lower metallization structure (55) of described first semiconductor chip and through described Layer and have three-termination and the 4th end more than second conductive through hole (130,135, 140), the described three-termination of the outermost conductive through hole in described more than second conductive through hole On be formed with the second conductive through hole extension, described second conductive through hole extension and described The three-termination of other the second conductive through holes in more than two conductive through hole with described second piece under Metallization structure Ohmic contact.

17. semiconductor equipments according to claim 15, it includes and described more than first The conductor structure (90) of the described second end Ohmic contact of individual conductive through hole.

18. semiconductor equipments according to claim 17, wherein said conductor structure bag Include redistributing layer structure.

19. semiconductor equipments according to claim 15, it includes coupleding to described The welding block (40) of one piece of lower metallization structure or conductive pole (240).

20. semiconductor equipments according to claim 15, it includes being stacked on described The second semiconductor chip (25) on semiconductor chip.

21. semiconductor equipments according to claim 15, it includes coupleding to described The circuit board (20) of semiconductor chip.