CN103137613A - Active chip packaging substrate and method for preparing same - Google Patents
Active chip packaging substrate and method for preparing same Download PDFInfo
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- CN103137613A CN103137613A CN2011103867861A CN201110386786A CN103137613A CN 103137613 A CN103137613 A CN 103137613A CN 2011103867861 A CN2011103867861 A CN 2011103867861A CN 201110386786 A CN201110386786 A CN 201110386786A CN 103137613 A CN103137613 A CN 103137613A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 59
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- 238000002161 passivation Methods 0.000 claims description 57
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides an active chip packaging substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip embedded in the core board, wherein the active surface of the upper active chip faces the lower surface of the core board, and the upper active chip is an active bare chip; and at least one lower active chip embedded in the core board, wherein the active surface of the lower active chip faces the upper surface of the core board, and the lower active chip is an active bare chip. In the active chip packaging substrate and the method for preparing the substrate, the active chip is not packaged before being buried and is subjected to thinning treatment, so that the microminiaturization and the light weight of a packaging structure are realized, the substrate manufacturing process is simplified, and the production efficiency is improved; in addition, the invention realizes that a plurality of active bare chips are embedded on two sides of the substrate at the same time, thereby improving the integration level; meanwhile, the two surfaces of the substrate have great freedom and space, and multilayer wiring can be continuously carried out, so that the process quality and the reliability of electrical connection are improved.
Description
Technical field
The present invention relates to microelectronic industry system in package technical field, relate in particular to a kind of active chip base plate for packaging and prepare the method for this substrate.
Background technology
Modern portable type electronic product is had higher requirement to microelectronics Packaging, and along with it is lighter, thinner, less, the continuous pursuit of high reliability, low-power consumption, microelectronics Packaging is, packing forms development that size less higher towards density also.Microelectronics Packaging will encapsulate future development to nothing from encapsulation, few encapsulation are arranged, so direct chip bonding (Direct Chip Attach is called for short DCA) technology causes increasing attention.The direct chip adhesive technology is the highest encapsulation technology of a kind of packaging efficiency, it " do not have " encapsulation and directly with die bonding in printed circuit board (PCB) or substrate, its advantage is that it has better electrical property, more direct heat dissipation channel, lighter, less size and lower cost.
Usually, after these chip packages, then welded and installed is to substrate surface.Will directly be embedded into substrate inside to these naked active chips now, its complexity is apparent.Because the inside composition of chip is next more complex compared with passive component with structure, therefore embedding chip is much more difficult compared with embedding passive component, in embedding chip processes, because the Thickness Ratio thin film passive components of chip wants much thick, at first will be first with its complanation, slimming, and then carry out embedded process.In addition, chip is howed a lot at the interconnection node of substrate inside than passive component, and the wire fineness of these interconnection nodes requires also high a lot, and great majority are connections of " micron order " or even " nanoscale ", and this all gives chip has embeddingly brought a lot of difficulties.
Current chip is imbedded and is mainly contained dual mode, a kind of employing Losec nurse (Occam) technique, another kind of polymer embedded (the Chip in Polymer) technique that adopts, its thought all is based on first chip configuration on certain very thin core substrate, then go out a plank round these chips " length ", therefore chip buried have a following advantage: at first, no longer need scolder in assembling, also just no longer need to reflux, those have a large amount of defectives of direct or indirect relation to disappear with scolder and backflow; Secondly, because the shortening of interconnected distance can improve performance, in this technological design of majority, will can be not leaded, the substitute is device interconnected by little via hole and cabling, device can also be placed on another device here; At last, the substrate of completing with this kind technique has higher intensity in itself, can bear more impact and vibrations.And this plate also can be referred to as base plate for packaging, a kind of substrate with encapsulation function.
Chinese patent CN101192544A adopts and has realized two back-to-back imbedding at loading plate of chip with cuniculate loading plate.As shown in Figure 1A, at first in two loading plate 21a and 21b perforate in advance, chip 233a and 233b are placed in default hole, and adopt medium 221a and 221b to be embedded in respectively chip 233a and 233b in the hole, at last two loading plate 21a and 21b are coupled together face-to-face by dielectric layer 26, because loading plate needs perforate in advance, after chip is embedded in respectively default hole, carry out stacking pressing, technique is more complicated again.
United States Patent (USP) NO.7663249B2 has proposed a kind of chip-packaging structure and manufacture method, as shown in Figure 1B, this method is first to adopt face-down bonding technique that packaged chip 108 and 208 is connected respectively on two substrates, first with pressing one deck dielectric layer 120 on a substrate that has been connected with packaged chip 108, the real estate that again another piece upside-down mounting is connected with packaged chip 208 presses to dielectric layer 120 down, then remove the substrate on both sides, so just realized imbedding of a plurality of packaged chips, but above-mentioned patent chips adopts upside-down mounting to be connected on substrate then pressing dielectric layer, work as like this salient point many, gap ratio hour, salient point and the space between salient point (being the B in Figure 1B) that might dielectric layer can't fill chip fully, cause the existence of bubble, and chip is through encapsulation, the size of chip itself is just very large like this, encapsulating structure also will be larger so, be difficult to reduce the size of whole packaging body.
Summary of the invention
The technical problem that (one) will solve
For above-mentioned one or more problems, the invention provides a kind of active chip base plate for packaging and prepare the method for this substrate, imbed high-performance and miniaturization and with circuit when having realized a plurality of chip, also improved efficient and integrated level simultaneously.
(2) technical scheme
According to an aspect of the present invention, the invention discloses a kind of active chip base plate for packaging.This active chip base plate for packaging comprises: central layer; Active chip at least one embeds in central layer, and its active surface is towards the lower surface of central layer, and on this, active chip is active bare chip; And at least one lower active chip, embedding in central layer, its active surface is towards the upper surface of central layer, and this time active chip is active bare chip.
According to another aspect of the present invention, the invention also discloses a kind of method that is prepared with the source chip base plate for packaging.The method comprises: active surface one side of active chip at least one is fixed in upper loading plate by interim bonding film bonding; Active surface one side of at least one lower active chip is fixed in lower loading plate by interim bonding film bonding; Upper active chip and lower active chip are naked active chip; Active surface one side of upper active chip and lower active chip adds one deck sheet semi-solid preparation medium at least all toward the outer side in the middle of upper loading plate and lower loading plate, the gross thickness of sheet semi-solid preparation medium is greater than the thickness of upper active chip or lower active chip; Upper loading plate, at least one lamellar semi-solid preparation medium and lower loading plate are carried out thermocompression bonding, and at least one, active chip and at least one lower active chip embed in the semi-solid preparation medium, form central layer after at least one lamellar semi-solid preparation medium solidifies; Separate bonding and remove the interim bonding film of central layer both sides, upper loading plate and lower loading plate are removed thereupon, thereby at least one, active chip is encapsulated in central layer with at least one lower active chip, is formed with the source chip base plate for packaging.
(3) beneficial effect
From technique scheme as can be known, active chip base plate for packaging of the present invention and the method for preparing this substrate have following beneficial effect:
(1) to adopt active bare chip directly to carry out embedding in the present invention, avoided the generation of bubble between salient point and salient point when packaged chip is embedding;
(2) in the present invention, without encapsulation, and pass through the slimming processing due to active bare chip, thereby realized microminaturization and the lightweight of encapsulating structure, therefore simplified substrate manufacture technique, improved production efficiency;
(3) the present invention has realized that a plurality of active chips imbed in the substrate two sides, has improved integrated level; Simultaneously on the substrate two sides, the very large degree of freedom and space are arranged, sustainablely carry out multilayer wiring, thereby promoted process quality and be electrically connected reliability;
(4) method of the whole process using of the present invention can with the planar semiconductor process compatible, realized the integrated making of encapsulation and substrate.
Description of drawings
Figure 1A is the schematic diagram of prior art chip-packaging structure one of the present invention;
Figure 1B is the schematic diagram of prior art chip-packaging structure two of the present invention;
Fig. 2 is the flow chart of embodiment of the present invention chip packaging method;
Fig. 3 a-3e is the manufacturing process that active chip is made passivation layer and carried out slimming and cutting in embodiment of the present invention chip packaging method; Wherein:
Fig. 3 a is the whole wafer cutaway view with a plurality of active chips of metal electrode;
Fig. 3 b is the whole wafer cutaway view with a plurality of active chips of the first passivation layer;
Fig. 3 c is the whole wafer cutaway view with a plurality of active chips of the second passivation layer;
Fig. 3 d is thinning back side and polishes rear whole wafer cutaway view with a plurality of active chips;
Fig. 3 e is the single active chip cutaway view after cutting;
Fig. 4 a-4h is that in embodiment of the present invention chip packaging method, active chip is embedded into the medium central layer and prepares the manufacturing process of outer graphics; Wherein:
Fig. 4 a is that upper active chip is connected to the cutaway view on loading plate;
Fig. 4 b is that lower active chip is connected to the cutaway view on lower loading plate;
Fig. 4 c is the schematic diagram that upper loading plate, sheet semi-solid preparation dielectric layer and lower loading plate carry out thermocompression bonding;
Fig. 4 d is the embedding module cutaway view that upper active chip and lower active chip are arranged after thermocompression bonding;
Fig. 4 e removes the module cutaway view of upper loading plate and lower loading plate for separating bonding;
Fig. 4 f is the module cutaway view at medium central layer both sides making wired media layer and metal level;
Fig. 4 g is the module cutaway view in medium central layer both sides making the first outer-layer circuit;
Fig. 4 h is the module cutaway view in medium central layer both sides making the second outer-layer circuit;
Fig. 5 a-5h is the manufacturing process that in embodiment of the present invention chip packaging method, active chip and passive component is embedded into the medium central layer simultaneously and prepares outer graphics, wherein:
Fig. 5 a is that upper active chip is connected to the cutaway view on loading plate;
Fig. 5 b is that passive component is connected to the cutaway view on lower loading plate;
Fig. 5 c is the schematic diagram that upper loading plate, sheet semi-solid preparation dielectric layer and lower loading plate carry out thermocompression bonding;
Fig. 5 d is the embedding module cutaway view that active chip and passive component are arranged after thermocompression bonding;
Fig. 5 e removes the module cutaway view of upper loading plate and lower loading plate for separating bonding;
Fig. 5 f is the module cutaway view at medium central layer both sides making wired media layer and metal level;
Fig. 5 g is the module cutaway view in medium central layer both sides making the first outer-layer circuit;
Fig. 5 h is the module cutaway view in medium central layer both sides making the second outer-layer circuit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.Need to prove, although this paper can provide the demonstration of the parameter that comprises particular value, should be appreciated that, parameter need not definitely to equal corresponding value, but can be similar to described value in acceptable error margin or design constraint.For ease of explanation, at first each part involved in the present invention is numbered:
The upper active chip of 100-; The metal electrode of the upper active chip of 101-;
The first passivation layer on the upper active chip of 102-with windowing, exposes electrode;
The second passivation layer on the upper active chip of 103-;
The interim bonding film of 104-;
The upper loading plate of 105-;
The blind hole that the electrode of the upper active chip of 106-is drawn;
Active chip under 200-; Metal electrode under 201-on active chip;
The first passivation layer under 202-on active chip with windowing, exposes electrode;
The second passivation layer under 203-on active chip;
The interim bonding film of 204-
Loading plate under 205-;
The blind hole that under 206-, the electrode of active chip is drawn;
300-central layer/semi-solid preparation medium;
301,302,307,308-wired media layer;
303,304,309,310-metal level;
The 305-through hole;
The 400-passive component;
Metal electrode on the 401-passive component;
The blind hole that the electrode of 406-passive component is drawn.
In one exemplary embodiment of the present invention, provide a kind of active chip base plate for packaging.Fig. 4 e is the schematic diagram of embodiment of the present invention active chip base plate for packaging.As shown in Fig. 4 e, this active chip base plate for packaging comprises: central layer 300, the lower active chip 200 of active chip 100 and at least one at least one, and wherein, upper active chip 100 and lower active chip 200 are the active bare chip after attenuate; Upper active chip 100 embeds in central layer 300, and its active surface is towards the lower surface of central layer 300; Lower active chip 200 embeds in central layer 300, and its active surface is towards the upper surface of central layer 300.Certainly, can also comprise in this substrate: at least one passive component, this passive component embed in central layer 300 equally, and its active surface is towards upper surface or the lower surface of central layer 300.
In the present embodiment, central layer is one or more layers semi-solid preparation medium through hot-press solidifying, its material can be but be not limited to following material: epoxy resin, polyimides, span come vinegar imines-cyanate resin, liquid crystal polymer, ABF film (Ajinomoto Build-up Film), polyphenylene oxide, polytetrafluoroethylene, Parylene or stupid the third cyclobutane etc.In addition, need to prove, for the purpose of the statement smoothness, if no special instructions, " active chip " hereinafter all represents " active bare chip "; Passive component all represents " passive bare chip ".
In the present embodiment, upper active chip and lower active chip are all not pass through the bare chip of encapsulation, its active surface electrode is to draw by Microvia, therefore can avoid packaged chip when the substrate embedded set, the issuable bubble of filled media between chip bump and salient point.Simultaneously,, directly be embedded in substrate without encapsulation due to active bare chip, therefore simplified widely the preparation technology of base plate for packaging, improved production efficiency.
As a complete substrate, also should there be corresponding circuitous pattern and blind hole or through hole that circuitous pattern is connected with above-mentioned active bare chip in its both sides.Therefore, in a preferred embodiment of the invention, also provide a kind of active chip base plate for packaging.As shown in Fig. 4 g, in the present embodiment, upper active chip 100 and lower active chip 200 include: the first passivation layer and the second passivation layer.Upper surface and the lower surface of active chip base plate for packaging also all comprise: wired media layer and outer circuit figure.The first passivation layer is formed at the active surface of active bare chip, has window in the position of active bare chip active surface electrode; The second passivation layer is formed at the surface of the first passivation layer and the window's position of active bare chip active surface electrode, and its surface toward the outer side is the plane; The second passivation layer of upper active chip and the upper surface of central layer are coplanar; The second passivation layer of lower active chip and the lower surface of central layer are coplanar.The wired media layer is formed at upper surface and the lower surface of central layer; The outer circuit figure is formed on dielectric layer, and it is connected with the electrode of active chip active surface by the metalized blind vias of passing dielectric layer and the second passivation layer.And wired media layer and the outer circuit figure of central layer both sides can be multilayer.
In the present embodiment, the first passivation layer and the second passivation layer are all to adopt the lower material of surface activity, and the original idea of passivation reduces surface activity exactly, guarantees stability of characteristics.Semiconductor surface has a large amount of unsaturated linkages, and activity is very high, adds passivation layer can reduce the dangling bonds on surface, namely reduces surface density of states.The thermal oxidation commonly used of the first passivation layer, some stop mobile ion, steam, contamination etc. and prevent from scratching and radiation-resistant rete, comprise silicon dioxide, the materials such as silicon nitride or aluminium oxide.Here the second passivation layer is to the protection of the first passivation layer, adopts polymeric material, as polyimides more.The present embodiment has realized that a plurality of active chips imbed in the substrate two sides, improved greatly integrated level; The present invention has the very large degree of freedom and space on the substrate two sides, sustainablely carries out multilayer wiring, and promotes its process quality and be electrically connected reliability;
According to another aspect of the present invention, also provide a kind of active chip method for packing.Fig. 2 is the flow chart of embodiment of the present invention chip packaging method.As shown in Figure 2, the present embodiment comprises:
Step S202 is fixed in upper loading plate with active surface one side of upper active chip by interim bonding film bonding, and on this, active chip is active bare chip;
Step S204 is fixed in lower loading plate with active surface one side of lower active chip by interim bonding film bonding, and this time active chip is active bare chip;
Step S206, active surface one side of upper active chip and lower active chip adds one deck sheet semi-solid preparation medium at least all toward the outer side in the middle of upper loading plate and lower loading plate;
In this step, the gross thickness of sheet semi-solid preparation medium is greater than the thickness of upper active chip or lower active chip, and preferably, the gross thickness of sheet semi-solid preparation medium is greater than the gross thickness of upper active chip and lower active chip.Upper active chip and lower active chip can be oppositely arranged (as shown in Fig. 4 d), also can separate the predeterminable range setting.In the situation that upper active chip and lower active chip separate predeterminable range setting, the gross thickness of sheet semi-solid preparation medium can suitably reduce, thereby it is integrated more to be conducive to device.
Step S208 carries out thermocompression bonding with upper loading plate, sheet semi-solid preparation medium and lower loading plate, and upper active chip and lower active chip embed in the semi-solid preparation medium, forms central layer after sheet semi-solid preparation medium solidifies;
Step S210 separates the interim bonding film that bonding is removed the central layer both sides, and upper loading plate and lower loading plate are removed thereupon, thereby upper active chip and lower active chip all are encapsulated in central layer.
Below will on the basis of said method embodiment, provide another two embodiments of the method for the present invention.Need to illustrate, the feature in following two embodiment, in the situation that without indicating especially, all be applicable to simultaneously embodiment of the method and product embodiments, the technical characterictic that occurs in identical or different embodiment can be used in combination in not conflicting situation.
In another exemplary embodiment of the present invention, also provide a kind of active chip method for packing.This chip packaging method is divided into three phases: (1) makes the passivation layer stage to active chip; (2) the embedding stage of active chip; (3) the outer circuit patterning stage.Below this three phases is illustrated respectively.
Phase I: active chip is made the passivation layer stage.Fig. 3 a-3e be in embodiment of the present invention chip packaging method to active chip and the manufacturing process of carrying out slimming and cutting.
Step S302 consults Fig. 3 a, selects the wafer of 4 " or 8 ", has made circuitous pattern on wafer, with a plurality of active chips 100, has on each active chip 100 with a plurality of electrodes 101;
Step S304 consults Fig. 3 b, makes the first passivation layer 102 on the wafer of making circuitous pattern, and material selects Si
3N
4Or silicon dioxide, and window, expose the electrode 101 of active chip 100;
Step S306 consults Fig. 3 c, makes the second passivation layer 103 on the passivation layer 102 of windowing, and adopts the organic polymer materials such as polyimides, and this layer passivation layer 103 can cover the electrode 101 (namely filling windowing of the first passivation layer) of active chip 100; The upper surface of this passivation layer is the plane;
Step S308 consults Fig. 3 d, and to adopting chemical Mechanical Polishing Technique carry out attenuate and polish with the wafer rear of the first passivation layer 102 and the second passivation layer 103, wafer thickness is reduced to 200 μ m or following;
Step S310 consults Fig. 3 e, by mechanical means, wafer is cut into a plurality of active chips 100, and single active chip 100 is all with electrode 101, passivation layer 102 and 103.
Need to prove, the active chip of this process of process is still bare chip.
Second stage: embedding stage of active chip.Fig. 4 a-4h is the manufacturing process that in embodiment of the present invention chip packaging method, active chip is embedded into the medium central layer.
Step S412, consult Fig. 4 a, select glass or metal material or epoxy resin, span to come organic materials such as vinegar imines-cyanate resin, liquid crystal polymer etc. as upper loading plate, adopt interim bonding film 104 pre-configured, fix active chip 100 at least one, upper active chip 100 active surfaces are connected with upper loading plate 105, and on this, active chip 100 is active bare chip;
Step S414, consult Fig. 4 b, select glass or metal material or epoxy resin, span to come organic materials such as vinegar imines-cyanate resin, liquid crystal polymer etc. as lower loading plate, adopt interim bonding film 204 pre-configured, fix at least one lower active chip 200, lower active chip 200 is consulted Fig. 3 a-3e and is made, its active surface is connected with lower loading plate 205, and this time active chip 200 is active bare chip;
Step S416 consults Fig. 4 c, and adopting epoxy resin, span to come the organic materials such as vinegar imines-cyanate resin, polyimides or liquid crystal polymer is the semi-solid preparation dielectric layer, and thickness is generally selected 25 to 500 μ m.This semi-solid preparation dielectric layer is one deck or multilayer (being two-layer in Fig. 4 c).To be bonded with the upper loading plate 105 of upper active chip 100, the lower loading plate 205 that is bonded with lower active chip 200 and semi-solid preparation dielectric layer 300 by the vacuum hotpressing bonding method and carry out the vacuum hotpressing bonding, its laminar structure is followed successively by the lower loading plate that is bonded with lower active chip from top to bottom, organic dielectric layer is bonded with the upper loading plate of active chip.
Need in making first to locate, have at least the upper loading plate of an active chip and lower loading plate to aim at respectively to above-mentioned configuration, the centre adds organic dielectric layer to carry out the vacuum hotpressing bonding, and bonder is with camera, can aim at the location, the device after the vacuum hotpressing bonding is as shown in Fig. 4 d.Upper active chip and lower active chip embed in the semi-solid preparation medium, form integrated central layer after one or more layers sheet semi-solid preparation medium solidifies;
Step S418 consults Fig. 4 e, adopt to separate bonding method, makes interim bonding film and central layer separate, can remove so above-mentioned embedding upper active chip and lower active chip central layer both sides interim bonding film and go up loading plate and lower loading plate.
Phase III: outer circuit patterning stage.Fig. 4 f-4h prepares the manufacturing process of outer circuit figure in central layer both sides in embodiment of the present invention chip packaging method.
Step S420 consults Fig. 4 f, adopts lamination process to carry out simultaneously wired media layer 301 and 302 and the making of metal level 303 and 304 to the central layer two sides of above-mentioned embedding two active chips;
Step S422 consults Fig. 4 g, the central layer of above-mentioned embedding two active chips is carried out the making of ground floor outer-layer circuit;
Carry out the making of blind hole by laser drill, carry out the preparation of through hole by machine drilling, and adopt electroless copper plating and electric plating method to carry out hole metallization and filling, form conductive blind hole 106 in blind hole, make this skin wiring layer can be electrically connected to the electrode 101 of active chip 100 on this; Form conductive blind hole 206 in blind hole, make this wiring layer can be electrically connected to the electrode 201 of this time active chip 200; Form conductive through hole 305 in through hole, make the up and down wiring layer to be electrically connected;
Step S424 consults Fig. 4 h, has the module of at least two active chips to carry out the making of the second outer-layer circuit to above-mentioned with the embedding of the first outer-layer circuit;
Adopt circuit to increase layer process the making of the second wiring layer is carried out on the module two sides simultaneously, certainly can also continue to increase layer, decide according to the needs of oneself.Thereby promote its process quality and be electrically connected reliability.
So far, the present embodiment active chip method for packing is described.
In another exemplary embodiment of the present invention, also provide a kind of active chip method for packing.The difference of the present embodiment and first embodiment is, has carried out simultaneously the embedding of active chip and passive component at second stage.This chip packaging method is divided into three phases equally: (1) makes the passivation layer stage to active chip; (2) the embedding stage of active chip/passive component; (3) the outer circuit patterning stage.Below this three phases is illustrated respectively.
Phase I: active chip is made the passivation layer stage.
This stage is identical with respective stage in above-described embodiment, no longer repeats herein, can be with reference to the related description of Fig. 3 a-3e.
Second stage: embedding stage of active chip/passive component.Fig. 5 a-5e is embedded into active chip and passive component the manufacturing process of medium central layer simultaneously in embodiment of the present invention chip packaging method.
Step S512, consult Fig. 5 a, select glass or metal material or epoxy resin, span to come organic materials such as vinegar imines-cyanate resin, liquid crystal polymer etc. as upper loading plate, adopt interim bonding film 104 pre-configured, fix active chip 100 and passive component 400 at least one, upper active chip 100 active surfaces are connected with upper loading plate 105, passive component 400 active surfaces are connected with upper loading plate 105, and on this, active chip is active bare chip;
Step S514, consult Fig. 5 b, select glass or metal material or epoxy resin, span to come organic materials such as vinegar imines-cyanate resin, liquid crystal polymer etc. as lower loading plate, adopt interim bonding film 204 pre-configured, fix at least one lower active chip, lower active chip 200 is consulted Fig. 3 a-3e and is made, its active surface is connected with lower loading plate 205, and this time active chip is active bare chip;
Step S516 consults Fig. 5 c, and adopting epoxy resin, span to come the organic materials such as vinegar imines-cyanate resin, polyimides or liquid crystal polymer is dielectric layer, generally selects 25 to 500 μ m.
To be bonded with the upper loading plate 105 of upper active chip 100 and passive component 400, the lower loading plate 205 that is bonded with lower active chip 200 and organic dielectric layer 300 by the vacuum hotpressing bonding method and carry out the vacuum hotpressing bonding, its laminar structure is followed successively by the lower loading plate of the lower active chip of bonding from top to bottom, organic dielectric layer is bonded with the upper loading plate of active chip and passive component.Need in making first to locate, the upper loading plate of at least one active chip of above-mentioned configuration and passive component and the lower loading plate of at least one active chip of configuration are aimed at respectively, the centre adds organic dielectric layer to carry out thermocompression bonding, bonder is with camera, can aim at the location, the device after thermocompression bonding is as shown in Fig. 5 d.Upper active chip, lower active chip and passive component embed in the semi-solid preparation medium, form central layer after sheet semi-solid preparation medium solidifies;
Step S518, consult Fig. 5 e, adopt to separate the method for bonding, make interim bonding film separate with central layer, embeddingly have the structure of at least two active chips and at least one passive component to remove interim bonding film and upper loading plate and the lower loading plate on both sides to above-mentioned like this.
Phase III: outer circuit patterning stage.Fig. 5 f-5h prepares the manufacturing process of outer circuit figure in central layer both sides in embodiment of the present invention chip packaging method.The manufacturing process of the present embodiment chip packaging method ectomesoderm circuitous pattern preparatory phase.
Step S520 consults Fig. 5 f, adopts lamination process to carry out simultaneously wired media layer 301 and 302 and the making of metal level 303 and 304 to the above-mentioned embedding central layer two sides that at least two active chips and at least one passive component arranged;
Step S522 consults Fig. 5 g, has the central layer of at least two active chips and at least one passive component to carry out the making of ground floor outer-layer circuit to above-mentioned with the outer wiring layer of one deck is also embedding;
Carry out the making of blind hole by laser drill, carry out the preparation of through hole by machine drilling, and adopt electroless copper plating and electric plating method to carry out hole metallization and filling, and form conductive blind hole 106 in blind hole, make this wiring layer can be electrically connected to the electrode 101 of active chip 100 on this; Form conductive blind hole 206 in blind hole, make this wiring layer can be electrically connected to the electrode 201 of this time active chip 200; Form conductive blind hole 406 in blind hole, make this wiring layer can be electrically connected to the electrode 401 of this passive component 400; Form conductive through hole 305 in through hole, make the up and down wiring layer to be electrically connected;
Step S524 consults Fig. 5 h, has the module of at least two active chips and at least one passive component to carry out the making of the second outer-layer circuit to above-mentioned with the embedding of the first outer-layer circuit;
Adopt circuit to increase layer process the making of the second wiring layer is carried out on the module two sides simultaneously, certainly can also continue to increase layer, decide according to the needs of oneself.Thereby promote its process quality and be electrically connected reliability.
So far, this embodiment chip packaging method is described.
From technique scheme as can be known, active chip base plate for packaging of the present invention and the method for preparing this substrate have following beneficial effect:
(1) to adopt active bare chip directly to carry out embedding in the present invention, the generation of bubble between salient point and salient point when having avoided packaged chip embedding;
(2) in the present invention, without encapsulation, and pass through the slimming processing due to active bare chip, thereby realized microminaturization and the lightweight of encapsulating structure, therefore simplified substrate manufacture technique, improved production efficiency;
(3) the present invention has realized that a plurality of active chips imbed in the substrate two sides, has improved integrated level; Simultaneously on the substrate two sides, the very large degree of freedom and space are arranged, sustainablely carry out multilayer wiring, thereby promoted process quality and be electrically connected reliability;
(4) method of the whole process using of the present invention can with the planar semiconductor process compatible, realized the integrated making of substrate.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (16)
1. an active chip base plate for packaging, is characterized in that, comprising:
Central layer;
Active chip at least one embeds in described central layer, and its active surface is towards the lower surface of described central layer, and on this, active chip is active bare chip; And
At least one lower active chip embeds in described central layer, and its active surface is towards the upper surface of described central layer, and this time active chip is active bare chip.
2. active chip base plate for packaging according to claim 1, is characterized in that, described central layer is that any in following material forms through hot-press solidifying:
Epoxy resin, polyimides, span come vinegar imines-cyanate resin, liquid crystal polymer, ABF film, polyphenylene oxide, polytetrafluoroethylene, Parylene or stupid the third cyclobutane.
3. active chip base plate for packaging according to claim 1, is characterized in that, described active bare chip comprises: the first passivation layer and the second passivation layer;
Described the first passivation layer is formed at the active surface of described active bare chip, has window in the position of active bare chip active surface electrode;
Described the second passivation layer is formed at the surface of described the first passivation layer and the window's position of active bare chip active surface electrode, and its surface toward the outer side is the plane;
The second passivation layer of described upper active chip and the lower surface of described central layer are coplanar; The second passivation layer of described lower active chip and the upper surface of described central layer are coplanar.
4. active chip base plate for packaging according to claim 3, is characterized in that, the material of described the first passivation layer is silicon nitride; The material of described the second passivation layer is polyimides.
5. the described active chip base plate for packaging of any one according to claim 1 to 4, is characterized in that, also comprises:
At least one passive chip embeds in described central layer, and its active surface is towards lower surface or the lower surface of described central layer.
6. the described active chip base plate for packaging of any one according to claim 1 to 4, is characterized in that, also comprises:
The wired media layer is formed at upper surface and the lower surface of described central layer;
The outer circuit figure is formed on described dielectric layer, and it is connected with the active surface electrode of described active bare chip by the metalized blind vias of passing described dielectric layer and described the second passivation layer.
7. active chip base plate for packaging according to claim 6, is characterized in that, in the one side at least of described central layer, described wired media layer and outer circuit figure are mutual stacked multilayer.
8. a method that is prepared with the source chip base plate for packaging, is characterized in that, comprising:
Active surface one side of active chip at least one is fixed in upper loading plate by interim bonding film bonding; Active surface one side of at least one lower active chip is fixed in lower loading plate by interim bonding film bonding; Described upper active chip and lower active chip are naked active chip;
Active surface one side of described upper active chip and described lower active chip all toward the outer side, add one deck sheet semi-solid preparation medium at least on described in the middle of loading plate and lower loading plate, the thickness of described at least one lamellar semi-solid preparation medium is greater than thickness or upper active chip and the lower active chip thickness sum of thickness or the lower active chip of described upper active chip;
Described upper loading plate, at least one lamellar semi-solid preparation medium and lower loading plate are carried out the vacuum hotpressing bonding, described at least one active chip and at least one lower active chip embed in the described semi-solid preparation of one deck at least medium, form central layer after described at least one lamellar semi-solid preparation medium solidifies;
Separate bonding and remove the interim bonding film of described central layer both sides, described upper loading plate and lower loading plate are removed thereupon, thereby descend active chip to be encapsulated in described central layer with at least one described at least one upper active chip, are formed with the source chip base plate for packaging.
9. the method that is prepared with the source chip base plate for packaging according to claim 8, is characterized in that,
Described interim bonding film is for realizing active chip and loading plate bonding, and by ultraviolet light, thermal decomposition or the solvolysis film except described bonding;
Described sheet semi-solid preparation medium is selected from a kind of in following material: epoxy resin, polyimides, span come vinegar imines-cyanate resin, liquid crystal polymer, ABF film, polyphenylene oxide, polytetrafluoroethylene, Parylene or stupid the third cyclobutane.
10. the method that is prepared with the source chip base plate for packaging according to claim 8, is characterized in that, described active surface one side with active chip at least one is fixed in upper loading plate by interim bonding film bonding; Active surface one side of at least one lower active chip is also comprised by the step that interim bonding film bonding is fixed in lower loading plate before:
Make a plurality of continuous active chips on wafer, on each active chip with a plurality of electrodes;
Form the first passivation layer on described wafer, and window on described the first passivation layer, to expose the described metal electrode of described active chip;
Make the second passivation layer on described first passivation layer of windowing, this second passivation layer covers described the first passivation layer, and fills windowing of described the first passivation layer;
Described wafer is cut, form a plurality of active chips, the upper surface of each active chip is all with described the first passivation layer and described the second passivation layer, and described upper active chip and lower active chip all are selected from described a plurality of active chip.
11. the method that is prepared with the source chip base plate for packaging according to claim 10 is characterized in that, the material of described the first passivation layer is silicon nitride; The material of described the second passivation layer is polyimides.
12. the method that is prepared with the source chip base plate for packaging according to claim 10 is characterized in that, the described step that wafer is cut also comprises before:
The back side of described wafer is carried out attenuate and polished.
13. the method that is prepared with the source chip base plate for packaging according to claim 10 is characterized in that, described at least one active chip and at least one lower active chip also comprise after being encapsulated into step in described central layer:
Make respectively wired media layer and outer wiring layer on the two sides of described central layer;
Two sides at described central layer forms respectively blind hole, and this blind hole is passed the second passivation layer of described wired media layer and active chip, and this active chip is upper active chip and/or lower active chip;
Plated metal in described blind hole forms conductive blind hole, and the electrode of described active chip is electrically connected to described outer wiring layer by described conductive blind hole;
Outer wiring layer to described central layer two sides carries out respectively etching, forms the outer circuit figure.
14. the method that is prepared with the source chip base plate for packaging according to claim 13 is characterized in that, described outer wiring layer to the central layer two sides carries out respectively also comprising before the step of etching:
Two sides at described central layer forms conductive through hole, and this conductive through hole is electrically connected the outer wiring layer on described central layer two sides.
15. the method that is prepared with the source chip base plate for packaging according to claim 13 is characterized in that, also comprises after the step of described formation outer circuit figure:
In the one side at least of described central layer, continue to form one or more layers wired media layer and outer circuit figure.
16. according to claim 8 to 15, the described method that is prepared with the source chip base plate for packaging of any one, is characterized in that,
Described active surface with active chip at least one also comprises simultaneously by the step that interim bonding film bonding is fixed in upper loading plate: the active surface of at least one passive component is fixed in upper loading plate by described interim bonding film bonding; And/or described active surface with at least one lower active chip also comprises simultaneously by the step that interim bonding film bonding is fixed in lower loading plate: the active surface of at least one passive component is fixed in lower loading plate by described interim bonding film bonding;
The described step that the lower active chip of active chip at least one and at least one is embedded in described semi-solid preparation medium comprises simultaneously: described at least one passive component is embedded in described semi-solid preparation medium.
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Effective date of registration: 20191205 Address after: 214028 Jiangsu New District of Wuxi City Linghu Road No. 200 Chinese Sensor Network International Innovation Park building D1 Patentee after: National Center for Advanced Packaging Co.,Ltd. Address before: 200331 room 155-2, ginkgo Road, Shanghai, Putuo District, China, 4 Patentee before: Shanghai State Intellectual Property Services Co.,Ltd. |