CN1758430A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN1758430A CN1758430A CN200510102531.2A CN200510102531A CN1758430A CN 1758430 A CN1758430 A CN 1758430A CN 200510102531 A CN200510102531 A CN 200510102531A CN 1758430 A CN1758430 A CN 1758430A
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- insulating resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained. Further, since the forming ability of the conductor layer connecting the front and rear surfaces and the insulation layer is high, the manufacturing cost can be reduced.
Description
Technical field
The present invention relates to be suitable for load the semiconductor device and the manufacture method thereof of the multi-chip encapsulation body of a plurality of semiconductor elements (semiconductor chip).
Background technology
In the last few years, for miniaturization, the high density assemblingization that realizes semiconductor device, realized in 1 packaging body, being sealed with the stacked multi-chip packaging body of a plurality of semiconductor elements (chip) lamination.In general, in the stacked multi-chip packaging body, being electrically connected between the electrode part of each electrode pad that has carried out a plurality of semiconductor chips by means of the lead-in wire bonding and substrate.In addition, between a plurality of semiconductor chips under the situation connected to one another, with the lead-in wire bonding being electrically connected between the electrode pad of each semiconductor chip.
Just as the stacked multi-chip packaging body such, be applied to the lead-in wire bonding between semiconductor chip and the substrate or the package body structure that is connected between a plurality of semiconductor chip, result from the increase that connects the needed cost of operation, man-hour and be easy to produce manufacturing cost.In addition, have that not only signal routing length is elongated, and the problem that maximizes of packaging body shape.
So, people just proposed connect connector (attachment plug) or connect path be applied between semiconductor chip and the substrate with a plurality of semiconductor chips between the scheme that is connected (for example, opening flat 10-223833 communique) referring to the spy.
Can be applicable to the attachment plug of the connection etc. between semiconductor chip, for example, have the through hole that on semiconductor substrate, connects its table back of the body two sides, use the method for in this through hole, filling metal etc. to form the structure of conductor layer.Being connected between the electrode pad of attachment plug and semiconductor substrate surface, the wiring technique that can the common semiconductor technology of applications exploiting carries out.
In addition, constitute between the inner face (side wall surface) of surface, through hole of the conductor layer of attachment plug and semiconductor substrate and must insulate, these insulation people use the SiO that is formed by CVD method (LPCVD method) etc. always
2Layer, Si
3N
4The inorganic insulation thing layer of layer or their stack membrane and so on.
But, the said SiO in top
2Layer, Si
3N
4The inorganic insulation thing layer of layer etc. will form on the inner face of through hole equably, is difficult technically, particularly exists the problem that is difficult to form thick film.As mentioned above, use the formed inorganic insulation thing of conventional semiconductor technology layer, just become the principal element of the insulating reliability reduction of the attachment plug that makes the table back of the body two sides that connects semiconductor chip.
In addition, under the situation that forms inorganic insulation thing layer on the inner face of through hole, also exist the problem that is difficult to fill the conductor of metal etc. technically to the inside of through hole.With regard to this point, form equally with common through hole, though also can consider only on the wall of through hole, to form conductor layer,, in this case, but can produce the problem that the mechanical strength of semiconductor chip reduces.
Summary of the invention
The present invention finishes in order to tackle such problem, purpose is to provide and can improves the conductor layer that couples together between the table of semiconductor substrate back of the body two sides and the formation of insulating barrier, realize to form the reduction of cost etc., and can improve the semiconductor device and the manufacture method thereof of the insulating reliability of the conductor layer that constitutes attachment plug etc.
Form 2 of the present invention is manufacture methods of semiconductor device, comprises following operation: form the operation of through hole to irradiating laser on the integrated semiconductor substrate that is formed with element on the surperficial side; In above-mentioned through hole, fill the operation of insulating resin; In the insulating resin of filling, form the operation in the diameter resin hole littler with one heart than above-mentioned through hole with above-mentioned operation; And form conductor layer at above-mentioned resin hole inner face, form the operation of the through hole conducting portion of the surface that makes above-mentioned semiconductor substrate and back side conducting.
Description of drawings
Though the present invention wants the limit to describe referring to the accompanying drawing limit,, these accompanying drawings only provide for diagram, and no matter saying on what meaning neither be to the qualification of invention.
The profile of Fig. 1 has illustrated the formation of the semiconductor device of example 1 of the present invention.
The profile of Fig. 2 has illustrated preceding half the operation of manufacture method of the semiconductor device of example 2 of the present invention.
The profile of Fig. 3 has illustrated the operation of centre of manufacture method of the semiconductor device of example 2 of the present invention.
The profile of Fig. 4 has illustrated the later half operation of manufacture method of the semiconductor device of example 2 of the present invention.
The profile of Fig. 5 has illustrated the formation of the semiconductor device of example 3 of the present invention.
The profile of Fig. 6 has illustrated the formation of the semiconductor device of example 4 of the present invention.
The profile of Fig. 7 has illustrated the formation of the stacked package body of the semiconductor device that uses example 4 of the present invention.
The profile of Fig. 8 has illustrated the manufacturing process of the semiconductor device of example 5 of the present invention.
The profile of Fig. 9 has illustrated the formation of the semiconductor device of example 6 of the present invention.
The profile of Figure 10 has illustrated the manufacturing process of the semiconductor device of example 7 of the present invention.
The profile of Figure 11 has illustrated the formation of the semiconductor device of example 8 of the present invention.
The profile of Figure 12 has illustrated the manufacturing process of the semiconductor device of example 9 of the present invention.
The profile of Figure 13 has illustrated the formation of the semiconductor device of example 10 of the present invention.
The profile of Figure 14 has illustrated the variation of semiconductor device shown in Figure 13.
The profile of Figure 15 has illustrated the manufacturing process of the semiconductor device of example 11 of the present invention.
The profile of Figure 16 has illustrated an example of the formation operation of the porous matter insulating resin layer in the manufacturing process of semiconductor device shown in Figure 15.
The profile of Figure 17 has illustrated another example of the formation operation of the porous matter insulating resin layer in the manufacturing process of semiconductor device shown in Figure 15.
The profile of Figure 18 has illustrated the example of semiconductor device of the stacked multi-chip structure of the semiconductor device that uses example 10 of the present invention.
Embodiment
Semiconductor device and manufacture method thereof according to a form of the present invention, then can be easily and obtain at low cost in through hole, having Jie by with the conductor layer of being adjacent to property of inner wall surface thereof good insulation performance resin bed insulation, be suitable for the high semiconductor device of insulating reliability that lamination loads the multi-chip encapsulation body etc. of a plurality of semiconductor chips.
Below, describe being used for implementing form of the present invention.In addition, though be that example is described with reference to the accompanying drawings in the following description,, these accompanying drawings only provide for diagram, and the present invention is not limited to these accompanying drawings.
The profile of Fig. 1 has illustrated the formation of the semiconductor device of example 1 of the present invention.In the figure, the semiconductor substrate of the integrated from the teeth outwards silicon substrate that is formed with function element etc. of label 1 expression etc.In other words, surface one side of semiconductor substrate 1, as element area, the multilayer wiring portion that is formed with integrated component portion and each interelement is coupled together (silicon wire layer) 2 etc.In addition, on the surface of semiconductor substrate 1, be formed with the Al electrode (pad) 3 that is connected in its inner multilayer wiring portion.This semiconductor substrate 1 has the through hole 4 at the perforation table back side.The formation of through hole 4 can be carried out by means of the irradiation of laser, and the inner face of through hole 4 (side wall surface) is to use the silicon of impalpable structure to constitute.
Then, on the inner face of the through hole 4 that the silicon with impalpable structure constitutes, form the layer 5 that constitutes by the 1st insulating resin.Can use polyimide resin, benzene two cyclobutane resins, epoxy resin, phenolic resin, cyanate ester resin, bimaleimide resin, bismaleimide-triazine resin, polybenzoxazole, butadiene resin, silicones, polycarbonamide, polyurethane resin etc. as the 1st insulating resin here.
In addition, on the predetermined zone at the surface of semiconductor substrate 1 and the back side, be formed with the layer 6 that constitutes by the 2nd insulating resin respectively.Said the 1st insulating resin in the 2nd insulating resin and top both can be that same resin also can be different resin.
Then the through hole 4 of surface one side of the bottom of the top of the 1st insulating resin layer 5 in through hole 4 and through hole 4 and semiconductor substrate 1 around, form the conductor layer 7 of Ti, Ni, Cu, V, Cr, Pt, Pd, Au, Sn etc.In addition, on the end of the through hole 4 of the back side of semiconductor substrate 1 side, form backplate 8.Conductor as constituting backplate 8 also can use Ti, Ni, Cu, V, Cr, Pt, Pd, Au, Sn etc.So, just can form by means of the conductor layer 7 that in through hole 4, forms the table of semiconductor substrate 1 is carried on the back the through hole conducting portion (perforation path) that electrical connection is got up, the Al electrode 3 on the surface of semiconductor substrate 1 and backplate 8 be coupled together by this perforation path.
In the example 1 that constitutes like this, insulating material as the inner face (side wall surface) that covers through hole 4, because what use is insulating resin (the 1st insulating resin), so, remove cost low outside, thick insulation thickness can also be stably formed, good insulation performance and reliability can be guaranteed.
In addition,, be formed with insulating resin layer (the 1st insulating resin layer 5) above that, so this insulating resin layer and be good as the being adjacent to property between the silicon of substrate because the side wall surface of through hole 4 constitutes with the silicon of impalpable structure.In other words, in general because silicon and being adjacent to property of resin material are poor, form under the situation of insulating resin layer in the through hole with formation such as RIE (reactive ion etching) on silicon substrate, owing to resulting from the thermal stress of difference of insulating resin layer and conductor layer that forms and the thermal coefficient of expansion between the silicon above that, just be easy to produce the peeling off of insulating resin layer, crackle etc.But in the semiconductor device of example 1, through hole 4 forms by means of laser radiation, and the side wall surface of through hole 4 becomes the silicon of impalpable structure, so and the being adjacent to property height between the insulating resin layer.Therefore, can obtain the high conducting portion of reliability (conduction path).
Secondly, referring to Fig. 2～Fig. 4 the example 2 as the manufacture method of the semiconductor device of the said example 1 in top is described.In example 2, at first, shown in Fig. 2 A, by means of common semiconductor technology, the multilayer wiring portion (silicon wire layer) 2 of preparing to be formed with from the teeth outwards integrated component portion, each interelement being coupled together and be connected to the semiconductor substrate (silicon wafer) 1 of Al electrode 3 in the multilayer wiring portion etc., after BSG being with 9 paste on its surface, carry out grinding back surface.At this moment, in order to improve rupture strength, also can carry out the processing of dry tumbling, RIE, CMP (cmp) etc. at last.
Secondly, be with after 9, shown in Fig. 2 B, after being attached on the back side, form through hole 4 to retainer belt 10 to semiconductor substrate 1 irradiating laser at the BSG of stripper surface.As the laser that will shine, though can use for example YAG laser of wavelength 355nm,, Wavelength of Laser is not limited to this.When carrying out the perforate of semiconductor substrate 1, both can also perforate on retainer belt 10, also can carry out cleaning as required after the perforate with laser.In addition, the flying when guarding against perforate also can form diaphragm in advance on the surface of semiconductor substrate 1, remove this diaphragm after perforate again.
Then, shown in Fig. 2 C, from the insulating resin 11 of the back side one side printing polyimide resin of semiconductor substrate 1 etc., filling insulating resin 11 to through hole 4 in.The filling of the insulating resin 11 that is undertaken by printing also can be carried out in a vacuum.Under the situation of printing in a vacuum, can eliminate the space in the insulating resin 11.In addition, the filling of carrying out in the through hole 4 of insulating resin 11 also can be carried out with the roller coating mode.In retainer belt 10, also have the hole, and under the situation of the open through holes 4 of these sides of retainer belt 10, can be easily and carry out the filling of insulating resin 11 in through hole 4 reliably.
Secondly, shown in Fig. 2 D, remove the lip-deep insulating resin 11 that is overlayed on semiconductor substrate 1 by means of grinding.This operation is carried out as required.Then, on exchangining cards containing all personal details and become sworn brothers after the retainer belt 10, cutting, the insulating resin 11 that highlights on grinding overleaf make the flattening surface of semiconductor substrate 1.If insulating resin 11 is few to the overhang on surface, this grinding can not carried out yet.
Then, shown in Fig. 2 E, on the surface that retainer belt 10 has been attached to semiconductor substrate 1 after, go up to form insulating resin film 12 overleaf.As this insulating resin, for example, can use polyimide resin, can carry out film formation by means of spin coated or printing.Also can form with roller coating mode or curtain formula application pattern.By the method for the aqueous insulating resin of employing coating, though can form insulating resin film 12 with low cost,, also can adopt the method for pasting dry film.
Secondly, shown in Fig. 3 F, after bonding to the back side of semiconductor substrate 1 on the glass support 14 by bonding agent (for example, UV cured type bonding agent) 13, insulating resin 11 irradiating lasers in being filled into through hole 4 form the resin through hole 15 of minor diameter with one heart.At this moment employed laser and since perforate processing to as if resin, so both can be that the carbon dioxide gas volumetric laser also can be a YAG laser.
In addition, using under the situation of photosensitive insulating resin, also can form resin through hole 15 by means of exposure, development as the insulating resin 11 of in through hole 4, filling.No matter adopt any method, compare with the CVD method, can in through hole 4, easily form the insulating resin layer of enough thickness.In addition, be present in the insulating resin of aluminium electrode 3 tops on the surface of semiconductor substrate 1, can when the formation of resin through hole 15, remove or remove individually as required.
Then, shown in Fig. 3 G, on the side wall surface and bottom of the surface of semiconductor substrate 1 and resin through hole 15, form layer (the inculating crystal layer metal) 16 of conductor metals such as Ti, Ni, Cu, V, Cr, Pt, Pd, Au, Sn by means of the electroless plating method of applying.Can not use the deposited method of electroless plating and replace and use vapour deposition method or sputtering method.Can form more good conductor metal layer 16 by vapour deposition method or sputtering method.
Then, shown in Fig. 3 H, expose after having formed resist layer, develop in the top of formed conductor metal layer 16 on the surface of semiconductor substrate 1, forms resist figure 17.Resist both can be aqueous also can be film.Then, be electrode with the conductor metal layer 16 that forms in the operation formerly, form the electrolysis plating layer 18 of Ni/Cu, Cu, Cu/Ni/Au etc.Then, shown in Fig. 3 I, after peeling off resist figure 17, remove conductor metal layer 16 as electrode by means of etching.So, just can be on the side wall surface and bottom of the predetermined zone on the surface of semiconductor substrate 1 and resin through hole 15, form the conductor layer 19 that conductor metal layer 16 and electrolysis plating layer 18 laminations are got up.
Then, shown in Fig. 4 J, as required, form diaphragm (wiring nurse tree adipose membrane) 20 from the teeth outwards by means of coating or stickup, the formation peristome exposes, develops.The formation of diaphragm 20 both can be that the method for the aqueous material of coating also can be the method for sticking film.When forming diaphragm 20, need under the situation of flatness, also can use the resin landfill resin through hole 15 that forms diaphragm 20.In addition, also can form diaphragm 20 again after the resin landfill resin through hole 15 with other in advance.
Then, be under the situation of Ni/Cu, Cu layer at conductor metal layer 16, in the peristome of diaphragm 20, apply the conductor layer 21 that method forms Au, Ni/Au etc. with electroless plating.This conductor layer 21, because connection electrode that can be when the chip-stack, so though also can be on through hole 4,, also can on through hole position in addition, form.Using under the situation of scolder as connected mode, diaphragm 20 plays a part solder resist.Not using diaphragm 20 generation by coating or paste resist; expose, develop formed figure after; make under the situation of conductor metal layer 16 for Ni/Cu, Cu layer, also can adopt and use electroless plating to apply the conductor layer 21 that method forms Au, Ni/Au etc., peel off the method for resist.In this case, just no longer need solder resist.
Then, shown in Fig. 4 K, the upper glass support 14 of exchangining cards containing all personal details and become sworn brothers on the surface of semiconductor substrate 1, by bonding agent 13 bonding after, be under the situation of Ni/Cu, Cu layer at conductor metal layer 16, form the electroless plating coating 22 of Au, Ni/Au in the through hole portion overleaf.Form backplate like this.
Then, peel off glass support 14, shown in Fig. 4 L, paste cutting belt 23 on the back side as required after, the processing of cutting etc.So, just can only on the surface of semiconductor substrate 1, form wiring layer again, just can obtain through hole 4 tops have and other chip between the semiconductor device of connection electrode.
According to the example 2 that constitutes like this, then can make the high semiconductor device of reliability of structure that is suitable for a plurality of semiconductor chips of lamination.In addition, remove outside the device of the costliness that needn't use RIE and so on, because mask exposure, developing procedure are few, so can obtain semiconductor device with low cost.
In addition, because the formation of through hole 4 on semiconductor substrate 1 carries out by means of laser radiation, the side wall surface of through hole 4 is made of the silicon of impalpable structure, so and be filled into being adjacent to property height between the interior insulating resin 11 of through hole 4.In addition, the side wall surface of through hole 4 has been covered reliably by the insulating resin 11 till the back side of arrival semiconductor substrate 1, just guaranteed to constitute the insulation between the conductor metal layer 16 of silicon and inboard of side wall surface of through hole 4 by means of this insulating resin 11, so can form the high perforation path (conducting portion) of reliability.
Secondly, another example of the present invention is described.The profile of Fig. 5 has illustrated the semiconductor device of example 3.In Fig. 5, the wiring layer of the label 24 expression back sides one side.This wiring layer 24 has the structure that is formed with the electrolysis plating layer of Ni/Cu, Cu, Cu/Ni/Au etc. at the top lamination of conductor metal layer (inculating crystal layer metal).In addition, the electroless plating coating of label 25 expression Au, Ni/Au etc., 26 expression diaphragms (wiring nurse tree adipose membrane).In Fig. 5, for the additional identical label of the part identical and omit explanation with example shown in Figure 11.
In the semiconductor device of example 3, as shown in Figure 5, not only on the surface of semiconductor substrate 1, go up overleaf and also be formed with wiring layer 24, on the back side of semiconductor substrate 1, from connecting the top of the wiring layer 24 that path extracts, be formed with and other semiconductor device between connection electrode.
Want to make the semiconductor device of example 3, will with example 2 similarly, carrying out in order from Fig. 2 A after the operation shown in Fig. 4 J, the glass support is exchanged cards containing all personal details and become sworn brothers on the surface of semiconductor substrate 1.Then, apply method or vapour deposition method or sputtering method, on the whole back side of the semiconductor substrate 1 that comprises 4 ones of through holes, form conductor metal layer (inculating crystal layer metal) by means of electroless plating.
Then, top at this conductor metal layer forms resist, and after having carried out exposure, development, is that electrode forms the electrolysis plating layer by Ni/Cu, Cu, Cu/Ni/Au etc. with the conductor metal layer, after peeling off resist, remove conductor metal layer as electrode by means of etching.Then, form diaphragm on the whole, expose, develop formed peristome after, by means of electroless plating apply in peristome, form Au, Ni/Au etc. the layer.This electroless plating coating, because connection electrode that can be when the chip-stack, so, also can on through hole position in addition, form though can be on through hole.
Then, peel off the glass support, the processing of cutting etc.So, then can obtain not only on the surface of silicon wafer, go up overleaf and also form wiring again, the wiring top that from connect path, extracts be formed with and other semiconductor chip between the semiconductor device of connection electrode.
In addition, in the manufacturing process of the semiconductor device of example 2 and 3, though explanation is the example that forms wiring by means of semi-additive process on the surface of semiconductor substrate and the back side,, also can not use semi-additive process, use full additive method or subraction to form wiring layer and replace.In addition, in the manufacturing process of example 3, though be that the glass support is pasted on a side the face (surface) of semiconductor substrate 1, form conductor metal layer (inculating crystal layer metal), and similarly form resist in the operation shown in Fig. 3 H and Fig. 3 I to form wiring figure, then, the glass support is exchanged cards containing all personal details and become sworn brothers on the opposing party's the face (back side) of semiconductor substrate 1, similarly form wiring figure, still, also can not use the glass support to carry out.In this case, also can be after having formed through hole, on the side wall surface of the two sides of semiconductor substrate and through hole, form conductor metal layer by means of plating successively or simultaneously.Then, on the two sides, carry out resist successively or simultaneously and form, and then relend and help plating and on the two sides of semiconductor substrate, form wiring layer simultaneously.At this moment, also can in the formation of wiring layer, on the side wall surface of through hole, form conductor layer by means of plating.If use this method, then has the advantage of the formation of the conductor layer that can connect path and wiring layer with operation (plating operation) still less.
Secondly, another example of the present invention is described.
The profile of Fig. 6 has illustrated the formation of the semiconductor device of example 4 of the present invention.In Fig. 6, label 31 is semiconductor substrates of silicon wafer and so on, and its back side one side is as element area, the multilayer wiring portion 32 that is formed with integrated component portion and each interelement is coupled together.In addition, on the surface of semiconductor substrate 31, be formed be connected in the multilayer wiring portion can be used for and the outside between the electrode pad 33 of signal reception and registration etc.In addition, on semiconductor substrate 31, also be formed with the through hole 34 of the perforation table back of the body.On the table back of the body two sides of semiconductor substrate 31 with through hole 34, carry out contiguously the resin sheet that lamination respectively has the one-side band Copper Foil with the resin face, carry on the back on the two sides at the inner face (side wall surface) of through hole 34 and the table of semiconductor substrate 31, be coated with the insulating resin layer 35 of the resin sheet formation of the one-side band Copper Foil that gets up with lamination.
In addition, on the outside that is formed at the insulating resin layer 35 on the table back of the body two sides of semiconductor substrate 31, be formed with wiring layer 36.This wiring layer 36 has employing the Copper Foil of the resin sheet of one-side band Copper Foil is carried out the formed copper clad patterns layer of way of figure processing and 2 layers of such structure of copper plating layer of formation above that.Also can further form the plating layer of Ni/Au etc. in the top of copper plating layer.In addition, insulating resin layer 35 tops in the inside of through hole 34 in the mode that the wiring layer 36 on the two sides of semiconductor substrate 31 is coupled together, form the joint pin 37 of the electric conductor of copper etc.In addition, in Fig. 6, label 38 is illustrated on the insulating resin layer 35 of the inside that is disposed at through hole 34 and forms, the resin hole of the minor diameter that diameter is littler than through hole 34.In addition, label 39 is illustrated in the interior formed electric conductor (copper) of opening of the insulating resin layer 35 of 33 ones of electrode pads.
In the semiconductor device of the example 4 that constitutes like this, use the resin sheet of one-side band Copper Foil to form insulating resin layer 35 and wiring layer 36, the member of using by means of printed board more cheaply constitutes.In addition, wiring layer 36, owing to become to having employing the Copper Foil of the resin sheet of one-side band Copper Foil carried out the formed copper clad patterns layer of way of figure processing and 2 layers of such structure of copper plating layer of formation above that, so and between the insulating resin layer 35 of lower floor to be adjacent to intensity big, resistances to impact etc. are good.In other words, the formed copper clad patterns layer of lamination with the resin sheet of one-side band Copper Foil, because and insulating resin layer 35 between the interface on have a lot of fine concavo-convex, so with the copper plating layer comparison of the top that directly is formed at insulating resin layer 35, and between the lower floor to be adjacent to intensity big.Specifically, be 0.6～0.8Kgf/cm with respect to the measured value in the disbonded test under 90 ℃ of copper plating layer, the measured value of the copper foil layer that forms with lamination is 1.5Kgf/cm, has increased significantly.
In addition, semiconductor device according to this example, then as shown in Figure 7, can realize simply a plurality of semiconductor device (semiconductor chip) 71,72,73 semiconductor laminated packaging body (stacked multi-chip packaging body) 70 in the saving space that get up to constitute of lamination longitudinally.As so semiconductor laminated packaging body 70, for example, can enumerate stacked package body, memory and the logical circuit of a plurality of memory chips the stacked package body, use the stacked package body etc. of the assembly of sensor chip.
Secondly, referring to the example 5 of Fig. 8 explanation as the manufacture method of the semiconductor device of the said example 4 in top.In this example, at first, shown in Fig. 8 A, to having element portion or multilayer wiring portion (silicon wire layer) 32 in a surperficial side, being formed with on the semiconductor substrate 31 of electrode pad 33, for example irradiating laser forms through hole 34.The formation position of through hole 34, at any position of semiconductor substrate 31 (semiconductor chip) top all can, can form on the position that be connected with other packaging body or parts being suitable for.In addition, the bore dia of through hole 34 is though limiting value along with the varied in thickness of semiconductor substrate 31, is taken as about about 0.02～0.1mm.
Then, shown in Fig. 8 B, on the two sides of semiconductor substrate 31, be clamped in medially lamination for making its resin face contact from both sides the thin slice (resin sheet of one-side band Copper Foil) that is coated with the insulating resin 41 of Copper Foil 40 at single face, insulating resin 41 is layed onto respectively on the two sides of semiconductor substrate 31, and, insulating resin 41 is filled in the through hole 34.This lamination procedure, same with the manufacturing process of printed circuit board, carry out by means of vacuum hotpressing.In example 4, for example, can use the resin sheet of the about 12 microns one-side band Copper Foil of about 30 microns of resin thickness, copper thickness.
Secondly, shown in Fig. 8 C, in the insulating resin 41 of the inside that is filled into through hole 34, form the resin hole 38 of the diameter minor diameter littler than through hole 34, and, in the insulating resin 41 on the top of the electrode pad 33 of semiconductor substrate 31 tops, form opening 33a.The opening of this insulating resin 41 is handled, and the formation of resin hole 38 and opening 33a can be used laser machine in other words.The diameter in resin hole 38 for example is taken as 70 microns.In addition, in this example, though resin hole 38 become to only at the non-through hole of one-sided (a surperficial side) opening,, also can become and be the Copper Foil 40 of the two sides side of semiconductor substrate 31 through hole of opening all.
Secondly, resin hole 38 in the opening 33a of electrode pad 33 tops in and the conductor of Copper Foil 40 top plating coating coppers etc.Handle by means of this plating, shown in Fig. 8 D, just can in resin hole 38, form the joint pin 37 of electric conductor.In addition, on the table back of the body two sides of semiconductor substrate 31, just can form the conductor layer 42 that wiring forms usefulness by means of the copper plating layer of Copper Foil 40 and lamination formation above that.In this form, though carried out fully in the landfill resin hole 38 and the platings in the opening 33a are handled,, as described later, also can be only on the side wall surface in resin hole 38 and bottom, form the copper plating layer.
Then, shown in Fig. 8 E, form on the predetermined position of using conductor layer 42, form etching resist 43 in the wiring that is formed on the table back of the body two sides of semiconductor substrate 31.Then, shown in Fig. 8 F, be mask with this etching resist 43, connecting up forms the etch processes of using conductor layer 42, forms the wiring layer 36 of predetermined pattern.Then, shown in Fig. 8 G, remove etching resist 43, become and be completion status.In addition, actual manufacturing process will carry out under the state of semiconductor wafer, after becoming to above-mentioned completion status, cuts, and makes the product of finishing of each chip.
As mentioned above, in example 4 and 5, can use the method processing identical substantially to the operation beyond the formation operation of the through hole 34 of semiconductor substrate 31, compared with the prior art, can make semiconductor device with low cost simple ground with the manufacture method of printed circuit board.
The profile of Fig. 9 has illustrated the formation of the semiconductor device of example 6 of the present invention.In Fig. 9, give same label and omit explanation for those parts identical with semiconductor device shown in Figure 6.The semiconductor device of example 6 is by means of the conductor plating layer semiconductor device of the structure of landfill fully not in the on top said resin hole 38 and in the opening 33a.In other words, only in resin hole 38 and on side wall surface in the opening 33a and the bottom, formed the conductor plating layer, and, the electrode on the two sides of semiconductor substrate 31 has been electrically connected by means of the electric conductor 42a of tubulose of formation resin hole 38 in.
The semiconductor device of example 6 can be made via each operation shown in Figure 10.The profile of Figure 10 A～10G has illustrated the manufacturing process as the semiconductor device of example 7.In Figure 10, give same label and omit explanation for the part corresponding with the manufacturing process of semiconductor device shown in Figure 8.In the manufacturing process of this semiconductor device, only the plating treatment process shown in Figure 10 D is different with example 5 shown in Figure 8, the way that employing is controlled the plating condition has only formed conductor plating layer 44 in resin hole 38 and on side wall surface in the opening 33a and the bottom.In the manufacture method of such semiconductor device, compared with the prior art, also can make semiconductor device with low cost simple ground.
The profile of Figure 11 has illustrated the formation of the semiconductor device of example 8 of the present invention.In Figure 11, give same label and omit explanation for those parts identical with semiconductor device shown in Figure 6.In the semiconductor device of example 8, become to handle resin hole 38 in, to form and conduct electricity the structure of body for filled conductive resin 45 in resin hole 38 rather than by means of plating.Then, by means of the packed layer of this electroconductive resin 45, the electrode on the two sides of semiconductor device 31 is electrically connected.
The semiconductor device of example 8 can be made via each operation shown in Figure 12.The profile of Figure 12 A～H has illustrated the manufacturing process as the semiconductor device of example 9.In this example, do not carry out the plating treatment process shown in Fig. 8 D, and replace the electroconductive resin 45 that carries out shown in Figure 12 D filling work procedure in resin hole 38 and the grinding step of the electroconductive resin 45 of surface one side shown in Figure 12 E.As for other each operation, be identical with the operation of example 5 shown in Figure 8.Utilize the manufacture method of such semiconductor device, compared with the prior art, also can make semiconductor device with low cost simple ground.
The profile of Figure 13 has illustrated the formation of the semiconductor device of example 10 of the present invention.Semiconductor device 51 shown in this figure has the semiconductor substrate (silicon substrate etc.) 52 that is formed with the function element portion etc. of arithmetic element portion, memory element portion or sensor element portion and so on by means of common semiconductor technology.In other words, this side of surperficial 52a of semiconductor substrate 52 forms element area, be formed with omitted illustrated integrated component portion, multilayer wiring portion that couples together between each element portion etc.In addition, be formed with the electrode 53 that is connected in the inner multilayer wiring portion on the surperficial 52a of semiconductor substrate 52.
Then, on the peripheral part of such semiconductor substrate 52, form the through hole 54 that for example has the diameter about 20～100 microns.In other words, semiconductor substrate 52 has the through hole 54 that couples together between its surperficial 52a and the back side 52b.Be filled with porous matter insulating resin layer 55 in through hole 54, in addition, porous matter insulating resin layer 55 is formed and makes and continuously the surperficial 52a of semiconductor substrate 52 and back side 52b to be covered in through hole 54.
This porous matter insulating resin layer 55, for example, can adopt after nitrogen that low-boiling point liquid, high pressure are filled or carbon dioxide etc. are distributed in the resin, add the method for thermosetting bubble, heating, thermal decomposition have been distributed to blowing agent in the resin to make it to produce the method that gas forms bubble, perhaps in polymerizable monomer, disperse the organic compound of non-intermiscibility with it etc., make and remove non-intermiscibility organic compound after the polymerizable monomer sclerosis with the method that forms small emptying aperture etc., various well-known porous materialization methods form.
In addition, the formation material of porous matter insulating resin layer 55, not what special qualification can be according to the use various insulative resins (organic insulation substrate) such as method of porous materialization.As an example, can enumerate the porous matter insulating resin layer 55 that adopts the polyamide-imide resin to form.
In addition, porous matter insulating resin layer 55 is that a kind of making can form the porous matter insulating resin layer that conductor layer described later is communicated with the internal state that gets up with having fine emptying aperture 3 dimensions like that on the emptying aperture face of side within it continuously.It is desirable to remove and obtain outside such internal state, the emptying aperture degree (the emptying aperture volume is to the ratio of the apparent volume of insulating resin layer) that also makes porous matter insulating resin layer 55 is 40～90% scope.If the emptying aperture degree of porous matter insulating resin layer 55 is less than 40%, then the connected state of emptying aperture will reduce, exist conductor layer become for discontinuous state may.On the other hand, when the emptying aperture degree had surpassed 90%, intensity of porous matter insulating resin layer 55 self etc. will be impaired, and existing can not the sustaining layer state or the possibility of occupied state.
In the on top said porous matter insulating resin layer 55, form conductor layer 56 selectively.In other words, on the inner surface of the emptying aperture in porous matter insulating resin layer 55 (forming the surface of the resin of emptying aperture), for example adopt the way of using the deposited method that waits of electroless plating to separate out the conductive metal of copper or aluminium etc., form continuous conductor layer 56 selectively.
Here, the electric conductor joint pin 56a of portion, must with inner face (side wall surface) insulation by this through hole 54 that constitutes as the silicon of the constituent material of semiconductor substrate 52 etc.So the electric conductor joint pin 56a of portion it is desirable to, forming selectively on for example more than or equal to 1 micron position from the inner face of through hole 54.In other words, between the inner face of electric conductor joint pin 56a of portion and through hole 54, exist the not porous matter insulating resin layer 55 of filled conductive body, this unfilled porous matter insulating resin layer 55 just will play a part insulating barrier.
The conductor layer joint pin 56a of portion, owing to use optionally plating method described later etc., so can be with degree of depth formation arbitrarily on the position arbitrarily in the porous matter insulating resin layer 55.For this reason, just can be between the inner face of electric conductor joint pin 56a of portion and through hole 54, with thickness (for example, more than or equal to 1 micron) reproducibility arbitrarily the porous matter insulating resin layer 55 that plays a part insulating barrier is existed.Therefore, just can improve the insulating reliability of the electric conductor joint pin 56a of portion.
In addition, conductor layer 56, also have from be present in the through hole 54 the electric conductor joint pin 56a of portion continuously, at the part 56b of the inside of the porous matter insulating resin layer 55 that the surperficial 52a of semiconductor substrate 52 is covered formation.The conductor layer 56b of this surface one side is the part that the electric conductor joint pin 56a of portion in the through hole 54 and electrode 53 are electrically connected, and is that the wiring figure with expection forms accordingly.
The conductor layer 56b of surface one side also with through hole 54 in same, it is desirable to forming on for example more than or equal to 1 micron position from the surperficial 52a of semiconductor substrate 52.Conductor layer 56, as mentioned above owing to can on the depth areas arbitrarily of porous matter insulating resin layer 55, form, so can be between the surperficial 52a of the conductor layer 56b of a surperficial side and semiconductor substrate 52, reproducibility makes porous matter insulating resin layer 55 existence that play a role as insulating barrier well.Therefore, even if, also can improve insulating reliability to the surperficial 52a of semiconductor substrate 52 for the conductor layer 56b of a surperficial side.
As for the conductor layer 56b of a surperficial side and the connecting portion between the electrode 53, adopt with this part and correspondingly deepen the way of conductor layer 56b the formation zone of porous matter insulating resin layer 55, just can be easily and obtain good electrical connection reliably and need not be via complicated step.In addition, in the back side of semiconductor substrate 52 52b one side, be formed with become and other semiconductor device or circuit board etc. between the conductor layer 56c of platform-like of connecting portion.This back side one side conductor layer 56c, desirable also is is forming on for example more than or equal to 1 micron position from the back side of semiconductor substrate 52 52b.In addition, back side 52b one side of semiconductor substrate 52 also can be the state that the electric conductor joint pin 56a of portion in the through hole 54 exists fully unchangeably.
Be formed with the porous matter insulating resin layer 55 of conductor layer 56, though also can be with of the practicality of constant fully state for semiconductor device 51, but, because the part mechanical strength of filled conductive body layer 56 is not low, so it is desirable in the whole emptying aperture of porous matter insulating resin layer 55, fill the 2nd insulating resin and make it sclerosis.2nd insulating resin of landfill in the emptying aperture of porous matter insulating resin layer 55 for example, can adopt to use to be pressed into or the way of the thermosetting resin constituent of vacuum impregnation varnish shape etc. is filled, and the way that makes it to harden by means of heat treatment etc. forms.As mentioned above, adopt the way of the emptying aperture that uses the remnants in the 2nd insulating resin landfill porous matter insulating resin layer 55, just can guarantee the intensity of semiconductor device 51.
As mentioned above, in porous matter insulating resin layer 55, form electrode 53 from surperficial 52a one side of semiconductor substrate 52 selectively via the conductor layer 56 (56a, 56b, 56c) that arrives back side 52b in the through hole 54, this conductor layer 56 plays a part the wiring of the electrode 53 of surperficial 52a one side is connected to wiring layer on the 52b of the back side.In addition, insulation to the inner face (side wall surface) of table back side 52a, the 52b of semiconductor substrate 52 and through hole 54, owing to can keep by means of porous matter insulating resin layer 55, conductor layer 56 is good as the wiring layer reliability in the semiconductor device 51.In addition, can also suppress the reduction of the rate of finished products that the defective insulation etc. by wiring layer causes or reduction of operating characteristic etc. effectively.As described later, these form the semiconductor technology ratio of operations and prior art, also summary and cost degradation significantly.
The conductor layer 56 that couples together between table back side 52a, the 52b of semiconductor substrate 52, for example, when constituting lamination and seal the stacked multi-chip packaging body of a plurality of semiconductor device 51 with getting up, play a part between semiconductor device or the attachment plug that is connected between semiconductor device and the circuit board.As the stacked multi-chip packaging body, can enumerate the multi-chip module that a plurality of memory component laminations are got up, or the system LSI assembly that logic element and memory component lamination are got up etc.
In addition, under the situation of the semiconductor device with sensor function of imaging apparatus and so on, sensor part is being configured under the state of a surperficial side, can utilizing the wiring layer (conductor layer 56) that has been connected to the back side one side to connect, be loaded on the assembling substrate etc.
In addition, example 10 shown in Figure 13 is though show the example that conductor layer 56 is applied to the wiring layer of electrode 53, but, as shown in figure 14, the table back side 52a of semiconductor substrate 52, perforation connector that 52b couples together, also can use conductor layer 56 as only.In other words, semiconductor device 51 shown in Figure 14, same with Figure 13, the inside with the porous matter insulating resin layer 55 in being present in through hole 54 is selectively and the electric conductor joint pin 56a of portion that forms continuously.In addition, in the surperficial 52a of semiconductor substrate 52 side and back side 52b one side, also be formed with respectively with become and other semiconductor device or circuit board etc. between the conductor layer 56d of platform-like of connecting portion.Conductor layer 56 (56a, 56d) plays a part the perforation connector that couples together between other semiconductor device up and down that is configured in semiconductor device 51 or the circuit board etc.
Secondly, referring to Figure 15 the example 11 as the manufacture method of the semiconductor device of the said example 10 in top is described.In example 11, at first, shown in Figure 15 A, have in surperficial 52a one side on the semiconductor substrate 52 of integrated component portion that omission do not draw, multilayer wiring portion, electrode 53, form the through hole 54 that connects between table back side 52a, 52b.The formation of through hole 54 for example can be carried out by means of laser radiation or etching and processing etc.
Then, shown in Figure 15 B, porous matter insulating resin layer 55 formed make it when two sides 52a, 52b cover the table of semiconductor substrate 52 back of the body, to be filled in the through hole 54.Porous matter insulating resin layer 55 for example can followingly form like that.
At first, carry on the back the porous layer formation insulating resin constituent that applies and fill the varnish shape in two sides 52a, 52b and the through hole 54 to the table of semiconductor substrate 52.Coating, filling to such insulating resin constituent, for example, adopt to use the way that the operation (porous materialization operation) of removing the organic compound that is distributed to the non-intermiscibility in the insulating resin constituent etc. waits, when the insulating resin constituent is hardened, make it porous materialization.As the porous matter insulating resin layer 55 that available such operation obtains, for example, can enumerate the polyamide-imide resin bed of porous matter.The emptying aperture degree of porous matter insulating resin layer 55 as mentioned above, it is desirable to the scope 40～90%.
Here, when forming porous matter insulating resin layer 55, need a lot of varnish shape insulating resin constituents when in through hole 54, filling, with the par of table back side 52a, the 52b of semiconductor substrate 52 relatively, amount of resin just becomes to a bit not enough, sometimes can make flatness impaired because of producing pore on this part.In addition, shrink because of the sclerosis that makes varnish shape insulating resin constituent when sclerosis and also produce same phenomenon.As mentioned above, when producing depression on because of the part of the through hole 54 that is being equivalent to porous matter insulating resin layer 55 and making flatness impaired, just exist when being connected, have problems with other semiconductor device or circuit board etc. may.
So, as shown in figure 16, it is desirable to milled processed has produced the porous matter insulating resin layer 55 of depression on the part that is equivalent to through hole 54 surface, make it planarization.In Figure 16, S represents abradant surface.Perhaps, as shown in figure 17, it is desirable to adopt the coating of repeatedly carrying out varnish shape insulating resin constituent repeatedly, the way of cure process, make 55 planarizations of porous matter insulating resin layer.In Figure 17, label 55a represents that the porous matter insulating resin layer that forms with the 1st time processing, 55b represent the porous matter insulating resin layer with the 2nd time processing formation.The flatness of porous matter insulating resin layer 55 it is desirable to, and the degree of depth of the depression of the part that is equivalent to through hole 54 is set at relatively flat portion smaller or equal to 2 microns.
Secondly, after with emulsion porous matter insulating resin layer 55 having been carried out handling, shown in Figure 15 C, make 55 exposures of porous matter insulating resin layer according to the state of the conductor layer 56 that should form.In addition, arrow represent the to expose light of usefulness among the figure.By the processing that emulsion is carried out, for example, adopt the way enforcement that in the solution that the semiconductor substrate 52 with porous matter insulating resin layer 55 is impregnated into emulsion, makes it dry afterwards.By means of such processing, just can comprise that the emptying aperture surface of the inside of porous matter insulating resin layer 55 applies emulsion to integral body.In addition, emulsion is owing to applying extremely thinly on the inner surface of emptying aperture, so can keep porous matter state.
The exposure-processed of porous matter insulating resin layer 55 for example, for the part of through hole 54, connects between table back side 52a, the 52b for making the thickness direction overall exposing.At this moment, be controlled to be and make exposed portion leave predetermined distance (for example, more than or equal to 1 micron) just carrying out exposed areas from the inner face (side wall surface) of through hole 54.In addition, for the wiring pattern portion of surperficial 52a one side of semiconductor substrate 52 and the platform part of back side 52b one side, then to be treated to and make the predetermined degree of depth of to expose to porous matter insulating resin layer 55.In other words, be treated to feasible can the exposure to the position of leaving predetermined distance (for example, more than or equal to 1 micron) from each face 52a, 52b just.The connecting portion of comparative electrode 53 also is same, be treated to make exposed portion arrive electrode 53.The degree of depth of exposing can be controlled by means of exposure (exposure of light).
Such exposure-processed, can adopt with each zone (attachment plug, wiring pattern portion, connect connecting portion toward electrode, platform part etc.) accordingly, use the way of mask of the transit dose of control light to handle together each zone of porous matter insulating resin layer 55.For example, adopt part light all to see through, and, make and carried out porous matter insulating resin layer 55 exposures that sensitization is handled at the wiring pattern portion of table back side 52a, 52b, the platform part such mask of light-semipermeable then at through hole 54.Then, make plating separate out like that and in the exposure portion of porous matter insulating resin layer 55, carry out activation processing.The activation of porous matter insulating resin layer 55 can be carried out selectively for exposed portion.
Then, semiconductor substrate 52, for example be impregnated in the electroless plating copper liquid with porous matter insulating resin layer 55 of having implemented sensitization processing, exposure-processed, activation processing successively.In this plating treatment process, the coating metal of copper etc., owing to only on the part that the exposure and the activation processing of porous matter insulating resin layer 55 are crossed, separate out, so the part of through hole 54 for example, form copper plate etc. conductor layer (the electric conductor joint pin 56a of portion) and coupling together between table back side 52a, 52b.In addition, surperficial 52a one side of semiconductor substrate 52 and back side 52b one side can form conductor layer 56b, the 56c of copper plate etc. according to wiring figure, platform part shape respectively.
So, just can be formed on the inner face of through hole 54 and between the table back side of semiconductor substrate 52 52a, 52b, insert and put the insulating barrier (the not porous matter insulating resin layer 55 of filled conductive body) that exists preset thickness, and the conductor layer 56 that couples together between table back side 52a, the 52b of semiconductor substrate 52 etc.After the formation of conductor layer 56, as required, carry out the operation of in the emptying aperture of the remnants of porous matter insulating resin layer 55, filling the 2nd insulating resin and making it to harden.The 2nd insulating resin is to the filling work procedure of porous matter insulating resin layer 55, as mentioned above, can adopt to use to be pressed into or the way of vacuum impregnation etc. is implemented.
Manufacture method according to such semiconductor device as example 11, owing to can in porous matter insulating resin layer 55, form conductor layer 56 selectively, so except keeping well the insulation to table back side 52a, the 52b of the inner face of through hole 54 and semiconductor substrate 52 by means of porous matter insulating resin layer 55, can also comprise through hole 54 inherent in precision well conductor layer 56 is formed the figure of expection.In addition, the formation operation of conductor layer 56 and insulating barrier (not filling the porous matter insulating resin layer 55 of conductor) is owing to the easy operation of the coating that can use insulating resin or plating etc. is implemented, so can form conductor layer 56 and insulating barrier with low cost.These all can help to have the reduction of the manufacturing cost of the semiconductor device 51 of the conductor layer 56 that couples together between table back side 52a, the 52b of semiconductor substrate 52 and the raising of reliability.
Secondly, referring to Figure 18 the stacked multi-chip packaging body that uses semiconductor device of the present invention is described.The semiconductor device of this example (semiconductor package body) 60 has circuit board 61 as mounting substrate.Circuit board 61 can use the various substrates of resin substrate or ceramic substrate etc.Can use common multilayered printed wiring board etc. as resin substrate,, be formed with the external connection terminals 62 of metal bumps etc. in lower surface one side of circuit board 61.On the other hand, upper surface one side at circuit board 61 then is provided with the electrode part 63 that internal layer connects up and external connection terminals 62 is electrically connected of not drawing by omitting.
On the element loading surface (upper surface) of circuit board 62, be mounted with the semiconductor device 51 of the said example 8 in a plurality of tops overlappingly.In addition, be the semiconductor package body 60 that 2 semiconductor device 51 is loaded into circuit board 61 tops though Figure 18 illustrates,, the loading number of semiconductor device 51 is not limited to 2, also can be more than 3 or 3.
The semiconductor device 51 of downside is affixed to by the metal bumps on the part that is formed at conductor layer 56 64 on the electrode part 63 of circuit board 61.Equally, the semiconductor device 51 of upside is affixed to by the metal bumps on the part that is formed at conductor layer 56 64 on the conductor layer 56 of semiconductor device 51 of downside.Adopt to use sealing resin sealings such as (the drawing) way of a plurality of semiconductor device 51 of getting up of lamination like this, just can constitute the semiconductor package body 60 of stacked multi-chip package body structure.
According to such semiconductor package body 60, because being connected between 51 of semiconductor device and semiconductor device 51 and circuit board 61 can be used the connection of back-off chip, so connect the needed cost of operation and man-hour, can also realize the shortening of signal routing length and the miniaturization of packaging body shape etc. except reducing.These all help the cost degradation of stacked multi-chip packaging body and the raising of reliability and operating characteristic etc.As the concrete example of semiconductor package body 60, as mentioned above, can enumerate multi-chip module that a plurality of memory component laminations are got up or system LSI assembly that logic element and memory component lamination are got up etc.
In addition, the present invention can use in the various semiconductor device with the conductor layer that connects between the table back of the body two sides that connects semiconductor substrate, and be not limited to the said example in top, be also included within the present invention for above-mentioned such semiconductor device.In addition, example of the present invention can expand in the scope of technological thought of the present invention or change, and this expansion, example after changing are also included within the technical scope of the present invention.
Claims (18)
1. semiconductor device, it possesses:
Semiconductor substrate with the through hole at the perforation table back side;
Formed the 1st insulating resin layer on the inner face of above-mentioned through hole;
Formed the 2nd insulating resin layer on the surface of above-mentioned semiconductor substrate and at least one side's in the back side face; And
In above-mentioned through hole, at least the mode that couples together between the table of above-mentioned semiconductor substrate back of the body two sides being formed continuously, and, the 1st conductor layer that insulate by means of the inner face of above-mentioned the 1st insulating resin layer and above-mentioned through hole.
2. semiconductor device according to claim 1, it possesses: form the 2nd conductor layer that is electrically connected with above-mentioned the 1st conductor layer on the predetermined zone on above-mentioned the 2nd insulating resin layer.
3. semiconductor device according to claim 2, above-mentioned the 2nd conductor layer have the Copper Foil that has carried out wiring processing.
4. semiconductor device according to claim 3 also has the conductor plating layer in above-mentioned top of having carried out the Copper Foil of wiring processing.
5. semiconductor device according to claim 3 is formed with copper plate on the above-mentioned lamination ground, positive top that has carried out the Copper Foil of wiring processing.
6. semiconductor device according to claim 1 and 2,
On the inner face of the above-mentioned through hole of above-mentioned semiconductor substrate, be formed with the basis material zone of impalpable structure, and be formed with above-mentioned the 1st insulating resin layer thereon.
7. semiconductor device according to claim 1,
Above-mentioned the 1st insulating resin layer and above-mentioned the 2nd insulating resin layer are porous matter insulating resin layer, and above-mentioned the 1st conductor layer forms in above-mentioned porous matter insulating resin layer continuously.
8. semiconductor device according to claim 7,
Above-mentioned semiconductor substrate has formed electrode on the above-mentioned surface of element area one side, and above-mentioned electrode is connected with above-mentioned the 1st conductor layer.
9. semiconductor device according to claim 7 is filled with the 3rd insulating resin in the emptying aperture of above-mentioned porous matter insulating resin layer.
10. the manufacture method of a semiconductor device, it comprises:
Form the operation of through hole to irradiating laser on the integrated semiconductor substrate that is formed with element on the surperficial side;
In above-mentioned through hole, fill the operation of insulating resin;
In the insulating resin of filling, form the operation in the diameter resin hole littler with one heart than above-mentioned through hole with above-mentioned operation; And
Form conductor layer at the inner face in above-mentioned resin hole, form the operation of the through hole conducting portion of the surface that makes above-mentioned semiconductor substrate and back side conducting.
11. the manufacture method of semiconductor device according to claim 10 forms the resin hole to above-mentioned insulating resin irradiating laser.
12. the manufacture method of semiconductor device according to claim 10 forms above-mentioned conductor layer with the plating method on the inner face in above-mentioned resin hole.
13. the manufacture method of semiconductor device according to claim 10 has on the surface of above-mentioned semiconductor substrate and at least one side's in the back side face, forms the operation of the wiring of expection.
14. the manufacture method of a semiconductor device, it comprises:
On semiconductor substrate, form the operation of through hole;
On the two sides of above-mentioned semiconductor substrate, respectively the resin sheet of one-side band Copper Foil is carried out with disposing the operation of lamination in the mode that contacts with the resin face;
On the part of the above-mentioned through hole of above-mentioned semiconductor substrate, form the operation of the diameter small diameter bore littler than this through hole;
Inside in above-mentioned small diameter bore forms conductor layer, is electrically connected the operation of the above-mentioned Copper Foil on the two sides that is configured in above-mentioned semiconductor substrate; And
To above-mentioned Copper Foil connect up processing operation.
15. the manufacture method of semiconductor device according to claim 14, above-mentioned small diameter bore are non-through hole.
16. according to the manufacture method of claim 14 or 15 described semiconductor device, with the inside of the above-mentioned small diameter bore of above-mentioned conductor layer landfill.
17. the manufacture method of a semiconductor device, it comprises:
On semiconductor substrate, form the operation of through hole;
To comprise the mode that in the above-mentioned through hole inherence table of above-mentioned semiconductor substrate back of the body two sides is covered, form the operation of porous matter insulating resin layer;
In above-mentioned porous matter insulating resin layer, in the state that keeps with the insulation of the inner face of the table back of the body two sides of above-mentioned semiconductor substrate and above-mentioned through hole, be formed continuously to few the operation of the conductor layer that couples together between the table of above-mentioned semiconductor substrate back of the body two sides.
18. the manufacture method of semiconductor device according to claim 17 also possesses the operation of filling the 2nd insulating resin and making it to harden in the emptying aperture of above-mentioned porous matter insulating resin layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP264729/2004 | 2004-09-10 | ||
| JP2004264729 | 2004-09-10 | ||
| JP264731/2004 | 2004-09-10 | ||
| JP264732/2004 | 2004-09-10 |
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| CN1758430A true CN1758430A (en) | 2006-04-12 |
| CN100481402C CN100481402C (en) | 2009-04-22 |
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| US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
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Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003289073A (en) * | 2002-01-22 | 2003-10-10 | Canon Inc | Semiconductor device and method of manufacturing semiconductor device |
-
2005
- 2005-09-08 CN CN200510102531.2A patent/CN100481402C/en not_active Expired - Fee Related
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| US8653644B2 (en) | 2006-11-22 | 2014-02-18 | Tessera, Inc. | Packaged semiconductor chips with array |
| US8704347B2 (en) | 2006-11-22 | 2014-04-22 | Tessera, Inc. | Packaged semiconductor chips |
| US8735287B2 (en) | 2007-07-31 | 2014-05-27 | Invensas Corp. | Semiconductor packaging process using through silicon vias |
| US7863747B2 (en) | 2007-12-21 | 2011-01-04 | Dongbu Hitek Co., Ltd. | Semiconductor chip, method of fabricating the same and semiconductor chip stack package |
| US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
| CN102347271B (en) * | 2010-07-23 | 2014-05-07 | 泰塞拉公司 | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| CN102347271A (en) * | 2010-07-23 | 2012-02-08 | 泰塞拉公司 | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US9355948B2 (en) | 2010-09-17 | 2016-05-31 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US9847277B2 (en) | 2010-09-17 | 2017-12-19 | Tessera, Inc. | Staged via formation from both sides of chip |
| US8809190B2 (en) | 2010-09-17 | 2014-08-19 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
| US9362203B2 (en) | 2010-09-17 | 2016-06-07 | Tessera, Inc. | Staged via formation from both sides of chip |
| US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
| US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| US9224649B2 (en) | 2010-12-08 | 2015-12-29 | Tessera, Inc. | Compliant interconnects in wafers |
| US8796828B2 (en) | 2010-12-08 | 2014-08-05 | Tessera, Inc. | Compliant interconnects in wafers |
| CN102903645B (en) * | 2011-07-27 | 2015-04-22 | 佳邦科技股份有限公司 | Planar semiconductor element and manufacturing method thereof |
| CN102903645A (en) * | 2011-07-27 | 2013-01-30 | 佳邦科技股份有限公司 | Planar semiconductor element and manufacturing method thereof |
| CN110476228A (en) * | 2017-04-04 | 2019-11-19 | 索尼半导体解决方案公司 | Semiconductor device, the method and electronic equipment for manufacturing semiconductor device |
| CN110476228B (en) * | 2017-04-04 | 2024-01-16 | 索尼半导体解决方案公司 | Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus |
| CN110767604A (en) * | 2019-10-31 | 2020-02-07 | 厦门市三安集成电路有限公司 | Compound semiconductor device and back copper processing method of compound semiconductor device |
| CN110767604B (en) * | 2019-10-31 | 2022-03-18 | 厦门市三安集成电路有限公司 | Compound semiconductor device and back copper processing method of compound semiconductor device |
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