CN213936169U - Secondary plastic package packaging structure - Google Patents
Secondary plastic package packaging structure Download PDFInfo
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- CN213936169U CN213936169U CN202023249037.8U CN202023249037U CN213936169U CN 213936169 U CN213936169 U CN 213936169U CN 202023249037 U CN202023249037 U CN 202023249037U CN 213936169 U CN213936169 U CN 213936169U
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Abstract
The utility model discloses a secondary plastic envelope packaging structure, include: an adapter plate; the conductive through silicon hole penetrates through the adapter plate; at least one first chip attached to the front side of the interposer, the first chip being electrically connected to the conductive via; the first plastic package layer is arranged on the front surface of the adapter plate, the at least one first chip is wrapped around the first plastic package layer on four surfaces, and the back surface of the at least one first chip leaks out of the first plastic package layer; the second plastic package layer is arranged on the front surface of the adapter plate, the first plastic package layer is wrapped around the four surfaces of the second plastic package layer, and internal stress generated by the second plastic package layer at least partially offsets the internal stress generated by the first plastic package layer; the metal wiring layer is arranged on the back surface of the adapter plate and is electrically connected to the conductive through hole.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a secondary plastic envelope packaging structure.
Background
With the demand for light weight and miniaturization of electronic products, IC chip packages tend to be thin and miniaturized. The three-dimensional system integrated package utilizing the adapter plate can better meet the requirement.
However, when the conventional wafer-level interposer is stacked and packaged three-dimensionally, the interposer with the conductive through-silicon-vias is subjected to integral plastic packaging after chips are mounted thereon. At this time, local thermal stress is more easily generated due to mismatch of Coefficient of Thermal Expansion (CTE) among the conventional plastic package IC chip, the interposer and the plastic package material, so that surface warpage of the package is generated. The excessive warping not only increases the difficulty of subsequent processes (such as rib cutting, forming and the like) after plastic packaging, but also obviously increases the process reject ratio when the finished product of the plastic packaged IC chip is assembled by SMT, and is easy to generate serious device failure problems such as chip and packaging cracks and the like.
To the wafer warpage problem that current three-dimensional pile up the encapsulation and exist based on wafer level keysets, the utility model provides a secondary plastic envelope packaging structure and manufacturing method thereof, the problem that the above-mentioned prior art of improvement that can show exists.
SUMMERY OF THE UTILITY MODEL
To the wafer warpage problem that current three-dimensional pile up the encapsulation and exist based on wafer level keysets, according to the utility model discloses an embodiment provides a secondary plastic envelope packaging structure, include:
an adapter plate;
the conductive through silicon hole penetrates through the adapter plate;
at least one first chip attached to the front side of the interposer, the first chip being electrically connected to the conductive via;
the first plastic package layer is arranged on the front surface of the adapter plate, the at least one first chip is wrapped around the first plastic package layer on four surfaces, and the back surface of the at least one first chip leaks out of the first plastic package layer;
the second plastic package layer is arranged on the front surface of the adapter plate, the first plastic package layer is wrapped around the four surfaces of the second plastic package layer, and internal stress generated by the second plastic package layer at least partially offsets the internal stress generated by the first plastic package layer;
the metal wiring layer is arranged on the back surface of the adapter plate and is electrically connected to the conductive through hole.
In one embodiment of the present invention, the metal wiring layer includes one or more line layers, and a dielectric layer disposed between the line layers, and has a pad region on an outer surface of the metal wiring layer.
In an embodiment of the present invention, the interposer front surface is further provided with a re-layout wiring layer electrically connected to the conductive via, and the at least one first chip is flip-chip bonded to a corresponding chip pad on the re-layout wiring layer.
In one embodiment of the present invention, the re-layout wiring layer includes one or more circuit layers and a dielectric layer disposed between the circuit layers, and the chip pad is disposed on the outer surface of the re-layout wiring layer.
In an embodiment of the present invention, the first plastic-sealed layer is opposite to the interposer and has a tensile stress, and the second plastic-sealed layer is opposite to the interposer and has a compressive stress.
In an embodiment of the present invention, the first plastic-sealed layer is opposite to the adapter plate and has a compressive stress, and the second plastic-sealed layer is opposite to the adapter plate and has a tensile stress.
The utility model discloses an in the embodiment, secondary plastic envelope packaging structure still includes: and the external solder balls are electrically connected to the metal wiring layer.
In an embodiment of the present invention, the external solder ball is a copper pillar or a lead-free solder ball.
In an embodiment of the present invention, the first plastic package layer and the second plastic package layer are formed by two times of plastic package.
In an embodiment of the present invention, the second plastic package layer balances warpage caused by mismatching of the first plastic package layer and the interposer.
The utility model provides a secondary plastic package packaging structure and a manufacturing method thereof, wherein, after chip surface mounting is completed on a wafer-level adapter plate, primary plastic package is carried out, after plastic package, plastic package layer thinning and plastic package area cutting are carried out, a whole plastic package layer is divided into plastic package units, and wafer warping after primary plastic package is reduced; and then carrying out secondary plastic packaging on the wafer on the basis of the primary plastic packaging, filling the surface of the primary plastic packaging and the cutting channel with a plastic packaging material, wrapping the whole wafer by a secondary plastic packaging layer, and finally reducing the warpage of the wafer after the plastic packaging by thinning the second plastic packaging layer, thereby facilitating the subsequent bonding and back process. Furthermore, the utility model discloses one of technical scheme's main points is through selecting suitable first and second plastic packaging material, makes second time plastic packaging material and first time plastic packaging material have different plastic packaging internal stress for wafer level keysets to can be at least partial balanced whole plastic packaging reconfiguration structure's internal stress, thereby show the warpage problem that reduces the wafer behind the plastic packaging. Based on this kind of secondary plastic envelope packaging structure and manufacturing approach of the utility model, adopt the mode of twice plastic envelope, the first plastic envelope realizes packing the parcel to the chip, but the plastic envelope region is less, mainly cladding chip paster region can, reduce the wafer warpage after the plastic envelope through reducing the plastic envelope area, get rid of the chip back plastic envelope through the plastic envelope attenuate, make the wafer warpage control in certain extent; the second plastic package selects a proper plastic package material, so that warping caused by mismatching of the first plastic package material is balanced, the whole wafer is wrapped in the plastic package area, the edge of the wafer is protected, and the wafer is prevented from being damaged by a subsequent process; through the balance of the two times of plastic packaging, the wafer is less warped after the plastic packaging and thinning, and the subsequent bonding process and the back process are utilized.
Drawings
To further clarify the above and other advantages and features of various embodiments of the present invention, a more particular description of various embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a schematic cross-sectional view of a secondary plastic package structure 100 according to an embodiment of the present invention.
Fig. 2A to 2K are schematic cross-sectional views illustrating a process of forming such a secondary plastic package structure 100 according to an embodiment of the present invention.
Fig. 3 illustrates a flow chart 300 for forming such a secondary plastic package structure 100 according to an embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, the embodiments of the present invention describe the process steps in a specific order, however, this is only for the convenience of distinguishing the steps, and not for limiting the sequence of the steps.
The utility model provides a secondary plastic package packaging structure and a manufacturing method thereof, wherein, after chip surface mounting is completed on a wafer-level adapter plate, primary plastic package is carried out, after plastic package, plastic package layer thinning and plastic package area cutting are carried out, a whole plastic package layer is divided into plastic package units, and wafer warping after primary plastic package is reduced; and then carrying out secondary plastic packaging on the wafer on the basis of the primary plastic packaging, filling the surface of the primary plastic packaging and the cutting channel with a plastic packaging material, wrapping the whole wafer by a secondary plastic packaging layer, and finally reducing the warpage of the wafer after the plastic packaging by thinning the second plastic packaging layer, thereby facilitating the subsequent bonding and back process. Furthermore, the utility model discloses one of technical scheme's main points is through selecting suitable first and second plastic packaging material, makes second time plastic packaging material and first time plastic packaging material have different plastic packaging internal stress for wafer level keysets to can be at least partial balanced whole plastic packaging reconfiguration structure's internal stress, thereby show the warpage problem that reduces the wafer behind the plastic packaging. Based on this kind of secondary plastic envelope packaging structure and manufacturing approach of the utility model, adopt the mode of twice plastic envelope, the first plastic envelope realizes packing the parcel to the chip, but the plastic envelope region is less, mainly cladding chip paster region can, reduce the wafer warpage after the plastic envelope through reducing the plastic envelope area, get rid of the chip back plastic envelope through the plastic envelope attenuate, make the wafer warpage control in certain extent; the second plastic package selects a proper plastic package material, so that warping caused by mismatching of the first plastic package material is balanced, the whole wafer is wrapped in the plastic package area, the edge of the wafer is protected, and the wafer is prevented from being damaged by a subsequent process; through the balance of the two times of plastic packaging, the wafer is less warped after the plastic packaging and thinning, and the subsequent bonding process and the back process are utilized.
A secondary plastic package structure according to an embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 shows a schematic cross-sectional view of a secondary plastic package structure 100 according to an embodiment of the present invention. As shown in fig. 1, the secondary plastic package structure 100 further includes an interposer 110, a conductive through-silicon via 120, a first chip 130, a second chip 140, a first plastic package layer 150, a second plastic package layer 160, a metal wiring layer 170, and external solder balls 180.
The interposer 110 is a supporting structure of the secondary plastic package structure 100, and is typically a silicon interposer. In one embodiment of the present invention, the interposer 110 is a wafer level silicon interposer with a thickness of about 50 microns to 150 microns. In another embodiment of the present invention, the interposer 110 may also be a PCB substrate or a glass substrate.
The conductive through-silicon-via 120 penetrates the interposer 110. In an embodiment of the present invention, the conductive through-silicon via 120 is formed by TSV through-silicon via, conductive metal filling, and backside exposure, and further, the conductive metal may be copper.
The first chip 130 is flip-chip bonded to the front surface of the interposer 110. In an embodiment of the present invention, the first chip 130 may be a logic chip such as a processor, an FPGA, and an MCU, a memory chip such as an EPROM, a FLASH, and a DRAM, or a radio frequency chip, a MEMS sensor, or other discrete devices. In another embodiment of the present invention, the first chip 130 is flip-chip bonded on the front surface of the interposer 110 through a bonding structure 131 such as a BGA solder ball or a conductive copper pillar disposed on the front surface of the first chip 130, and electrically connected to the conductive through-silicon via 120, and an underfill 132 is further disposed between the first chip 130 and the interposer for insulation and mechanical protection. In another embodiment of the present invention, the front surface of the interposer 110 may further be provided with one or more metal wiring layers, and a chip pad (not shown in the figure) is disposed on the upper metal wiring layer, and the first chip 130 is flip-chip bonded on the corresponding chip pad.
The second chip 140 is flip-chip bonded to the front surface of the interposer 110, similar to the first chip. The utility model discloses an embodiment, second chip 140 can be logic chips such as treater, FPGA, MCU, also can be storage chip such as EPROM, FLASH, DRAM, still can be radio frequency chip, MEMS sensor or other discrete device, and second chip 140 can be the same kind of chip with first chip, also can be different kinds of chips. In another embodiment of the present invention, the second chip 140 is flip-chip bonded to the corresponding position on the front surface of the interposer 110 through a bonding structure 141 such as a BGA solder ball or a conductive copper pillar disposed on the front surface of the second chip 140, and electrically connected to the conductive through-silicon-via 120, and an underfill 142 is further disposed between the second chip 140 and the interposer for insulation and mechanical protection. In another embodiment of the present invention, the front surface of the interposer 110 may further be provided with one or more metal wiring layers, and a chip pad (not shown in the figure) is disposed on the upper metal wiring layer, and the second chip 140 is flip-chip bonded on the corresponding chip pad.
The first molding compound layer 150 is disposed on the front surface of the interposer 110 and surrounds the first chip 130 and the second chip 140. In an embodiment of the present invention, the first molding compound layer 150 is only disposed near the chip mounting region of the first chip 130 and the second chip 140, and the back surfaces of the first chip 130 and the second chip 140 are leaked from the first molding compound layer 150.
The second plastic package layer 160 is disposed on the front surface of the interposer 110 and entirely surrounds and wraps the first plastic package layer 150, wherein the plastic package material of the second plastic package layer 160 and the plastic package material of the first plastic package layer 150 have different plastic package internal stresses relative to the interposer 110 and/or the chip, so that the internal stresses of the whole plastic package reconfiguration package structure can be at least partially balanced, and the warpage of the wafer after plastic package is reduced. In an embodiment of the present invention, the plastic package material of the first plastic package layer 150 has a tensile stress relative to the interposer 110, and the plastic package material of the second plastic package layer 160 has a compressive stress relative to the interposer 110, so as to balance the stress.
A metal wiring layer 170 is disposed on the back surface of the interposer 110 and electrically connected to the conductive through-silicon-vias 120. In an embodiment of the present invention, the number of metal layers of the metal wiring layer 170 may be a single layer or multiple layers, wherein an external pad is further disposed on the outermost layer, and a dielectric layer 171 is further disposed between the metal wiring layers on the same layer and between the adjacent metal layers.
The external solder balls 180 are electrically connected to the metal wiring layer 170, and serve as electrical and/or signal connections for the package structure to an external system.
The process of forming the secondary plastic package structure 100 is described in detail below with reference to fig. 2A to 2K and fig. 3. Fig. 2A to 2K are schematic cross-sectional views illustrating a process of forming such a secondary plastic package structure 100 according to an embodiment of the present invention; fig. 3 illustrates a flow chart 300 for forming such a secondary plastic package structure 100 according to an embodiment of the present invention.
First, in step 301, as shown in fig. 2A, a wafer 210 with non-exposed conductive through silicon vias 220 is provided. Wherein, the wafer 210 may be a 200mm or 300mm silicon wafer, and the thickness is about 150um to 1000 um; the conductive through silicon vias 220 are blind vias that do not penetrate the wafer 210, and the filling metal is mainly copper, and the depth/height thereof is about 50um to 150 um. In an embodiment of the present invention, the sidewall of the conductive through silicon via 220 contacting the wafer 210 may further have a barrier metal layer or the like to prevent copper contamination of the wafer 210, wherein the barrier metal layer may be titanium nitride, titanium, chromium, or the like.
Next, in step 302, as shown in fig. 2B, the first chip 230 and the second chip 240 are mounted on the front surface of the wafer 210. In an embodiment of the present invention, the first chip 230 and/or the second chip 240 are flip-chip bonded on the front surface of the wafer 210 through the first chip bonding structure 231 and/or the second chip bonding structure 241 disposed on the first chip 230 and/or the second chip 240, and the first chip bonding structure 231 and/or the second chip bonding structure 241 are electrically connected to the conductive through silicon via 220. In another embodiment of the present invention, a first underfill 232 and/or a second underfill 242 are further disposed between the first chip 230 and/or the second chip 240 and the wafer 210. In another embodiment of the present invention, the front surface of the wafer 210 is further provided with a metal wiring layer (not shown in the figure), and the first chip 230 and the second chip 240 are flip-chip bonded on the corresponding chip pads of the metal wiring layer.
Then, in step 303, as shown in fig. 2C, a first molding compound layer 250 covering the first chip 230 and the second chip 240 is formed on the front surface of the wafer 210. The material of the first molding compound layer 250 may be conventional molding compound such as resin, or specially modified, so that the molding compound has a specific stress with respect to the wafer 210.
Next, in step 304, as shown in fig. 2D, the first molding compound layer 250 is thinned, the back surfaces of the first chip 230 and the second chip 240 are exposed, and the thinned first molding compound layer 250 is divided to form a plurality of first molding compound layer units. In an embodiment of the present invention, the division can be performed by etching, photolithography etching, mechanical grooving, or the like.
Then, in step 305, as shown in fig. 2E, a second molding compound layer 260 covering the first molding compound layer 250 and the back surfaces of the first chip 230 and the second chip 240 is formed on the front surface of the wafer 210. The plastic package material of the second plastic package layer 260 and the plastic package material of the first plastic package layer 250 have different internal stresses relative to the wafer 210, so that the internal stress of the whole plastic package reconfiguration packaging structure can be at least partially balanced, and the warping of the wafer after plastic package is reduced. In an embodiment of the present invention, the plastic package material of the first plastic package layer 250 has a tensile stress after plastic package, and the plastic package material of the second plastic package layer 260 has a compressive stress after plastic package, so as to balance stress.
Next, in step 306, as shown in fig. 2F, thinning the second molding compound 260 leaks out of the first molding compound 250 and the back surfaces of the first chip 230 and the second chip 240. In one embodiment of the invention, the corresponding thinning may be performed by mechanical grinding in combination with a Chemical Mechanical Polishing (CMP) process.
Then, in step 307, as shown in fig. 2G, a carrier plate 270 is temporarily bonded to the second molding layer 260 and the back surfaces of the first chip 230 and the second chip 240. In an embodiment of the present invention, the carrier plate 270 is a transparent carrier plate, and the carrier plate 270 is adhered to the back of the second molding layer 260 and the first and second chips 230 and 240 by a laser detachable bonding material.
Next, in step 308, as shown in fig. 2H, the back surface of the wafer 210 is thinned, so as to expose the back surface of the conductive through silicon via 220. In one embodiment of the present invention, the back side thinning of the wafer 210 is achieved by a mechanical thinning combined with a Chemical Mechanical Polishing (CMP) process.
Then, in step 309, as shown in fig. 2I, a metal wiring layer 280 and external solder balls 290 are formed on the back side of the thinned wafer 210. In an embodiment of the present invention, a single-layer or multi-layer metal wiring layer 280 is formed by patterned electroplating, a dielectric layer 285 is further formed between metal wires on the same layer and between adjacent metal wires to perform the functions of insulation and mechanical support, an external bonding pad (not shown in the figure) is further provided in the outermost metal wiring layer 280, and an external bonding ball 290 is formed on the external bonding pad. In another embodiment of the present invention, the external solder ball 290 may be a lead-free solder ball formed by electroplating, reflow soldering process or ball-mounting process, or may be a conductive copper pillar formed by electroplating process.
Next, at step 310, the temporary bond carrier 270 is removed, as shown in fig. 2J. In a specific embodiment of the present invention, the carrier plate 270 is a transparent carrier plate, the bonding adhesive can be detached by laser and temporarily bonded on the back of the plastic package layer and the chip, the carrier plate 270 is peeled off by laser irradiation, and then the bonding adhesive is removed by a cleaning process.
Finally, in step 311, as shown in fig. 2K, the secondary plastic package structure is obtained by dividing.
Based on the utility model provides a this kind of secondary plastic envelope packaging structure and preparation method thereof, at first after accomplishing the chip paster on wafer level keysets, carry out primary plastic envelope, carry out the plastic envelope layer attenuate and the cutting of plastic envelope region after the plastic envelope, cut apart into the plastic envelope unit with whole plastic envelope layer, reduce the wafer warpage after primary plastic envelope; and then carrying out secondary plastic packaging on the wafer on the basis of the primary plastic packaging, filling the surface of the primary plastic packaging and the cutting channel with a plastic packaging material, wrapping the whole wafer by a secondary plastic packaging layer, and finally reducing the warpage of the wafer after the plastic packaging by thinning the second plastic packaging layer, thereby facilitating the subsequent bonding and back process. Furthermore, the utility model discloses one of technical scheme's main points is through selecting suitable first and second plastic packaging material, makes second time plastic packaging material and first time plastic packaging material have different plastic packaging internal stress for wafer level keysets to can be at least partial balanced whole plastic packaging reconfiguration structure's internal stress, thereby show the warpage problem that reduces the wafer behind the plastic packaging. Based on this kind of secondary plastic envelope packaging structure and manufacturing approach of the utility model, adopt the mode of twice plastic envelope, the first plastic envelope realizes packing the parcel to the chip, but the plastic envelope region is less, mainly cladding chip paster region can, reduce the wafer warpage after the plastic envelope through reducing the plastic envelope area, get rid of the chip back plastic envelope through the plastic envelope attenuate, make the wafer warpage control in certain extent; the second plastic package selects a proper plastic package material, so that warping caused by mismatching of the first plastic package material is balanced, the whole wafer is wrapped in the plastic package area, the edge of the wafer is protected, and the wafer is prevented from being damaged by a subsequent process; through the balance of the two times of plastic packaging, the wafer is less warped after the plastic packaging and thinning, and the subsequent bonding process and the back process are utilized.
Claims (10)
1. The utility model provides a secondary plastic envelope packaging structure which characterized in that includes:
an adapter plate;
the conductive through hole penetrates through the adapter plate;
at least one first chip attached to the front side of the interposer, the first chip being electrically connected to the conductive via;
the first plastic package layer is arranged on the front surface of the adapter plate, the at least one first chip is wrapped around the first plastic package layer on four surfaces, and the back surface of the at least one first chip leaks out of the first plastic package layer;
the second plastic package layer is arranged on the front surface of the adapter plate, the first plastic package layer is wrapped around the four surfaces of the second plastic package layer, and internal stress generated by the second plastic package layer at least partially offsets the internal stress generated by the first plastic package layer;
the metal wiring layer is arranged on the back surface of the adapter plate and is electrically connected to the conductive through hole.
2. The secondary plastic package structure of claim 1, wherein the metal wiring layer comprises one or more wiring layers and a dielectric layer disposed between the wiring layers, and has a pad region on an outer surface of the metal wiring layer.
3. The secondary plastic package structure of claim 1, wherein a redistribution routing layer is further disposed on the front side of the interposer, the redistribution routing layer is electrically connected to the conductive vias, and the at least one first chip is flip-chip bonded to corresponding chip pads on the redistribution routing layer.
4. The secondary plastic package assembly of claim 3, wherein the redistribution routing layer comprises one or more circuit layers and a dielectric layer disposed between the circuit layers, the die pad being disposed on an outer surface of the redistribution routing layer.
5. The secondary plastic package assembly of claim 1, wherein the first plastic package layer has a tensile stress with respect to the interposer, and the second plastic package layer has a compressive stress with respect to the interposer.
6. The secondary plastic package assembly of claim 1, wherein the first plastic package layer has a compressive stress with respect to the interposer, and the second plastic package layer has a tensile stress with respect to the interposer.
7. The secondary plastic package packaging structure of claim 1, further comprising: and the external solder balls are electrically connected to the metal wiring layer.
8. The secondary plastic package structure of claim 7, wherein the external solder balls are copper pillars or lead-free solder balls.
9. A secondary plastic package structure according to claim 1, wherein the first plastic package layer and the second plastic package layer are formed by two times of plastic package.
10. The secondary plastic package assembly of claim 1, wherein the second plastic package layer balances warpage caused by mismatching of the first plastic package layer and the interposer.
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| CN202023249037.8U CN213936169U (en) | 2020-12-29 | 2020-12-29 | Secondary plastic package packaging structure |
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| CN202023249037.8U CN213936169U (en) | 2020-12-29 | 2020-12-29 | Secondary plastic package packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112908947A (en) * | 2021-01-18 | 2021-06-04 | 上海先方半导体有限公司 | Plastic package structure and manufacturing method thereof |
| WO2024045757A1 (en) * | 2022-09-01 | 2024-03-07 | 盛合晶微半导体(江阴)有限公司 | 2.5d packaging structure and preparation method |
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2020
- 2020-12-29 CN CN202023249037.8U patent/CN213936169U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112908947A (en) * | 2021-01-18 | 2021-06-04 | 上海先方半导体有限公司 | Plastic package structure and manufacturing method thereof |
| WO2024045757A1 (en) * | 2022-09-01 | 2024-03-07 | 盛合晶微半导体(江阴)有限公司 | 2.5d packaging structure and preparation method |
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