CN109003961B - 3D system integrated structure and manufacturing method thereof - Google Patents
3D system integrated structure and manufacturing method thereof Download PDFInfo
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- CN109003961B CN109003961B CN201810831892.8A CN201810831892A CN109003961B CN 109003961 B CN109003961 B CN 109003961B CN 201810831892 A CN201810831892 A CN 201810831892A CN 109003961 B CN109003961 B CN 109003961B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The invention discloses a 3D system integrated structure, comprising: an adapter plate; the first through silicon via is arranged on the front surface of the adapter plate; the second through silicon via is arranged on the front surface of the adapter plate; the cavity is arranged on the back of the adapter plate; the first re-layout wiring layer and the bonding pad are arranged on the bottom surface of the cavity and electrically connected with the first through silicon via; a first chip disposed within the cavity, the first chip electrically connected to the first re-layout wiring layer and pads; the plastic packaging filling layer is arranged in gaps among the periphery, the bottom and the adapter plate of the first chip; the second chip is arranged on the back surface of the adapter plate and electrically connected to the second through silicon via; a second redistribution layer disposed on the front side of the interposer; and a solder structure disposed on a front side of the interposer, the solder structure being electrically connected to the second redistribution routing layer.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a 3D system integrated structure and a manufacturing method thereof.
Background
The demands of mobile device manufacturers for miniaturization, low cost, and high integration of products derive the requirements for cost, performance, and integration and functionality of system-in-package solutions for wafer-level packaging of related chips. In a system-in-package, several types of heterogeneous chips or passive devices are often involved in a package structure to achieve the functions of the package structure. The three-dimensional packaging technology has the combined advantages of planar and vertical space, and is a better direction for system-in-package.
Compared with a conventional packaging structure, the three-dimensional packaging technology based on the silicon adapter plate technology has the characteristics of smaller packaging size, higher integration level, better reliability and the like. An existing three-dimensional package structure based on a silicon interposer technology generally horizontally distributes different functional chips on the same surface of the silicon interposer, and fig. 1 shows an existing 2.5D/3D integrated package structure based on a silicon interposer technology, as shown in fig. 1, two types of functional chips 102 and 103 are respectively attached to the surface of a silicon interposer 101. The integration level of the package structure is relatively low, and the size of the adapter board is required to be large during integration, which indirectly results in high package cost.
Therefore, there is a need for a 3D system integrated structure and a method for manufacturing the same that at least partially improves the integration of a package structure based on a silicon interposer and reduces the package size.
Disclosure of Invention
In order to solve the problems that the integration level of a package structure based on a silicon interposer is relatively low and the size of the interposer is required to be large, which indirectly causes high package cost in the prior art, according to an embodiment of the present invention, a 3D system integration structure is provided, which includes:
an adapter plate;
the first through silicon via is arranged on the front surface of the adapter plate;
the second through silicon via is arranged on the front surface of the adapter plate;
the cavity is arranged on the back of the adapter plate;
the first re-layout wiring layer and the bonding pad are arranged on the bottom surface of the cavity and electrically connected with the first through silicon via;
a first chip disposed within the cavity, the first chip electrically connected to the first re-layout wiring layer and pads;
the plastic packaging filling layer is arranged in gaps among the periphery, the bottom and the adapter plate of the first chip;
the second chip is arranged on the back surface of the adapter plate and electrically connected to the second through silicon via;
a second redistribution layer disposed on the front side of the interposer; and
a solder structure disposed on the front side of the interposer, the solder structure being electrically connected to the second redistribution routing layer.
In one embodiment of the present invention, the first through silicon via has a smaller depth than the second through silicon via.
In one embodiment of the invention, the second chip is arranged above the first chip to form a 3D stereo structure.
In an embodiment of the invention, the second chip is a chip package structure.
In one embodiment of the present invention, the second re-layout wiring level has N levels of wiring, where N ≧ 2.
In one embodiment of the present invention, the 3D system integrated structure further includes a filling layer disposed between the second chip and the back surface of the interposer.
In one embodiment of the invention, the 3D system integrated structure further comprises a dielectric layer disposed between the wires of the second re-layout wiring layer.
According to another embodiment of the present invention, there is provided a method of manufacturing a 3D system integrated structure, including:
forming a first conductive through silicon via and a second conductive through silicon via with different depths on the front surface of the silicon adapter plate;
forming a first re-layout wiring layer and a first bump on the front surface of the silicon adapter plate, wherein the first re-layout wiring layer is electrically connected with the first conductive through silicon via and the second conductive through silicon via;
bonding a carrier plate on the front surface of the silicon adapter plate with the first salient points;
forming a cavity on the back of the silicon adapter plate to realize the exposure of the back of the first conductive silicon through hole;
forming a second re-layout wiring layer and a bonding pad on the bottom surface of the cavity;
a first chip is pasted in the cavity, and the first chip is electrically connected with the second re-layout wiring layer and the bonding pad after being pasted;
carrying out whole-surface plastic package on the back surface of the silicon adapter plate to form a plastic package layer;
thinning the plastic packaging layer and the silicon adapter plate to enable the back of the second conductive silicon through hole to expose;
forming a second bump electrically connected to the second conductive through-silicon-via;
bonding a second chip to the second bump; and
and removing the carrier plate.
In another embodiment of the present invention, the depth of the first conductive through silicon via is smaller than the depth of the second conductive through silicon via.
In another embodiment of the present invention, the method further comprises directly filling an underfill between the second chip and the silicon interposer.
The invention provides a 3D system integrated structure and a manufacturing method thereof.A TSV through holes with different depths are manufactured on a silicon adapter plate by adopting a TSV First technology, a cavity structure is formed on the silicon adapter plate by an etching process, a buried chip or an integrated passive device is formed in the cavity of the adapter plate, and finally other chips are pasted in the vertical direction. The three-dimensional packaging structure increases the packaging integration level in the vertical direction and has the characteristics of small packaging volume, low cost, short interconnection, high reliability and the like.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 is a schematic cross-sectional view illustrating a package structure based on a silicon interposer according to the prior art of the present invention.
Fig. 2 shows a schematic cross-sectional view of a 3D system integration structure 200 according to an embodiment of the invention.
Fig. 3A-3K illustrate cross-sectional projection views of a process for forming a 3D system integration structure 200 according to an embodiment of the invention.
Fig. 4 illustrates a flow diagram for forming a 3D system integration architecture 200 according to an embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a 3D system integrated structure and a manufacturing method thereof.A TSV (through silicon via First) technology with different depths is adopted to manufacture TSV through holes with different depths on a silicon adapter plate, a cavity structure is formed on the silicon adapter plate through an etching process, then a buried chip or an integrated passive device is formed in the cavity of the adapter plate, and finally other chips are pasted in the vertical direction. The three-dimensional packaging structure increases the packaging integration level in the vertical direction and has the characteristics of small packaging volume, low cost, short interconnection, high reliability and the like.
A 3D system integration structure according to the present invention is described in detail below with reference to fig. 2. Fig. 2 shows a schematic cross-sectional view of a 3D system integration structure 200 according to an embodiment of the invention. As shown in fig. 2, the 3D system integrated structure 200 further includes an interposer 201, a first through-silicon via 202, a second through-silicon via 203, an interposer cavity 204, a first redistribution layer and a bonding pad 205, a first chip 206, a mold filling layer 207, a second chip 208, a first bonding structure 209, a filling dielectric layer 210, a second redistribution layer 211, a dielectric layer 212, and a second bonding structure 213.
The interposer 201 is a main component of the 3D package structure, the through-silicon via is formed inside the interposer 201, and the functional chip is also carried on the interposer. In one embodiment of the present invention, interposer 201 is a silicon interposer. To realize wafer level packaging, the interposer 201 may be 300mm or 200mm, which is currently common wafer size. In another embodiment of the present invention, the interposer 201 may be an interposer made of other materials such as a glass interposer and a ceramic interposer.
The first through-silicon via 202 and the second through-silicon via 203 are located on the same surface (front surface) of the interposer 201. The substrate may be formed by one-time fabrication, or may be formed separately. In one embodiment of the present invention, different etching rates of the two types of vias are achieved by controlling the difference in Critical Dimension (CD) of the first through-silicon-via 202 and the second through-silicon-via 203, thereby achieving different via depths. In another embodiment of the present invention, there may be third and fourth through silicon vias (not shown) in addition to the first through silicon via 202 and the second through silicon via 203 to achieve more vertical packaging effect.
Through the back graphical etching of the adapter plate 201, an adapter plate cavity 204 is formed at a position corresponding to the first through-silicon-via 202 of the adapter plate, and after the adapter plate cavity 204 is formed, the first through-silicon-via 202 is exposed. In one embodiment of the present invention, the interposer 201 may be formed by bonding the front surface of the interposer 201 to a carrier and then performing photolithography, etching, and the like on the back surface of the interposer 201. The interposer cavity 204 is sized to meet the dimensions of the subsequent embedded chip.
A first redistribution routing layer and pad 205 is formed at the bottom of the interposer cavity 204, the first redistribution routing layer and pad 205 forming an electrical connection with the first through-silicon-via 202. The first re-layout wiring layer and the pad 205 may be formed by plating, deposition, or the like. Optionally, a dielectric layer (not shown) is formed between the first redistribution routing layer and the bonding pad 205 for electrical and mechanical protection.
The first chip 206 is located in the interposer cavity 204 and electrically connected to the first redistribution layer and the corresponding location of the pad 205 through mounting, soldering, bonding, and the like. In one embodiment of the present invention, first chip 206 is bonded to the first redistribution routing layer and to the chip pads of pads 205 by a flip-chip bonding process. In an embodiment of the present invention, the first chip 206 may be a functional chip such as a processor, MCU, DSP, memory, IPD, etc.
The plastic package filling layer 207 is disposed in a gap between the first chip 206 and the interposer cavity 204, and plays a role in protecting the chip. In one embodiment of the present invention, the mold filling layer 207 is located around the first chip 206 and in the gap between the bottom and the interposer cavity 204; in another embodiment of the present invention, the mold filling layer 207 further covers the upper portion of the first chip 206.
The second chip 208 is disposed on the back side of the interposer 201, and is electrically connected to the second through-silicon via 203 of the interposer 201 through the first bonding structure 209. In an embodiment of the present invention, the second chip 208 may be a single chip or a wafer-level chip to implement wafer-level packaging, and the first bonding structures 209 are bumps such as solder balls and copper pillars; in yet another embodiment of the present invention, the second chip 208 may also be an already packaged chip structure. In one embodiment of the present invention, the second chip 208 may be a functional chip or module such as a processor, an MCU, a DSP, a memory, a sensor, etc.
Optionally, a filling dielectric layer 210 is disposed between the second chip 208 and the interposer 201, and the filling dielectric layer 210 plays a role in electrical insulation and mechanical protection of the package structure. In one embodiment of the present invention, the filling dielectric layer 210 is an underfill.
The second redistribution routing layer 211 is disposed on the front surface of the interposer 201, and the second redistribution routing layer 211 may be one or more layers according to design requirements, wherein a pad may be disposed on the outermost layer. The second redistribution wiring layer 211 is electrically connected to the first and second through silicon vias 202 and 203, so as to realize electrical and/or signal connection between the first and second chips 206 and 208 and/or between external IO.
Alternatively, a dielectric layer 212 may be formed between the second re-layout wiring layers 211.
The second soldering structure 213 is disposed on the outermost layer of the front surface of the interposer 201 and electrically connected to the second redistribution layer 211, thereby interconnecting the entire 3D system integrated structure with external power and/or signals.
A process of forming a 3D system integration structure 200 is described in detail below with reference to fig. 3A to 3K and fig. 4. FIGS. 3A-3K illustrate cross-sectional projection views of a process for forming a 3D system integration structure 200 according to one embodiment of the invention; fig. 4 illustrates a flow diagram for forming a 3D system integration architecture 200 according to an embodiment of the present invention.
First, in step 401, as shown in fig. 3A, conductive Through Silicon Vias (TSVs) of different depths are formed on the front surface of the silicon interposer 301. The specific forming process can be formed by processes such as patterned etching, seed layer deposition, electroplating and the like, and the TSV control of two types of different depths can be manufactured according to the principle that different CD etching rates are different. In a specific embodiment of the present invention, two different depths of the first TSV 302 and the second TSV303 are formed, wherein the depth and size of the second TSV303 is greater than the first TSV 302.
Next, in step 402, as shown in fig. 3B, a first redistribution routing layer (RDL)304 and a first bump 305 are formed on the front side of the silicon interposer 301 where the first TSV 302 and the second TSV303 are located. A dielectric layer 306 is optionally formed in a non-conductive area of the first redistribution routing layer (RDL)304 for insulation and mechanical protection.
Then, in step 403, as shown in fig. 3C, a carrier board 307 is bonded to the front surface of the silicon interposer 301 with the first bumps 305 completed. The carrier plate 307 serves as a support for the subsequent manufacturing process of the interposer. The carrier 307 may be a wafer or glass.
Next, in step 404, as shown in fig. 3D, a cavity 308 is patterned in the back surface region of the silicon interposer 301, so as to expose the back surface of the first TSV 302. In one embodiment of the present invention, the cavity 308 may be formed by performing a photolithography, etching, or the like process on the backside of the silicon interposer 301. The size of the cavity 308 is required to meet the size of the subsequently embedded chip.
Then, in step 405, as shown in fig. 3E, a second redistribution layer (RDL) and a pad 309 are formed on the bottom surface of the cavity 308. A second redistribution routing layer (RDL) and pad 309 are electrically connected to the first TSV 302. In one embodiment of the present invention, a second re-layout wiring layer (RDL) and a pad 309 are formed by a patterned plating process; in yet another embodiment of the present invention, a second re-layout wiring layer (RDL) and pads 309 are formed by a patterned deposition process. In addition, a dielectric layer 310 is optionally formed in a non-conductive area of the second redistribution routing layer (RDL)309 for insulation and mechanical protection.
Next, in step 406, as shown in fig. 3F, a first chip 311 is mounted in the cavity 308, and the first chip 311 is mounted and electrically connected to a second redistribution layer (RDL) and a pad 309. The first chip 311 may be a functional chip such as a processor, an MCU, a DSP, a memory, and an IPD. In one embodiment of the present invention, the first chip 311 has a soldering mechanism 312 such as solder balls or copper pillars, and the first chip 311 is mounted on the second redistribution layer (RDL) and corresponding pads of the pads 309 by the soldering mechanism 312 through a flip-chip bonding process.
Next, in step 407, as shown in fig. 3G, the entire back surface of the silicon interposer 301 is subjected to mold sealing to form a mold protective layer 313 for the first chip 311. The plastic protection layer 313 covers the space between the bottom and the periphery of the first chip 311 and the silicon interposer 301, and covers the top of the chip 311.
Next, in step 408, as shown in fig. 3H, the plastic sealing protection layer 313 and the back surface of the silicon interposer 301 are thinned, so as to expose the second TSV 303. In one embodiment of the invention, thinning may be achieved by a mechanical grinding, Chemical Mechanical Polishing (CMP) process.
Then, in step 409, as shown in fig. 3I, a second bump 314 is formed. The second bump 314 is formed at an exposed position of the second TSV303 and electrically connected to the second TSV 303. In one embodiment of the present invention, the second bump 314 is a copper pillar or a solder ball.
Next, at step 410, as shown in fig. 3J, the second chip 315 is soldered to the second bump 314. The second chip 315 and the first chip form a vertical three-dimensional package structure.
Finally, in step 411, as shown in fig. 3K, the carrier 307 on the front surface of the silicon interposer 301 is removed to form the reddest 3D package structure.
Optionally, the method further includes cutting the 3D package structure with the wafer level package completed to form a single 3D system integrated structure.
According to the 3D system integrated structure and the manufacturing method thereof provided by the invention, TSV through holes with different depths are manufactured on a silicon adapter plate by adopting a TSV First technology, a cavity structure is formed on the silicon adapter plate through an etching process, then a buried chip or an integrated passive device is formed in the cavity of the adapter plate, and finally other chips are pasted in the vertical direction. The three-dimensional packaging structure increases the packaging integration level in the vertical direction and has the characteristics of small packaging volume, low cost, short interconnection, high reliability and the like.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (3)
1. A method of manufacturing a 3D system integrated structure, comprising:
forming a first conductive through silicon via and a second conductive through silicon via with different depths on the front surface of the silicon adapter plate;
forming a first re-layout wiring layer and a first bump on the front surface of the silicon adapter plate, wherein the first re-layout wiring layer is electrically connected with the first conductive through silicon via and the second conductive through silicon via;
bonding a carrier plate on the front surface of the silicon adapter plate with the first salient points;
forming a cavity on the back of the silicon adapter plate to realize the exposure of the back of the first conductive silicon through hole;
forming a second re-layout wiring layer and a bonding pad on the bottom surface of the cavity;
a first chip is pasted in the cavity, and the first chip is electrically connected with the second re-layout wiring layer and the bonding pad after being pasted;
carrying out whole-surface plastic package on the back surface of the silicon adapter plate to form a plastic package layer;
thinning the plastic packaging layer and the silicon adapter plate to enable the back of the second conductive silicon through hole to expose;
forming a second bump electrically connected to the second conductive through-silicon-via;
bonding a second chip to the second bump; and
and removing the carrier plate.
2. The method of claim 1, wherein a depth of the first conductive through silicon via is less than a depth of the second conductive through silicon via.
3. The method of claim 1, further comprising filling an underfill between the second chip and the silicon interposer.
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| CN110010548B (en) * | 2018-12-26 | 2021-08-24 | 浙江集迈科微电子有限公司 | Manufacturing method of cavity structure with bonding pad at bottom |
| CN109945852B (en) * | 2019-03-22 | 2021-05-28 | 中国科学院微电子研究所 | Packaging structure of gyroscope and manufacturing method |
| CN111293078B (en) * | 2020-03-17 | 2022-05-27 | 浙江大学 | Method for embedding chip into cavities on front surface and back surface of adapter plate |
| CN111968942B (en) * | 2020-08-24 | 2023-08-04 | 浙江集迈科微电子有限公司 | Interconnection technology for interconnecting radio frequency modules on side walls of adapter plates |
| CN116250074A (en) * | 2020-09-30 | 2023-06-09 | 华为技术有限公司 | Three-dimensional integrated circuit, preparation method thereof and electronic equipment |
| CN112331635B (en) * | 2020-11-04 | 2022-06-07 | 中国科学院微电子研究所 | Vertical packaging structure and packaging method based on adapter plate |
| WO2022161249A1 (en) * | 2021-01-29 | 2022-08-04 | 中芯集成电路（宁波）有限公司 | Wafer-level packaging structure and manufacturing method therefor |
| CN115312496A (en) * | 2022-07-12 | 2022-11-08 | 武汉大学 | Three-dimensional semiconductor integrated packaging structure and process based on rear through hole technology |
| CN117476550B (en) * | 2023-12-26 | 2024-04-05 | 季华实验室 | System-level fan-out type packaging method and packaging structure |
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| KR101461630B1 (en) * | 2008-11-06 | 2014-11-20 | 삼성전자주식회사 | Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof |
| US10163744B2 (en) * | 2011-09-07 | 2018-12-25 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure |
| US20150262902A1 (en) * | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
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| CN105845636A (en) * | 2010-04-16 | 2016-08-10 | 台湾积体电路制造股份有限公司 | TSVs with different sizes in interposers for bonding dies |
| CN106409777A (en) * | 2015-07-28 | 2017-02-15 | 钰桥半导体股份有限公司 | Package-on-package semiconductor assembly having bottom device confined by dielectric recess |
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Application publication date: 20181214 Assignee: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2022980027357 Denomination of invention: A 3D system integration structure and its manufacturing method Granted publication date: 20200616 License type: Common License Record date: 20221213 |