CN117476550B - System-level fan-out type packaging method and packaging structure - Google Patents
System-level fan-out type packaging method and packaging structure Download PDFInfo
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- CN117476550B CN117476550B CN202311805331.8A CN202311805331A CN117476550B CN 117476550 B CN117476550 B CN 117476550B CN 202311805331 A CN202311805331 A CN 202311805331A CN 117476550 B CN117476550 B CN 117476550B
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- 238000000034 method Methods 0.000 title claims abstract description 75
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 75
- 239000010703 silicon Substances 0.000 claims description 75
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 72
- 229910052751 metal Inorganic materials 0.000 claims description 69
- 239000002184 metal Substances 0.000 claims description 69
- 238000002161 passivation Methods 0.000 claims description 43
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 40
- 229910052802 copper Inorganic materials 0.000 claims description 40
- 239000010949 copper Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 10
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- 238000009713 electroplating Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 160
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- 238000010586 diagram Methods 0.000 description 5
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- 238000005538 encapsulation Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The application relates to the technical field of system-in-package, and particularly provides a system-in-fan-out type packaging method and a packaging structure, wherein the method comprises the following steps: manufacturing a packaging monomer and a first packaging body, wherein the packaging monomer comprises a first chip group, the first chip group comprises a first chip and a second chip which are respectively positioned on the upper side and the lower side of the packaging monomer, and the first packaging body comprises two second chip groups; forming a first cavity between two fourth chips; vertically mounting the side part of the packaging monomer into the first cavity, and electrically connecting the other bonding pad of the first chip and the other bonding pad of the second chip with the two second chip groups respectively by utilizing the first solder balls; forming a second solder ball on the third chip; according to the method, complex wiring is not required to be arranged between the packaging single body and the first packaging body, so that the problem that the system-level fan-out type packaging structure is large in size due to the fact that the complex wiring is required to be arranged to achieve interconnection between the multiple layers of chips is effectively solved.
Description
Technical Field
The application relates to the technical field of system-in-package, in particular to a system-in-fan-out type packaging method and a packaging structure.
Background
With the trend of high performance and integration of electronic products, chips develop to the directions of higher density, higher speed, lower cost and the like, and because the system-in-package has the advantages of providing more and stronger system functions, having good process compatibility, strong flexibility and adaptability, being easy for block test, having short interconnection leads between bare chips in the package, effectively reducing the time delay and crosstalk of interconnection lines of a system, reducing capacitive reactance, enabling devices to work at higher frequency, improving the transmission bandwidth and data rate of a system bus, having low working voltage, having low system power consumption and the like, the system-in-package becomes an important development trend.
The existing system-in-package method needs to form a plurality of packages first, then form a three-dimensional fan-out type package structure composed of multiple layers of chips in a manner of stacking and secondarily packaging the plurality of packages, namely the existing system-in-package method needs to form the three-dimensional fan-out type package structure in a manner of stacking and packaging, specifically, taking forming the three-dimensional fan-out type package structure composed of four layers of chips as an example, the existing system-in-package method needs to form two packages composed of two layers of chips first, and then form the three-dimensional fan-out type package structure in a manner of stacking and packaging the two packages. Since the existing system-in-package method needs to complete interconnection between the multi-layer chips by setting complex wiring, and the existing system-in-package method has limited wiring precision, the existing system-in-package method needs to occupy a large amount of packaging structure space to place the complex wiring, that is, the existing system-in-package method has the problems of high packaging cost and large system-in-fan-out type packaging structure volume caused by the need of setting complex wiring to achieve interconnection between the multi-layer chips.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The invention aims to provide a system-in fan-out type packaging method and a packaging structure, which do not need to set complex wiring between a packaging single body and a first packaging body, so that the problem that the system-in fan-out type packaging structure is large in size due to the fact that the complex wiring is required to be set to realize interconnection among multiple layers of chips is effectively solved.
In a first aspect, the present application provides a system-in-fan-out package method, including the steps of:
manufacturing a packaging monomer and a first packaging body, wherein the packaging monomer comprises a first chip group, the first chip group comprises a first chip and a second chip which are respectively positioned on the upper side and the lower side of the packaging monomer, a first bonding pad of the first chip and a bonding pad of the second chip are vertically interconnected, the first packaging body comprises two second chip groups, the second chip group comprises a fourth chip and a third chip which are respectively positioned on the upper side and the lower side of the first packaging body, the two third chips are horizontally interconnected, and the third chip is vertically interconnected with the fourth chip of the same chip group;
forming a first cavity between two fourth chips;
vertically mounting the side part of the packaging monomer into the first cavity, and electrically connecting the other bonding pad of the first chip and the other bonding pad of the second chip with the two second chip groups respectively by utilizing the first solder balls;
And forming a second solder ball on the third chip.
According to the system-level fan-out type packaging method, firstly, the packaging single body and the first packaging body are manufactured, then the first cavity is formed between the two fourth chips, the side part of the packaging single body is vertically attached to the first cavity, finally, the first solder balls are used for enabling the first chip and the second chip to be respectively electrically connected with the two second chip sets, the second solder balls are formed on the third chip, the first chip and the second chip are vertically interconnected, the third chip and the fourth chip of the same second chip set are vertically interconnected, the two third chips are horizontally interconnected, the first chip and the second chip are respectively electrically connected with the two fourth chips through the first solder balls, namely, the interconnection between the multi-layer chips can be completed only through the first solder balls, so that complex wiring is not required to be arranged between the packaging single body and the first packaging body, namely, the complex wiring is not required to be placed on the third chip, and the problem that the system-level fan-out type packaging structure is large due to the fact that the complex wiring is required to be arranged to achieve interconnection between the multi-layer chips is effectively solved.
Optionally, the step of making the encapsulation monomer includes:
forming a plurality of second cavities on the front surface of the first silicon wafer;
inversely mounting the first chip in the second cavity;
forming a plurality of first conductive heat-conducting columns on the first silicon wafer, and forming a first rewiring layer on the front surface of the first silicon wafer, so that one end of each first conductive heat-conducting column is connected with a first chip bonding pad of a corresponding first chip group, and each first conductive heat-conducting column corresponds to one first chip group and is positioned on any side of the first chip;
the front surface of the first silicon wafer is downwards attached to the carrier plate through temporary bonding glue;
forming a plurality of third cavities facing the second cavities on the back surface of the first silicon wafer;
reversely mounting the second chip in the third cavity, and forming a second rewiring layer on the back surface of the first silicon wafer so that the other end of the first conductive heat conduction column is connected with a corresponding second chip-bonding pad of the first chip group and a second packaging body comprising a plurality of first chip groups is formed;
slicing the second packaging body to form a plurality of packaging monomers.
Because this technical scheme's first chip subsides dress is in the second cavity, and this technical scheme's second chip subsides dress is in the third cavity, and this second cavity and third cavity can play the effect of assistance-localization real-time when the chip subsides dress, consequently this technical scheme can improve the paster precision of chip effectively and avoid appearing because first chip or second chip receive the influence of fluid force and lead to the condition of first chip or second chip drift.
Optionally, the step of forming the first rewiring layer on the front side of the first silicon wafer is the same as the step of forming the second rewiring layer on the back side of the first silicon wafer, and the step of forming the first rewiring layer on the front side of the first silicon wafer includes:
forming a first passivation film layer on the front surface of the first silicon wafer;
forming a bonding pad facing the first chip and a first opening facing the first conductive heat conduction column on the first passivation film layer;
forming a metal copper layer on the first passivation film layer;
forming a photosensitive film layer on the metal copper layer;
exposing and developing the photosensitive film layer to form a first patterned mask on the metallic copper layer;
etching the metal copper layer based on the first patterned mask to form a first metal rewiring layer;
removing the first patterned mask;
a second passivation film layer is formed on the first metal rewiring layer to form a first rewiring layer.
Before forming the first rewiring layer, the first chip is firstly mounted in the second cavity, the first rewiring layer can completely cover the front face of the first silicon wafer, namely, the first rewiring layer can perform sealing and protecting functions on the first chip, while before forming the second rewiring layer, the second chip is firstly mounted in the third cavity, the second rewiring layer can completely cover the back face of the first silicon wafer, namely, the second rewiring layer can perform sealing and protecting functions on the second chip, therefore, the technical scheme does not need to perform plastic packaging on the front face and the back face of the first silicon wafer, and the problem that when a system-level fan-out type packaging structure is subjected to plastic packaging, different layer interfaces are inconsistent in thermal matching performance, so that the different layer interfaces are thermally mismatched, and even warp under the stress effect is effectively solved, and the reliability of the system-level fan-out type packaging structure is effectively improved.
Optionally, the step of forming a first passivation film layer on the front surface of the first silicon wafer includes:
forming a first passivation film layer on the front surface of the first silicon wafer based on a dry pressing film process or a glue printing process;
the step of forming a second passivation film layer on the first metal rewiring layer includes:
and forming a second passivation film layer on the first metal rewiring layer based on a press-drying film process or a glue printing process.
Optionally, the step of forming a metallic copper layer on the first passivation film layer includes:
sequentially forming a metal seed layer and a metal copper layer on the first passivation film layer;
the step of etching the metallic copper layer based on the first patterned mask to form a first metal rewiring layer comprises:
and etching the metal seed layer and the metal copper layer based on the first patterned mask to form a first metal rewiring layer.
According to the technical scheme, the metal seed layer is formed on the first passivation film layer, and then the metal copper layer is formed on the metal seed layer, and as the metal seed layer can increase the binding force between the metal copper layer and the contact surface, the situation that the metal copper layer falls off due to the fact that the binding force between the metal copper layer and the contact surface is too small can be effectively avoided.
Optionally, the step of sequentially forming a metal seed layer and a metal copper layer on the first passivation film layer includes:
forming a metal seed layer on the first passivation film layer based on a physical vapor deposition process;
a metallic copper layer is formed on the metal seed layer based on an electroplating process.
Optionally, the step of fabricating the first package includes:
forming two fourth cavities on the back surface of the second silicon wafer;
reversely attaching the third chip in the fourth cavity;
forming two second conductive heat-conducting columns on the second silicon wafer, and forming a third rewiring layer on the back surface of the second silicon wafer, so that one end of each second conductive heat-conducting column is connected with a bonding pad of a third chip of a corresponding second chip set, and each second conductive heat-conducting column corresponds to one second chip set and is positioned on one side of the third chip far away from the other second chip set;
the back surface of the second silicon wafer is downwards attached to the carrier plate through temporary bonding glue;
forming two fifth cavities facing the fourth cavity on the front surface of the second silicon wafer;
and reversely mounting the fourth chip in the fifth cavity, and forming a fourth rewiring layer on the front surface of the second silicon wafer so that the other end of the second conductive heat conduction column is connected with a corresponding fourth chip bonding pad of the second chip group and a first packaging body comprising two second chip groups is formed.
Optionally, the step of vertically mounting the package unit side portion in the first cavity and electrically connecting the first chip further pad and the second chip further pad to the two second chip sets by using the first solder ball includes:
forming first solder balls on the other bonding pad of the first chip and the other bonding pad of the second chip based on a ball mounting process;
mounting the side part of the packaging single body into the first cavity;
and reflow the first solder balls based on a reflow process so that the other bonding pad of the first chip and the other bonding pad of the second chip are respectively and electrically connected with the two second chip groups.
Optionally, the step of vertically mounting the package unit side portion in the first cavity and electrically connecting the first chip further pad and the second chip further pad to the two second chip sets by using the first solder ball includes:
vertically attaching the side part of the packaging unit into the first cavity;
and forming first solder balls between the other bonding pad of the first chip and one of the second chip groups and between the other bonding pad of the second chip and the other second chip group based on a ball mounting process, so that the other bonding pad of the first chip and the other bonding pad of the second chip are respectively electrically connected with the two second chip groups.
In a second aspect, the present application further provides a system-in-fan-out package structure, including:
The packaging unit comprises a first chip group, wherein the first chip group comprises a first chip and a second chip which are respectively positioned on the upper side and the lower side of the packaging unit, and a first chip bonding pad and a second chip bonding pad are vertically interconnected;
the first packaging body comprises two second chip groups, wherein the second chip groups comprise a fourth chip and a third chip which are respectively positioned on the upper side and the lower side of the first packaging body, the two third chips are horizontally interconnected, and the third chip is vertically interconnected with the fourth chip of the same chip group;
the extending direction of the packaging unit is vertical to the extending direction of the first packaging body, and the side wall of the packaging unit is vertically attached in a first cavity formed between the two fourth chips;
the first solder ball is arranged between the other bonding pad of the first chip and one of the second chip groups and between the other bonding pad of the second chip and the other second chip group;
and the second solder ball is arranged on the third chip.
The utility model provides a system level fan-out type packaging structure, including encapsulation monomer and first packaging body, because first chip and second chip interconnect perpendicularly, the third chip interconnects perpendicularly with the fourth chip of same second chipset, two third chip horizontal interconnection, first chip and second chip pass through first solder ball respectively with two fourth chip electric connection, this application just need utilize first solder ball just can accomplish the interconnection between the multilayer chip promptly, consequently this application need not to set up complicated wiring between encapsulation monomer and first packaging body, this complex wiring is placed to this complex wiring to this application need not to occupy a large amount of packaging structure space promptly, thereby solve effectively and realize the interconnection between the multilayer chip and lead to the bulky problem of system level fan-out type packaging structure owing to setting up complicated wiring.
As can be seen from the above, the system-level fan-out packaging method and the packaging structure provided by the application are characterized in that firstly, the packaging unit and the first packaging body are manufactured, then the first cavity is formed between the two fourth chips, the side part of the packaging unit is vertically attached to the first cavity, finally, the first solder ball is used for enabling the first chip and the second chip to be respectively and electrically connected with the two second chip sets, and the second solder ball is formed on the third chip.
Drawings
Fig. 1 is a flowchart of a system-in-fan-out package method according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a packaging unit according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a first package according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a first cavity formed between two fourth chips according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a system-in-fan-out package structure according to an embodiment of the present application.
Fig. 6 is a schematic diagram illustrating formation of a first rewiring layer on a front side of a first silicon wafer according to an embodiment of the present application.
Reference numerals: 1. a first silicon wafer; 2. a first chip; 3. a first conductive thermal post; 4. a first rewiring layer; 401. a first passivation film layer; 402. a first metal rewiring layer; 5. a second chip; 6. a second rewiring layer; 7. a first solder ball; 8. a first chipset; 9. a second silicon wafer; 10. a third chip; 11. a second conductive heat-conducting post; 12. a third rewiring layer; 13. a fourth chip; 14. a fourth rewiring layer; 15. a second chipset; 16. a first cavity; 17. temporary bonding glue; 18. a second solder ball; 19. a metallic copper layer; 20. a photosensitive film layer; 21. a first patterned mask.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, as shown in fig. 1-6, the present application provides a system-in-fan-out package method, which includes the following steps:
s1, manufacturing a packaging single body and a first packaging body, wherein the packaging single body comprises a first chip set 8, the first chip set 8 comprises a first chip 2 and a second chip 5 which are respectively positioned on the upper side and the lower side of the packaging single body, one bonding pad of the first chip 2 is vertically interconnected with one bonding pad of the second chip 5, the first packaging body comprises two second chip sets 15, the second chip set 15 comprises a fourth chip 13 and a third chip 10 which are respectively positioned on the upper side and the lower side of the first packaging body, the two third chips 10 are horizontally interconnected, and the third chip 10 is vertically interconnected with a fourth chip 13 of the same chip set;
s2, forming a first cavity 16 between the two fourth chips 13;
s3, vertically mounting the side part of the packaging monomer into the first cavity 16, and electrically connecting the other bonding pad of the first chip 2 and the other bonding pad of the second chip 5 with the two second chip groups 15 by utilizing the first solder balls 7;
s4, forming second solder balls 18 on the third chip 10.
The first chip 2, the second chip 5, the third chip 10 and the fourth chip 13 of this embodiment each include two bonding pads, and the bonding pads of the first chip 2, the second chip 5, the third chip 10 and the fourth chip 13 are each disposed outward. In step S1, the package unit and the first package body may be manufactured by using the existing double-sided packaging process, specifically, the package unit of this embodiment includes a first chipset 8, where the first chipset 8 includes a first chip 2 and a second chip 5, the first chip 2 and the second chip 5 are located on the upper and lower sides of the package unit respectively, the first chip 2 may be vertically interconnected with the second chip 5 through a conductive pillar, the first package body includes two second chip sets 15, each second chip set 15 includes a third chip 10 and a fourth chip 13, the fourth chip 13 and the third chip 10 of the same second chip set 15 are located on the upper and lower sides of the second package body respectively, the two third chips 10 may be horizontally interconnected by a rewiring layer or a routing wire, etc., the third chip 10 may be vertically interconnected with the fourth chip 13 of the same second chip set 15 through a conductive pillar, and the conductive pillar is preferably located on a side of the third chip 10 away from the other second chip set 15. More specifically, one pad of the third chip 10 of this embodiment is vertically interconnected with one pad of the fourth chip 13 of the same second chipset 15, and the other pad of the third chip 10 of this embodiment is horizontally interconnected with one pad of the third chip 10 of another second chipset. It should be understood that there is no horizontal interconnection between the two fourth chips 13 of this embodiment.
Since the step S3 is equivalent to vertically attaching the package unit side to the first package body to form the three-dimensional fan-out package structure, in order to improve the structural stability of the three-dimensional fan-out package structure and connect the package unit with the two second chip sets at the same time, the step S2 needs to form a groove on the first package body into which the package unit side can be inserted, that is, form the first cavity 16 between the two fourth chips 13. Specifically, step S2 may form the first cavity 16 between the two fourth chips 13 by etching the first package based on the dry etching process, and step S2 may also form the first cavity 16 between the two fourth chips 13 by etching the first package using the laser etching process.
In step S3, the side portion of the package unit is first mounted vertically into the first cavity 16 (i.e. the extending direction of the package unit is perpendicular to the extending direction of the first package body), and then the first solder ball 7 is used to electrically connect the first chip 2 and the second chip 5 with the two second chip sets 15 respectively. After the package unit is vertically mounted in the first cavity 16, the first solder balls 7 may be formed between the first chip 2 and one of the second chip sets 15 and between the second chip 5 and the other second chip set 15 in step S3 by using an existing soldering process, and after the first solder balls 7 are formed, the first chip 2 and the second chip 5 are electrically connected to the two second chip sets 15, respectively. It should be understood that, since the third chips 10 are vertically interconnected with the fourth chips 13 of the same second chipset 15, and the two third chips 10 are horizontally interconnected, this embodiment can electrically connect the first chip 2 and the second chip 5 with the two second chipsets 15, respectively, only by electrically connecting the first chip 2 with one of the fourth chips 13 through the first solder balls 7 and electrically connecting the second chip 5 with the other fourth chip 13 through the first solder balls 7.
Step S4 may form the second solder balls 18 on the third chip 10 using an existing soldering process or a ball-mounting process to form a system in fan-out package structure including four chips.
The principle of this embodiment is: according to the system-level fan-out type packaging method, firstly, a packaging monomer and a first packaging body are manufactured, then a first cavity 16 is formed between two fourth chips 13, the side parts of the packaging monomer are vertically attached to the first cavity 16, finally, the first solder balls 7 are used for enabling the first chip 2 and the second chip 5 to be respectively and electrically connected with two second chip groups 15, and the second solder balls 18 are formed on the third chip 10, because the first chip 2 is vertically connected with the second chip 5, the third chip 10 is vertically connected with the fourth chips 13 of the same second chip group 15, the two third chips 10 are horizontally connected, and the first chip 2 and the second chip 5 are respectively and electrically connected with the two fourth chips 13 through the first solder balls 7, namely, the interconnection between the multi-layer chips can be completed only by using the first solder balls 7. In addition, since the upper side and the lower side of the package unit and the first package body of the embodiment are respectively provided with the chip and the interconnection structure, that is, the package unit and the first package body of the embodiment are respectively equivalent to the package structure adopting double-sided wiring and double-sided packaging, the embodiment can effectively improve the integration level of the system-in fan-out type package structure, thereby effectively reducing the volume of the system-in fan-out type package structure. It should be understood that, the system-in-fan-out packaging method provided in the present application can also be used to manufacture a plurality of system-in-fan-out packages at a time, specifically, step S1 manufactures a package board and a plurality of package units, where the package board includes a plurality of first packages, and when step S2 is performed, the embodiment forms a first cavity 16 between two fourth chips 13 of each first package, and when step S3 is performed, the embodiment needs to vertically attach a package unit side portion into each first cavity 16, and after step S4 is completed, the embodiment divides the package board into a plurality of system-in-fan-out packages (corresponding to a three-dimensional fan-out package) by using a dicing process.
In some embodiments, the step of making the encapsulation monomer comprises:
a1, forming a plurality of second cavities on the front surface of a first silicon wafer 1;
a2, reversely mounting the first chip 2 in the second cavity;
a3, forming a plurality of first conductive heat conduction columns 3 on the first silicon wafer 1, and forming a first rewiring layer 4 on the front surface of the first silicon wafer 1, so that one end of each first conductive heat conduction column 3 is connected with one bonding pad of a corresponding first chip 2 of a first chip group, and each first conductive heat conduction column 3 corresponds to one first chip group and is positioned on any side of the first chip 2;
a4, attaching the front surface of the first silicon wafer 1 to the carrier plate downwards through the temporary bonding adhesive 17;
a5, forming a plurality of third cavities opposite to the second cavities on the back surface of the first silicon wafer 1;
a6, reversely mounting the second chip 5 in the third cavity, and forming a second rewiring layer 6 on the back surface of the first silicon wafer 1 so that the other end of the first conductive heat conduction column 3 is connected with one bonding pad of the second chip 5 of the corresponding first chip group and a second package body comprising a plurality of first chip groups 8 is formed;
and A7, slicing the second packaging body to form a plurality of packaging monomers.
The specific workflow of step A1 may be: forming a second patterned mask on the front surface of the first silicon wafer 1 based on a photolithography process, wherein the shape of the second patterned mask corresponds to the shape of the second cavity; the front surface of the first silicon wafer 1 is etched based on the dry etching process and the second patterned mask to form a plurality of second cavities in the front surface of the first silicon wafer 1. The specific workflow of step A2 may be: attaching a DAF film to the back surface of the first chip 2 (i.e. the surface of the first chip 2 away from the bonding pad); the first chip 2 is reversely mounted in the second cavity by using a chip mounter. The specific workflow of forming the plurality of first conductive thermal pillars 3 on the first silicon wafer 1 in step A3 may be: forming a plurality of through-silicon vias (Through Silicon Via) on the first silicon wafer 1 based on an existing through-silicon via forming process; the through silicon vias are filled with a conductive material, such as copper or polysilicon, to form a plurality of first conductive thermal conductive pillars 3. Since the first conductive heat-conducting pillars 3 are capable of conducting electricity, the first rewiring layer 4 can be formed on the front surface of the first silicon wafer 1 by using the existing wafer level rewiring layer forming process in step A3, so that one end of the first conductive heat-conducting pillars 3 is connected with a pad of the first chip 2 of the corresponding first chipset. The specific workflow of step A5 is preferably the same as the specific workflow of step A1, the specific workflow of step A6 for mounting the second chip 5 is preferably the same as step A2, and the specific workflow of step A6 for forming the second rewiring layer 6 on the back side of the first silicon wafer 1 is preferably the same as the specific workflow of step A3 for forming the first rewiring layer 4 on the front side of the first silicon wafer 1. Step A7 dicing the second package based on the existing dicing process. Since the first chip 2 of the embodiment is inversely mounted in the second cavity, and the second chip 5 of the embodiment is inversely mounted in the third cavity, the second cavity and the third cavity can play a role in assisting positioning during chip mounting, so that the embodiment can effectively improve chip mounting accuracy and avoid the situation that the first chip 2 or the second chip 5 drifts due to the influence of fluid force on the first chip 2 or the second chip 5. It should be understood that this embodiment corresponds to forming the second package including the plurality of first chipsets 8 first and then dividing the second package into a plurality of package units, and since the second package of this embodiment needs to be divided into a plurality of package units, the plurality of first chipsets 8 of this embodiment may be interconnected, or the plurality of first chipsets 8 of this embodiment may not be interconnected, and this embodiment may remove the carrier plate and the temporary bonding adhesive 17 before performing step A7 or after performing step A7. It should also be appreciated that, since the embodiment selects the silicon wafer as the substrate, and the thermal conductivity of silicon is greater than that of resin, the heat dissipation performance of the system-in-fan package structure can be effectively improved compared to the resin-based fan-out package process. It should also be understood that the first through-silicon vias of this embodiment may be replaced by vias made of glass vias (TGV) and plastic vias (TMV), and specifically, the packaging unit includes a base layer, the first chip 2 and the second chip 5 are located in the base layer of the packaging unit, and the through-holes of this embodiment are related to the material of the base layer, for example, the material of the base layer is glass, the through-holes are TGV (glass vias), and for example, the material of the base layer is plastic, the through-holes are TMV (plastic vias), and since the first silicon wafer 1 of this embodiment corresponds to the base layer of the packaging unit, that is, the material of the base layer of the packaging unit of this embodiment is silicon.
In some embodiments, the step of forming the first rewiring layer 4 on the front side of the first silicon wafer 1 is the same as the step of forming the second rewiring layer 6 on the back side of the first silicon wafer 1, and the step of forming the first rewiring layer 4 on the front side of the first silicon wafer 1 includes:
b1, forming a first passivation film layer 401 on the front surface of the first silicon wafer 1;
b2, forming a bonding pad facing the first chip 2 and a first opening facing the first conductive heat conduction post 3 on the first passivation film layer 401;
b3, forming a metallic copper layer 19 on the first passivation film layer 401;
b4, forming a photosensitive film layer 20 on the metal copper layer 19;
b5, exposing and developing the photosensitive film layer 20 to form a first patterned mask 21 on the metallic copper layer 19;
b6, etching the metal copper layer 19 based on the first patterned mask 21 to form a first metal rewiring layer 402;
b7, removing the first patterned mask 21;
b8, forming a second passivation film layer on the first metal rewiring layer 402 to form the first rewiring layer 4.
The material of the first passivation film 401 in the step B1 may be PI (polyimide) or BCB (benzocyclobutene), and the first passivation film 401 may be an interlayer dielectric material of the multi-layered metal rewiring layer. Step B2 may form a pad facing the first chip 2 and a first opening facing the first conductive stud 3 on the first passivation film layer 401 using an existing mechanical removal method. Step B3 may form the metallic copper layer 19 on the first passivation film layer 401 based on an existing electroplating process. The first rewiring layer 4 of the embodiment corresponds to a multilayer structure formed by the first passivation film layer 401, the second passivation film layer and the first metal rewiring layer 402, and since the embodiment is capable of completely covering the front surface of the first silicon wafer 1 by mounting the first chip 2 in the second cavity before forming the first rewiring layer 4, that is, the first rewiring layer 4 can perform sealing and protecting functions on the first chip 2, and before forming the second rewiring layer 6, the embodiment is capable of completely covering the back surface of the first silicon wafer 1 by mounting the second chip 5 in the third cavity, that is, the second rewiring layer 6 can perform sealing and protecting functions on the second chip 5, the embodiment does not need to perform plastic packaging on the front surface and the back surface of the first silicon wafer 1, so that the problem that when the fan-out type packaging structure is in a system level, the thermal mismatch of different layer interfaces is inconsistent, the different layer interfaces are thermally mismatched, and even the problem that the stress of the fan-out type packaging structure is effectively improved in a system level is solved. It should be understood that, since the first passivation film layer 401 and the second passivation film layer are made of the same material, the specification drawing does not distinguish between the two.
In some embodiments, step B1 comprises:
b11, forming a first passivation film layer 401 on the front surface of the first silicon wafer 1 based on a dry pressing film process or a glue printing process;
step B8 includes:
b81, forming a second passivation film layer on the first metal rewiring layer 402 based on a press-dry film process or a paste printing process.
In some embodiments, step B3 comprises:
b31, sequentially forming a metal seed layer and a metal copper layer 19 on the first passivation film layer 401;
step B6 comprises:
b61, etching the metal seed layer and the metal copper layer 19 based on the first patterned mask 21 to form the first metal rewiring layer 402.
In this embodiment, a metal seed layer is formed on the first passivation film layer 401, and then a metal copper layer 19 is formed on the metal seed layer, and since the metal seed layer can increase the bonding force between the metal copper layer 19 and the contact surface, the embodiment can effectively avoid the situation that the metal copper layer 19 falls off due to too small bonding force between the metal copper layer 19 and the contact surface.
In some embodiments, step B31 comprises:
b311, forming a metal seed layer on the first passivation film layer 401 based on a physical vapor deposition process;
and B312, forming a metal copper layer 19 on the metal seed layer based on the electroplating process.
The metal seed layer of this embodiment preferably comprises a 0.05 μm titanium metal layer and a 1 μm copper layer, it being understood that the metal seed layer is not shown in the drawings since the thickness of the metal seed layer is much smaller than the thickness of the metal copper layer 19.
In some embodiments, the step of fabricating the first package includes:
c1, forming two fourth cavities on the back surface of the second silicon wafer 9;
c2, inversely mounting the third chip 10 in the fourth cavity;
c3, forming two second conductive heat-conducting pillars 11 on the second silicon wafer 9, and forming a third rewiring layer 12 on the back surface of the second silicon wafer 9, so that one end of the second conductive heat-conducting pillars 11 is connected with a pad of a third chip 10 of a corresponding second chip set, and each second conductive heat-conducting pillar 11 corresponds to one second chip set and is located on one side of the third chip 10 away from the other second chip set;
c4, attaching the back surface of the second silicon wafer 9 to the carrier plate downwards through the temporary bonding adhesive 17;
c5, forming two fifth cavities opposite to the fourth cavity on the front surface of the second silicon wafer 9;
and C6, reversely mounting the fourth chip 13 in the fifth cavity, and forming a fourth rewiring layer 14 on the front surface of the second silicon wafer 9 so that the other end of the second conductive heat conduction column 11 is connected with one bonding pad of the fourth chip 13 of the corresponding second chip group and a first package body comprising two second chip groups 15 is formed.
The vertical interconnection structure of the third chip 10 and the fourth chip 13 is the second conductive heat conduction post 11, and the specific step of manufacturing the first package in this embodiment is preferably the same as the specific step of manufacturing the second package in the above embodiment. It should be appreciated that since the second silicon wafer 9 is mounted on the carrier plate, this embodiment requires removal of the temporary bonding glue 17 and the carrier plate on the second silicon wafer 9 before performing step S4.
In some embodiments, step S3 comprises:
s31, forming a first solder ball 7 on the other bonding pad of the first chip 2 and the other bonding pad of the second chip 5 based on a ball mounting process;
s32, attaching the side part of the packaging single body into the first cavity 16;
and S33, remelting the first solder balls 7 based on a reflow process so that the other bonding pad of the first chip 2 and the other bonding pad of the second chip 5 are respectively electrically connected with the two second chip groups 15.
In some embodiments, step S3 comprises:
s31', vertically mounting the side part of the packaging unit into the first cavity 16;
s32', forming the first solder balls 7 between the other pad of the first chip 2 and one of the second chip groups 15 and the other pad of the second chip 5 and the other second chip group 15 based on the ball mounting process, so that the other pad of the first chip 2 and the other pad of the second chip 5 are electrically connected with the two second chip groups 15 respectively.
It should be appreciated that both of the above embodiments enable electrical connection of the first chip 2 and the second chip 5 with the two second chip sets 15 through the first solder balls 7, the first rewiring layer 4, the second rewiring layer 6, the third rewiring layer 12 and the fourth rewiring layer 14.
In some embodiments, step S3 comprises:
s31'', forming a first solder ball 7 on the other bonding pad of the first chip 2 and the other bonding pad of the second chip 5 based on a ball mounting process;
s32'', attaching a DAF Film (Die Attach Film, DAF Film is an ultrathin Film adhesive used for connecting a semiconductor chip and a packaging substrate and connecting the chip and the chip in a semiconductor packaging process) to the bottom of the first cavity 16;
s33', vertically attaching the packaging single side part to the DAF film;
s34, remelting the first solder balls 7 based on a reflow process so that the other bonding pad of the first chip 2 and the other bonding pad of the second chip 5 are respectively electrically connected with the two second chip groups 15;
s35, curing the DAF film.
As can be seen from the above, in the system-level fan-out packaging method provided by the present application, the packaging unit and the first packaging body are firstly manufactured, then the first cavity 16 is formed between the two fourth chips 13, and the packaging unit is vertically attached to the first cavity 16, and finally the first solder balls 7 are used to electrically connect the first chip 2 and the second chip 5 with the two second chip sets 15 respectively, and the second solder balls 18 are formed on the third chip 10, because the first chip 2 and the second chip 5 are vertically interconnected, the third chip 10 and the fourth chip 13 of the same second chip set 15 are vertically interconnected, the two third chips 10 are horizontally interconnected, and the first chip 2 and the second chip 5 are electrically connected with the two fourth chips 13 respectively through the first solder balls 7, namely, the interconnection between the multi-layer chips can be completed only by using the first solder balls 7.
In a second aspect, as shown in fig. 5, the present application further provides a system-in-fan-out package structure, which includes:
the packaging unit comprises a first chip set 8, wherein the first chip set 8 comprises a first chip 2 and a second chip 5 which are respectively positioned on the upper side and the lower side of the packaging unit, and one bonding pad of the first chip 2 and one bonding pad of the second chip 5 are vertically interconnected;
a first package including two second chip groups 15, the second chip groups 15 including a fourth chip 13 and a third chip 10 respectively located at upper and lower sides of the first package, the two third chips 10 being horizontally interconnected, the third chip 10 being vertically interconnected with the fourth chip 13 of the same chip group;
the extending direction of the packaging unit is perpendicular to the extending direction of the first packaging body, and the side part of the packaging unit is vertically attached in a first cavity 16 formed between the two fourth chips 13;
a first solder ball 7 disposed between the other pad of the first chip 2 and one of the second chip groups 15 and the other pad of the second chip 5 and the other second chip group 15;
second solder balls 18 are disposed on the third chip 10.
Embodiments of the present application provide a system-in-fan-out package structure, which is preferably manufactured by a system-in-fan-out package method provided in the first aspect. The working principle of a system-in-fan-out package structure provided in this embodiment is similar to that of a system-in-fan-out package method provided in the first aspect, and will not be discussed in detail here.
From the above, the system-level fan-out package structure provided by the application comprises a package monomer and a first package body, since the first chip 2 is vertically interconnected with the second chip 5, the third chip 10 is vertically interconnected with the fourth chip 13 of the same second chip set 15, the two third chips 10 are horizontally interconnected, the first chip 2 and the second chip 5 are respectively electrically connected with the two fourth chips 13 through the first solder balls 7, namely, the application can complete the interconnection between the multi-layer chips by only using the first solder balls 7, therefore, the application does not need to set complex wiring between the package monomer and the first package body, namely, the application does not need to occupy a large amount of package structure space to place the complex wiring, thereby effectively solving the problem of large volume of the system-level fan-out package structure due to the need to setting complex wiring to realize the interconnection between the multi-layer chips.
As can be seen from the above, the system-level fan-out packaging method and the packaging structure provided by the present application firstly make the packaging unit and the first packaging body, then form the first cavity 16 between the two fourth chips 13, and vertically attach the packaging unit side to the first cavity 16, finally make the first chip 2 and the second chip 5 electrically connect with the two second chip sets 15 respectively by using the first solder ball 7, and form the second solder ball 18 on the third chip 10, because the first chip 2 and the second chip 5 are vertically interconnected, the third chip 10 and the fourth chips 13 of the same second chip set 15 are vertically interconnected, the two third chips 10 are horizontally interconnected, and the first chip 2 and the second chip 5 are electrically connected with the two fourth chips 13 respectively by using the first solder ball 7, that is, the present application can complete the interconnection between the multi-layer chips only by using the first solder ball 7, that is, the present application does not need to occupy a large amount of packaging structure space to place the complex wiring, thereby effectively realizing the multi-layer interconnection between the multi-layer chip system due to the complex wiring.
In the embodiments provided herein, it should be understood that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (6)
1. A system-in-fan-out package method, comprising the steps of:
manufacturing a packaging monomer and a first packaging body, wherein the packaging monomer comprises a first chip group, the first chip group comprises a first chip and a second chip which are respectively positioned on the upper side and the lower side of the packaging monomer, a bonding pad of the first chip and a bonding pad of the second chip are vertically interconnected, the first packaging body comprises two second chip groups, the second chip group comprises a fourth chip and a third chip which are respectively positioned on the upper side and the lower side of the first packaging body, the two third chips are horizontally interconnected, and the third chip is vertically interconnected with a fourth chip of the same chip group;
Forming a first cavity between two fourth chips;
vertically attaching the side part of the packaging monomer into the first cavity, and electrically connecting the other bonding pad of the first chip and the other bonding pad of the second chip with the two second chip groups by using a first solder ball;
forming a second solder ball on the third chip;
the step of manufacturing the packaging single body comprises the following steps:
forming a plurality of second cavities on the front surface of the first silicon wafer;
inversely attaching the first chip in the second cavity;
forming a plurality of first conductive heat-conducting columns on the first silicon wafer, and forming a first rewiring layer on the front surface of the first silicon wafer, so that one end of each first conductive heat-conducting column is connected with a first chip bonding pad of a corresponding first chip group, and each first conductive heat-conducting column corresponds to one first chip group and is positioned on any side of the first chip;
the front surface of the first silicon wafer is downwards attached to a carrier plate through temporary bonding glue;
forming a plurality of third cavities facing the second cavities on the back surface of the first silicon wafer;
reversely mounting the second chip in the third cavity, and forming a second rewiring layer on the back surface of the first silicon wafer, so that the other end of the first conductive heat conduction column is connected with a corresponding second chip-bonding pad of the first chip group and a second packaging body comprising a plurality of first chip groups is formed;
Slicing the second packaging body to form a plurality of packaging monomers;
the specific steps for manufacturing the first packaging body are the same as those for manufacturing the second packaging body;
the step of forming the first rewiring layer on the front side of the first silicon wafer is the same as the step of forming the second rewiring layer on the back side of the first silicon wafer, and the step of forming the first rewiring layer on the front side of the first silicon wafer includes:
forming a first passivation film layer on the front surface of the first silicon wafer;
forming a bonding pad opposite to the first chip and a first opening opposite to the first conductive heat conduction column on the first passivation film layer;
forming a metal copper layer on the first passivation film layer;
forming a photosensitive film layer on the metal copper layer;
exposing and developing the photosensitive film layer to form a first patterned mask on the metallic copper layer;
etching the metal copper layer based on the first patterned mask to form a first metal rewiring layer;
removing the first patterned mask;
forming a second passivation film layer on the first metal rewiring layer to form a first rewiring layer;
The step of forming a metallic copper layer on the first passivation film layer includes:
sequentially forming a metal seed layer and a metal copper layer on the first passivation film layer;
the step of etching the metal copper layer based on the first patterned mask to form a first metal rewiring layer comprises the following steps:
and etching the metal seed layer and the metal copper layer based on the first patterned mask to form a first metal rewiring layer.
2. The system-in-fan-out package method of claim 1, wherein the forming a first passivation film layer on the front side of the first silicon wafer comprises:
forming a first passivation film layer on the front surface of the first silicon wafer based on a dry pressing film process or a glue printing process;
the step of forming a second passivation film layer on the first metal rewiring layer includes:
and forming a second passivation film layer on the first metal rewiring layer based on a press-drying film process or a glue printing process.
3. The system-in-fan-out package method of claim 1, wherein sequentially forming a metal seed layer and a metal copper layer on the first passivation film layer comprises:
forming a metal seed layer on the first passivation film layer based on a physical vapor deposition process;
A metallic copper layer is formed on the metallic seed layer based on an electroplating process.
4. The system-in-fan-out type packaging method according to claim 1, wherein the step of vertically mounting the package unit side portion into the first cavity and electrically connecting the first chip further pad and the second chip further pad to the two second chip sets by using a first solder ball includes:
forming first solder balls on the other bonding pad of the first chip and the other bonding pad of the second chip based on a ball mounting process;
mounting the packaging single side part into the first cavity;
and remelting the first solder balls based on a reflow process so that the other bonding pad of the first chip and the other bonding pad of the second chip are respectively and electrically connected with the two second chip groups.
5. The system-in-fan-out type packaging method according to claim 1, wherein the step of vertically mounting the package unit side portion into the first cavity and electrically connecting the first chip further pad and the second chip further pad to the two second chip sets by using a first solder ball includes:
vertically mounting the packaging single side part into the first cavity;
And forming first solder balls between the other bonding pad of the first chip and one of the second chip groups and between the other bonding pad of the second chip and the other of the second chip groups based on a ball mounting process, so that the other bonding pad of the first chip and the other bonding pad of the second chip are respectively electrically connected with the two second chip groups.
6. A system-in-fan-out package structure, characterized in that it is made by a system-in-fan-out package method selected from any of claims 1-5, comprising:
a packaging unit, which comprises a first chip group, wherein the first chip group comprises a first chip and a second chip which are respectively positioned on the upper side and the lower side of the packaging unit, and a bonding pad of the first chip and a bonding pad of the second chip are vertically interconnected;
the first packaging body comprises two second chip groups, wherein the second chip groups comprise a fourth chip and a third chip which are respectively positioned on the upper side and the lower side of the first packaging body, the two third chips are horizontally interconnected, and the third chip is vertically interconnected with the fourth chip of the same chip group;
the extending direction of the packaging unit is perpendicular to the extending direction of the first packaging body, and the side part of the packaging unit is vertically attached in a first cavity formed between the two fourth chips;
The first solder ball is arranged between the other bonding pad of the first chip and one of the second chip groups and between the other bonding pad of the second chip and the other second chip group;
and the second solder ball is arranged on the third chip.
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