CN109003961A - A kind of 3D system integration structure and its manufacturing method - Google Patents
A kind of 3D system integration structure and its manufacturing method Download PDFInfo
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- CN109003961A CN109003961A CN201810831892.8A CN201810831892A CN109003961A CN 109003961 A CN109003961 A CN 109003961A CN 201810831892 A CN201810831892 A CN 201810831892A CN 109003961 A CN109003961 A CN 109003961A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The invention discloses a kind of 3D system integration structures, comprising: pinboard；It is arranged in positive first through silicon via of the pinboard；It is arranged in positive second through silicon via of the pinboard；The cavity of the switching back is set；The first of cavity floor placement-and-routing's layer and pad again be set, and described first placement-and-routing's layer and pad are electrically connected with first through silicon via again；Be arranged in the cavity the first chip, first chip be electrically connected to described first again placement-and-routing layer and pad；The plastic packaging filled layer in gap between the first chip surrounding, bottom and the pinboard is set；Second chip of the switching back is set, and second chip is electrically connected to second through silicon via；Setting is in the pinboard positive second again placement-and-routing layer；And be arranged in the positive welding structure of the pinboard, the welding structure be electrically connected to described second again placement-and-routing layer.
Description
Technical field
The present invention relates to integrated antenna package technical field more particularly to a kind of 3D system integration structure and its manufacturers
Method.
Background technique
Mobile device manufacturer derives the crystalline substance to related chip to the miniaturization of product, low cost and highly integrated demand
Cost, performance, the integrated level of system in package solution and the functional requirement of circle grade encapsulation.In system in package,
In order to realize the function of encapsulating structure, the heterogeneous chip of several classes or passive device are often related in an encapsulating structure.It is three-dimensional
Encapsulation technology has the combination advantage in plane and vertical space, is one preferable direction of system in package.
Three-dimensional packaging technology based on silicon switching plate technique, collection smaller with package dimension relative to conventional encapsulating structure
The features such as at Du Genggao, better reliability.The existing three-dimension packaging structure based on silicon switching plate technique is usually by different function
Chip level is distributed in the same surface of silicon pinboard, and Fig. 1 shows a kind of existing 2.5D/3D collection based on silicon switching plate technique
At encapsulating structure, as shown in Figure 1, two class functional chips 102 and 103 are mounted on the surface of silicon pinboard 101 respectively.This encapsulation
The integrated level of structure is not relatively high, requires the size of pinboard larger when integrated to cause packaging cost higher indirectly.
Therefore, it is badly in need of a kind of 3D system integration structure and its at least part of envelope of the promotion based on silicon pinboard of manufacturing method
The integrated level of assembling structure reduces package dimension.
Summary of the invention
It is relatively not high for the integrated level of the encapsulating structure existing in the prior art based on silicon pinboard, it is desirable that pinboard
Size it is larger to leading to the higher problem of packaging cost indirectly, according to one embodiment of present invention, provide a kind of 3D system
System integrated morphology, comprising:
Pinboard；
It is arranged in positive first through silicon via of the pinboard；
It is arranged in positive second through silicon via of the pinboard；
The cavity of the switching back is set；
The first of cavity floor placement-and-routing's layer and pad again be set, described first again placement-and-routing's layer and
Pad is electrically connected with first through silicon via；
Be arranged in the cavity the first chip, first chip be electrically connected to described first again placement-and-routing layer and
Pad；
The plastic packaging filled layer in gap between the first chip surrounding, bottom and the pinboard is set；
Second chip of the switching back is set, and second chip is electrically connected to second through silicon via；
Setting is in the pinboard positive second again placement-and-routing layer；And
It is arranged in the positive welding structure of the pinboard, the welding structure is electrically connected to described second and is laid out cloth again
Line layer.
In one embodiment of the invention, the depth of first through silicon via is less than second through silicon via.
In one embodiment of the invention, the top of first chip is arranged in second chip, and it is vertical to form 3D
Body structure.
In one embodiment of the invention, second chip is chip-packaging structure.
In one embodiment of the invention, described second again placement-and-routing's layer there are N layer to be routed, wherein N >=2.
In one embodiment of the invention, the 3D system integration structure further include setting second chip with it is described
Filled layer between back of transferring.
In one embodiment of the invention, which further includes being arranged to be laid out cloth again described second
Dielectric layer between the conducting wire of line layer.
According to another embodiment of the invention, a kind of manufacturing method of 3D system integration structure is provided, comprising:
The the first conductive through silicon via and the second conductive through silicon via of different depth are formed in the front of silicon pinboard；
Silicon pinboard front formed first again placement-and-routing layer and the first salient point, described first is laid out cloth again
Line layer is electrically connected with the described first conductive through silicon via and the second conductive through silicon via；
In the front bonding support plate for completing the silicon pinboard of the first salient point；
Cavity is formed in silicon switching back, realizes that the described first conductive through silicon via back side is appeared；
The cavity bottom surface formed second again placement-and-routing layer and pad；
Mount the first chip in the cavity, after first chip attachment with described second again placement-and-routing's layer and
Pad forms electrical connection；
Whole face plastic packaging, which is carried out, at the back side of the silicon pinboard forms plastic packaging layer；
The plastic packaging layer and the silicon pinboard is thinned, realizes that the described second conductive through silicon via back side is appeared；
The second salient point is formed, the salient point is electrically connected to the described second conductive through silicon via；
Second chip is soldered to second salient point；And
Remove the support plate.
In another embodiment of the present invention, the depth of the described first conductive through silicon via is less than the second conductive through silicon via
Depth.
In another embodiment of the present invention, this method further includes direct in second chip and the silicon pinboard
Fill bottom filler.
The present invention provides a kind of 3D system integration structure and its manufacturing method, using TSV First technology in silicon pinboard
Upper production different depth TSV through hole forms cavity structure, then the shape in pinboard cavity by etching technics on silicon pinboard
At embedment chip or integrated passive devices, other chips are finally mounted in vertical direction again.The three-dimension packaging structure, which increases, hangs down
Histogram to encapsulation integrated level, have the characteristics that encapsulation volume it is small, it is at low cost, interconnect short, high reliablity.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows a kind of diagrammatic cross-section for encapsulating structure based on silicon pinboard that the prior art of the invention provides.
Fig. 2 shows a kind of diagrammatic cross-sections of 3D system integration structure 200 according to an embodiment of the invention.
Fig. 3 A to Fig. 3 K, which is shown, to be formed the process of 3D system integration structure 200 a kind of according to one embodiment of present invention and cuts open
Face perspective view.
Fig. 4 shows the flow chart for forming a kind of 3D system integration structure 200 according to one embodiment of present invention.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
The present invention provides a kind of 3D system integration structure and its manufacturing method, is existed using preferential (TSV First) technology of TSV
Different depth TSV through hole is made on silicon pinboard, cavity structure is formed on silicon pinboard by etching technics, then in pinboard
Embedment chip or integrated passive devices are formed in cavity, finally mount other chips in vertical direction again.The three-dimension packaging knot
Structure increase vertical direction encapsulation integrated level, have the characteristics that encapsulation volume it is small, it is at low cost, interconnection short, high reliablity.
A kind of 3D system integration structure according to the present invention is described in detail below with reference to Fig. 2.Fig. 2 shows according to the present invention
One embodiment a kind of 3D system integration structure 200 diagrammatic cross-section.As shown in Fig. 2, the 3D system integration structure 200
It further comprise that pinboard 201, the first through silicon via 202, the second through silicon via 203, pinboard cavity 204, first are laid out cloth again
Line layer and pad 205, the first chip 206, plastic packaging filled layer 207, the second chip 208, the first welding structure 209, filled media
Layer 210, second placement-and-routing's layer 211, dielectric layer 212 and the second welding structure 213 again.
Pinboard 201 is the main component of 3D encapsulating structure, and through silicon via is formed in inside pinboard 201, functional chip
It is carried on pinboard.In one embodiment of the invention, pinboard 201 is silicon pinboard.In order to realize wafer-level packaging,
Pinboard 201 can be the wafer size general at present such as 300mm or 200mm.In another embodiment of the present invention, pinboard
201 can also be the pinboard of the other materials such as glass pinboard, ceramic pinboard.
First through silicon via 202 and the second through silicon via 203 are located at the same surface (front) of pinboard 201.One can be passed through
Secondary property makes to be formed, and independently can also make to be formed.In one particular embodiment of the present invention, by controlling the first silicon
The difference of through-hole 202 and the critical size (CD) of the second through silicon via 203 realizes the different etching rates of two class through-holes, to reach
To different via depths.In another embodiment of the present invention, other than the first through silicon via 202 and the second through silicon via 203,
Can also there are third, the 4th through silicon via (not shown), to realize more vertical packaging effects.
By forming switching in the corresponding position of the first through silicon via of pinboard 202 to the back-patterned etching of pinboard 201
Plate cavity 204, after pinboard cavity 204 is formed, the realization of the first through silicon via 202 is appeared.In one embodiment of the invention, may be used
Then to carry out the techniques shapes such as photoetching, etching to the back side of pinboard 201 by the way that 201 front of pinboard to be bonded on support plate
At.The size of pinboard cavity 204 needs to meet the size of subsequent embedment chip.
First again placement-and-routing's layer and pad 205 be formed in the bottom of pinboard cavity 204, the first placement-and-routing again
Layer and pad 205 are electrically connected with the formation of the first through silicon via 202.First can be formed by the techniques such as being electroplated, deposit to be laid out again
Wiring layer and pad 205.Optionally, dielectric layer is formed between placement-and-routing's layer and pad 205 again first (not show in figure
Out) to play electrical and mechanical protective effect.
First chip 206 is located in pinboard cavity 204, is electrically connected to the first weight by techniques such as attachment, welding, bondings
The corresponding position of new placement-and-routing's layer and pad 205.In one embodiment of the invention, the first chip 206 passes through flip chip bonding
Technique be bonded to first again placement-and-routing layer and pad 205 chip bonding pad on.In one embodiment of the invention, first
Chip 206 can be the functional chips such as processor, MCU, DSP, memory, IPD.
Plastic packaging filled layer 207 is arranged in the gap between the first chip 206 and pinboard cavity 204, plays to chip
Protective effect.In one embodiment of the invention, plastic packaging filled layer 207 be located at 206 surrounding of the first chip and bottom with
In gap between pinboard cavity 204；In another embodiment of the present invention, plastic packaging filled layer 207 is also covered in the first core
The top of piece 206.
The back side of pinboard 201 is arranged in second chip 208, passes through the first welding structure 209 and the second of pinboard 201
Through silicon via 203 forms electrical connection.In one embodiment of the invention, the second chip 208 can be single chip, can also be with
It is the chip of wafer scale to realize that wafer-level packaging, the first welding structure 209 are the convex blocks such as soldered ball, copper post；It is of the invention again
In one embodiment, the second chip 208 can also be packaged chip structure.In one embodiment of the invention,
Two chips 208 can be functional chips or the mould groups such as processor, MCU, DSP, memory, sensor.
Optionally, filled media layer 210, filled media layer 210 are provided between the second chip 208 and pinboard 201
Play the role of the electrical isolation and mechanical protection to encapsulating structure.In one embodiment of the invention, filled media layer 210 is bottom
Filler.
Second front that placement-and-routing's layer 211 is arranged in pinboard 201 again, according to the needs of design, the second cloth again
Office's wiring layer 211 can be one or more layers, wherein pad can be set in outermost layer.Second again placement-and-routing layer 211 with
First through silicon via 202, the second through silicon via 203 form electrical connection, thus realize the first chip 206, between the second chip 208 and/
Or electricity and/or signal connection between external IO.
Optionally, dielectric layer 212 can be formed between second again placement-and-routing's layer 211.
The front outermost layer of pinboard 201 is arranged in second welding structure 213, with the second 211 formation of placement-and-routing's layer again
Electrical connection, plays entire 3D system integration structure and external electricity and/or signal interconnection.
The process to form a kind of 3D system integration structure 200 is described in detail below with reference to Fig. 3 A to Fig. 3 K and Fig. 4.Figure
3A to Fig. 3 K shows the process section projection signal for forming a kind of 3D system integration structure 200 according to one embodiment of present invention
Figure；Fig. 4 shows the flow chart for forming a kind of 3D system integration structure 200 according to one embodiment of present invention.
Firstly, as shown in Figure 3A, forming the conductive through silicon via of different depth in the front of silicon pinboard 301 in step 401
(TSV).Specific formation process can by graphically etching, deposited seed layer, the techniques such as plating formed, for two classes difference
The TSV of depth is controlled, and can be made according to the different principle of different CD etch rates.In a specific embodiment of the invention
In, the first TSV 302 and the 2nd TSV 303 of two kinds of different depths are formed, wherein the depth and size of the 2nd TSV 303 are greater than
First TSV 302.
Next, in step 402, as shown in Figure 3B, the silicon pinboard where the first TSV 302 and the 2nd TSV 303
301 front forms first placement-and-routing's layer (RDL) 304 and the first salient point 305 again.Optionally in the first placement-and-routing again
The non-conductor area of layer (RDL) 304 forms dielectric layer 306, to play the role of insulation and mechanical protection.
Then, in step 403, as shown in Figure 3 C, in the front key for the silicon pinboard 301 for completing the production of the first salient point 305
Close support plate 307.Support plate 307 plays the supporting role of pinboard subsequent manufacturing procedures.Support plate 307 can be wafer or glass.
Next, as shown in Figure 3D, cavity 308 is graphically formed in 301 rear surface regions of silicon pinboard in step 404, it is real
It appears at the back side of existing first TSV 302.In one embodiment of the invention, cavity 308 can be by silicon pinboard 301
The back side carries out the techniques such as photoetching, etching and is formed.The size of cavity 308 needs to meet the size of subsequent embedment chip.
Then, in step 405, as shown in FIGURE 3 E, cavity 308 bottom surface formed second again placement-and-routing layer (RDL)
And pad 309.Second again placement-and-routing layer (RDL) and pad 309 be electrically connected with the first TSV 302.At of the invention one
In embodiment, pass through graphical electroplating technology formation second again placement-and-routing's layer (RDL) and pad 309；It is of the invention again
In one embodiment, pass through pattern sedimentation technique formation second again placement-and-routing's layer (RDL) and pad 309.In addition, optional
Dielectric layer 310 is formed in the non-conductor area of second placement-and-routing's layer (RDL) 309 again, is made with playing insulation and mechanical protection
With.
Next, as illustrated in Figure 3 F, the first chip 311, the first chip 311 patch are mounted in cavity 308 in step 406
Placement-and-routing's layer (RDL) and the formation of pad 309 are electrically connected again with second after dress.First chip 311 can for processor, MCU,
The functional chips such as DSP, memory, IPD.State in one embodiment of the invention has soldered ball or copper post on the first chip 311
Equal welding mechanisms 312, the first chip 311 is mounted by welding mechanism 312 to second be laid out cloth again by Flip Chip Bond Technique
On the correspondence pad of line layer (RDL) and pad 309.
Then, in step 407, as shown in Figure 3 G, whole face plastic packaging is carried out at the back side of silicon pinboard 301 and is formed to the first core
The plastic packaging protective layer 313 of piece 311.Plastic packaging protective layer 313 be wrapped in the first chip 311 surrounding, bottom and silicon pinboard 301 it
Between space, and be covered on the top of chip 311.
Next, as shown in figure 3h, the back side of plastic packaging protective layer 313 and silicon pinboard 301 being thinned in step 408, realizing
2nd TSV's 303 appears.In one embodiment of the invention, mechanical lapping, chemically mechanical polishing (CMP) technique can be passed through
It realizes and is thinned.
Then, in step 409, as shown in fig. 31, the second salient point 314 is formed.Second salient point 314 is formed in the 2nd TSV
303 exposure site is electrically connected with the 2nd TSV 303 formation.The second salient point 314 is copper post in one embodiment of the invention
Or tin ball.
Next, as shown in figure 3j, the second chip 315 is soldered to the second salient point 314 in step 410.Second chip
315 and first chip formed vertical three-dimensional encapsulating structure.
Finally, as shown in Fig. 3 K, removing the positive support plate 307 of silicon pinboard 301 in step 411, most red 3D envelope is formed
Assembling structure.
Optionally, further include being cut to the 3D encapsulating structure for completing wafer-level packaging, form the single 3D system integration
Structure.
This kind of 3D system integration structure and its manufacturing method are provided based on the present invention, is turned using TSV First technology in silicon
Different depth TSV through hole is made on fishplate bar, cavity structure is formed on silicon pinboard by etching technics, then in pinboard cavity
Interior formation embedment chip or integrated passive devices, finally mount other chips in vertical direction again.The three-dimension packaging structure increases
The encapsulation integrated level for adding vertical direction, have the characteristics that encapsulation volume it is small, it is at low cost, interconnect short, high reliablity.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. a kind of 3D system integration structure, comprising:
Pinboard；
It is arranged in positive first through silicon via of the pinboard；
It is arranged in positive second through silicon via of the pinboard；
The cavity of the switching back is set；
The first of cavity floor placement-and-routing's layer and pad again be set, the described first placement-and-routing's layer and pad again
It is electrically connected with first through silicon via；
First chip is set in the cavity, and first chip is electrically connected to the described first placement-and-routing's layer and weldering again
Disk；
The plastic packaging filled layer in gap between the first chip surrounding, bottom and the pinboard is set；
Second chip of the switching back is set, and second chip is electrically connected to second through silicon via；
Setting is in the pinboard positive second again placement-and-routing layer；And
It is arranged in the positive welding structure of the pinboard, the welding structure is electrically connected to the described second placement-and-routing again
Layer.
2. 3D system integration structure as described in claim 1, which is characterized in that the depth of first through silicon via is less than described
Second through silicon via.
3. 3D system integration structure as described in claim 1, which is characterized in that second chip is arranged in first core
The top of piece forms 3D stereochemical structure.
4. 3D system integration structure as described in claim 1, which is characterized in that second chip is chip-packaging structure.
5. 3D system integration structure as described in claim 1, which is characterized in that described second again placement-and-routing layer have N
Layer is routed, wherein N >=2.
6. 3D system integration structure as described in claim 1, which is characterized in that further include being arranged in second chip and institute
State the filled layer between switching back.
7. 3D system integration structure as described in claim 1, which is characterized in that further include that setting is laid out again described second
Dielectric layer between the conducting wire of wiring layer.
8. a kind of manufacturing method of 3D system integration structure, comprising:
The the first conductive through silicon via and the second conductive through silicon via of different depth are formed in the front of silicon pinboard；
Silicon pinboard front formed first again placement-and-routing layer and the first salient point, described first again placement-and-routing layer
It is electrically connected with the described first conductive through silicon via and the second conductive through silicon via；
In the front bonding support plate for completing the silicon pinboard of the first salient point；
Cavity is formed in silicon switching back, realizes that the described first conductive through silicon via back side is appeared；
The cavity bottom surface formed second again placement-and-routing layer and pad；
Mount the first chip in the cavity, after first chip attachment with the described second placement-and-routing's layer and pad again
Form electrical connection；
Whole face plastic packaging, which is carried out, at the back side of the silicon pinboard forms plastic packaging layer；
The plastic packaging layer and the silicon pinboard is thinned, realizes that the described second conductive through silicon via back side is appeared；
The second salient point is formed, the salient point is electrically connected to the described second conductive through silicon via；
Second chip is soldered to second salient point；And
Remove the support plate.
9. method according to claim 8, which is characterized in that the depth of the described first conductive through silicon via is less than the second conductive silicon
The depth of through-hole.
10. method according to claim 8, which is characterized in that further include straight in second chip and the silicon pinboard
Connect filling bottom filler.
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| CN109945852A (en) * | 2019-03-22 | 2019-06-28 | 中国科学院微电子研究所 | The encapsulating structure and production method of gyroscope |
| CN110010548A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of cavity structure production method of bottom belt pad |
| CN111293078A (en) * | 2020-03-17 | 2020-06-16 | 浙江大学 | Method for embedding chips into cavities on front and back surfaces of adapter plate |
| CN111968942A (en) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | Interconnecting process for interconnecting radio frequency modules on side walls of adapter plates |
| CN112331635A (en) * | 2020-11-04 | 2021-02-05 | 中国科学院微电子研究所 | Vertical packaging structure and packaging method based on adapter plate |
| WO2022067804A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | Three-dimensional integrated circuit and method for fabrication thereof and electronic device |
| WO2022161249A1 (en) * | 2021-01-29 | 2022-08-04 | 中芯集成电路（宁波）有限公司 | Wafer-level packaging structure and manufacturing method therefor |
| CN115312496A (en) * | 2022-07-12 | 2022-11-08 | 武汉大学 | Three-dimensional semiconductor integrated packaging structure and process based on rear through hole technology |
| CN117476550A (en) * | 2023-12-26 | 2024-01-30 | 季华实验室 | System-level fan-out type packaging method and packaging structure |
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