CN111293078A - Method for embedding chips into cavities on front and back surfaces of adapter plate - Google Patents
Method for embedding chips into cavities on front and back surfaces of adapter plate Download PDFInfo
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- CN111293078A CN111293078A CN202010186930.6A CN202010186930A CN111293078A CN 111293078 A CN111293078 A CN 111293078A CN 202010186930 A CN202010186930 A CN 202010186930A CN 111293078 A CN111293078 A CN 111293078A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
Abstract
The invention discloses a method for embedding chips into cavities on the front side and the back side of an adapter plate, which comprises the following steps: the adapter plate is made of a silicon wafer with double SOI layers, a silicon through hole is manufactured, the silicon through hole penetrates through the first layer of SOI layer and stops on the second layer of SOI layer, the silicon wafer with the silicon through hole is obtained, then metal is electroplated to fill the silicon through hole, and the silicon wafer with the metal is obtained; then etching a groove on the opening surface of the silicon through hole, etching the metal column in the groove, and forming a cavity on the front side and the back side to obtain the adapter plate with the groove on the double sides; embedding a chip with soldering tin, then manufacturing an RDL interconnection layer on the surface, continuously etching a second SOI layer to expose one end of a metal column in the filled silicon through hole, embedding the chip with the soldering tin ball, solidifying the filled colloid, and removing the surface colloid. According to the invention, the adapter plate is manufactured, the front surface and the back surface of the adapter plate are both provided with the grooves, and then the chips are embedded into the grooves, so that the purpose of embedding the chips into the front surface and the back surface of the adapter plate is realized.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a method for embedding chips into cavities on the front side and the back side of an adapter plate.
Background
The millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection and imaging and the like, is expected to reach 11 billion dollars in market in 2018, and becomes a new industry. The new application puts new requirements on the electrical performance, compact structure and system reliability of the product, and the wireless transmitting and receiving system cannot be integrated on the same chip (SOC) at present, so that different chips including a radio frequency unit, a filter, a power amplifier and the like need to be integrated into a separate system to realize the functions of transmitting and receiving signals.
In the traditional packaging process, various functional chips and passive devices are mounted on a substrate, so that the occupied area is large, the reliability is poor, and the trend of more and more miniaturization of a packaging system cannot be met, while the three-dimensional heterogeneous packaging technology (system-in-package SIP) based on the standard Silicon process integrates chips with different functions on different substrates by using a TSV (Through Silicon Via) technology and a cavity structure, so that the stacking and interconnection of the chips can be realized in a smaller area, the area of the functional devices is greatly reduced, the reliability of the functional devices is improved, and the packaging process is more and more in the direction of future development of the industry.
The bottom of the radio frequency chip needs to be subjected to heat dissipation and grounding interconnection, so that the bottom of the chip needs to be contacted with a TSV copper column, and particularly for a structure with a solder ball at the bottom of the chip, a corresponding bonding pad needs to be used for welding. In addition, for the interposer with the double-layer chip structure, generally, the double-layer interposer needs to be manufactured, then different chips are embedded into each layer of interposer, and then wafer-level bonding is performed on the interposer, so that the process is complex and the cost is high.
Disclosure of Invention
The invention provides a method for embedding chips into cavities on the front side and the back side of an adapter plate.
A method for embedding chips into cavities on the front side and the back side of an adapter plate comprises the following steps:
a: the method comprises the following steps that a Silicon wafer with a double SOI (Silicon-On-Insulator) layer is adopted for an adapter plate, the double SOI layer is a first SOI layer and a second SOI layer from the top to the bottom of the adapter plate, a Through Silicon Via (TSV) is manufactured from the top of the adapter plate to the bottom of the adapter plate, penetrates through the first SOI layer and stops On the second SOI layer, the Silicon wafer with the through Silicon via is obtained, and then the Through Silicon Via (TSV) is electroplated and filled with metal, so that the Silicon wafer filled with metal is obtained;
b: forming a groove at the bottom of the silicon wafer filled with the metal, etching the groove on the opening surface of the silicon through hole, corroding the metal column in the groove, and forming a cavity on the front surface and the back surface to obtain the adapter plate with the grooves on the two surfaces;
c: embedding the chip that has soldering tin in the top recess of the keysets of double-sided area recess, then make RDL interconnection layer on this surface, continue to etch the second SOI layer at the bottom recess of the keysets of double-sided area recess, make metal column one end in the packing silicon through-hole expose, the recess of keysets bottom is embedded into to the chip that has the soldering tin ball, later pack the colloid solidification in the gap of top recess and bottom recess, get rid of the surface colloid, the keysets that has the chip is inlayed to the two-sided, accomplish the front and back two sides cavity embedding chip of keysets.
In the step (A), the through silicon via is manufactured by photoetching and etching processes. The diameter range of the Through Silicon Via (TSV) is 1um to 1000um, and the depth is 10um to 1000 um;
the electroplated metal-filled Through Silicon Via (TSV) specifically comprises:
(1) depositing an insulating layer above a silicon wafer with a silicon through hole, or directly thermally oxidizing to form the insulating layer, and manufacturing a seed layer above the insulating layer;
(2) electroplating copper to fill the through silicon via with copper metal, densifying at 200-500 ℃ to make the copper more dense, and removing the copper on the surface of the silicon wafer by a copper Chemical Mechanical Polishing (CMP) process to only leave the copper in the through silicon via on the silicon wafer, wherein the insulating layer on the surface of the silicon wafer can be removed or retained;
in the step (1), the insulating layer is silicon oxide or silicon nitride and the like, and the thickness of the insulating layer ranges from 10nm to 100 um;
a seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
In the step (2), the insulating layer on the surface of the silicon wafer can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
in the step B, forming a groove at the bottom of the silicon wafer after the metal filling, and the method comprises the following steps:
carrying out dry etching on the thinned surface to form a cavity at the bottom of the silicon chip filled with the metal by using photoetching and dry etching processes, or forming the cavity in a wet etching mode, wherein the etching of the cavity is stopped at the second SOI layer, and a groove is formed at the bottom:
the depth range of the cavity is 100nm to 700um, the shape of the cavity can be square, round, oval, triangular and the like, and the side wall of the cavity can be vertical or inclined;
and step B, etching a groove on the opening surface of the silicon through hole by adopting a photoetching and dry etching process or a wet etching mode, wherein the depth range of the cavity is 100nm to 700um, the cavity can be square, circular, oval, triangular and the like, the side wall of the cavity can be vertical or inclined, and the etching is stopped on the first SOI layer.
In the step B, corroding the metal column in the groove, and adopting a wet etching process, wherein wet etching liquid adopted by the wet etching process comprises one or more of chemical substances such as hydrofluoric acid, phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, ammonia water, hydrogen peroxide and the like, and the mass concentration range of the wet etching liquid is 1-90%; after the etching is finished, all the metal columns in the cavity are removed, and only one end of the bottom of the cavity is exposed for mutual connection.
Another method for embedding chips into cavities on the front side and the back side of an adapter plate comprises the following steps:
a: the method comprises the following steps that a Silicon wafer with double SOI (Silicon-On-Insulator) layers is adopted for an adapter plate, the double SOI layers are a first SOI layer and a second SOI layer from the top to the bottom of the adapter plate, Through Silicon Vias (TSV) are manufactured from the top of the adapter plate to the bottom of the adapter plate and penetrate through the first SOI layer and the second SOI layer to obtain the Silicon wafer with the through Silicon vias, and then the Through Silicon Vias (TSV) are electroplated and filled with metal to obtain the Silicon wafer filled with metal;
b: forming grooves at the top and the bottom of the silicon wafer after metal filling, wherein the depth of the top groove is stopped on a first SOI layer, the depth of the bottom groove is stopped on a second SOI layer, then corroding metal columns in the top groove and the bottom groove, and forming cavities on the front side and the back side to obtain the adapter plate with grooves on the double sides;
c: all imbed the chip that has soldering tin in the top recess of the keysets of double-sided area recess and bottom recess, then at this surperficial preparation RDL interconnection layer (rewiring layer), later at the solidification of the intussuseption colloid in the gap of top recess and bottom recess, get rid of the surface colloid, obtain the keysets that the chip was inlayed to the double-sided, accomplish the keysets positive and negative both sides cavity embedding chip.
In the step (A), the through silicon via is manufactured by photoetching and etching processes. The diameter range of the Through Silicon Via (TSV) is 1um to 1000um, and the depth is 10um to 1000 um;
the electroplated metal-filled Through Silicon Via (TSV) specifically comprises:
(1) depositing an insulating layer above a silicon wafer with a silicon through hole, or directly thermally oxidizing to form the insulating layer, and manufacturing a seed layer above the insulating layer;
(2) electroplating copper to fill the through silicon via with copper metal, densifying at 200-500 ℃ to make the copper more dense, and removing the copper on the surface of the silicon wafer by a copper Chemical Mechanical Polishing (CMP) process to only leave the copper in the through silicon via on the silicon wafer, wherein the insulating layer on the surface of the silicon wafer can be removed or retained;
in the step (1), the insulating layer is silicon oxide or silicon nitride and the like, and the thickness of the insulating layer ranges from 10nm to 100 um;
a seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
In the step (2), the insulating layer on the surface of the silicon wafer can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
and in the step B, grooves are formed in the top and the bottom of the silicon wafer after the metal filling by adopting a photoetching and dry etching process or a wet etching mode, the depth range of the cavity is 100nm to 700um, the cavity can be square, circular, oval, triangular and the like, and the side wall of the cavity can be vertical or inclined.
In the step B, corroding the metal columns in the top groove and the bottom groove, and adopting a wet etching process, wherein wet etching liquid adopted by the wet etching process comprises one or more of chemical substances such as hydrofluoric acid, phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, ammonia water, hydrogen peroxide and the like, and the mass concentration range of the wet etching liquid is 1-90%; after the etching is finished, all the metal columns in the cavity are removed, and only one end of the groove exposed is left for mutual connection.
Compared with the prior art, the invention has the following advantages:
according to the method for embedding the chips into the cavities on the front side and the back side of the adapter plate, the adapter plate is manufactured, the front side and the back side of the adapter plate are both provided with the grooves, and then the chips are embedded into the grooves, so that the purpose of embedding the chips on the front side and the back side of the adapter plate is achieved, the cost advantage is high, the economic benefit is high, the marketization popularization is facilitated, and the application prospect is wide.
Drawings
FIG. 1 is a schematic structural view of a silicon wafer having a double-layer SOI layer according to embodiment 1 of the present invention;
FIG. 2 is a schematic structural diagram of a TSV hole formed in the surface of an SOI wafer in embodiment 1 of the present invention;
FIG. 3 is a schematic structural diagram of a metal-filled TSV structure plated in accordance with example 1 of the present invention;
fig. 4 is a schematic structural view of a TSV silicon wafer bottom groove in embodiment 1 of the present invention;
FIG. 5 is a schematic structural diagram of a cavity formed by dry etching on a TSV opening surface by using photolithography and dry etching processes in embodiment 1 of the present invention;
fig. 6 is a schematic structural diagram of a chip with solder embedded in a groove on one side of a TSV opening in embodiment 1 of the present invention;
fig. 7 is a schematic structural diagram illustrating a structure in which a second SOI layer is etched to expose and locate one end of a TSV copper pillar in embodiment 1 of the present invention;
FIG. 8 is a schematic structural diagram of a chip 106 with solder balls embedded in a groove on the back surface of an interposer according to embodiment 1 of the present invention;
fig. 9 is a schematic structural diagram of curing by filling a colloid in a gap between cavities on two sides of an interposer in embodiment 1 of the present invention;
fig. 10 is a schematic structural view of an interposer with chips embedded on both sides obtained by removing surface colloids in embodiment 1 of the present invention;
fig. 11 is a schematic structural diagram of a chip with solder embedded in a top groove of an interposer with grooves on both sides in embodiment 2 of the present invention;
fig. 12 is a schematic structural view of a chip with solder embedded in a bottom groove of an interposer with grooves on both sides in embodiment 2 of the present invention;
fig. 13 is a schematic structural diagram of curing by filling a colloid in a gap between cavities on two sides of an interposer in embodiment 2 of the present invention;
fig. 14 is a schematic structural diagram of an interposer with chips embedded on both sides obtained by removing surface colloids in embodiment 2 of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments described in the present invention, and that other drawings can be obtained from these drawings by a person skilled in the art without inventive effort.
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely for simplicity and clarity of describing the present invention, and are not intended to represent any correlation between the various embodiments and/or structures discussed.
Reference numerals in the various embodiments of the invention with respect to steps are merely for convenience of description and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention introduces a chip embedding process in a cavity, which comprises the following steps:
example 1
The method comprises the following steps:
a: manufacturing a TSV (through Silicon via) On a Silicon wafer with a double-layer SOI (Silicon-On-Insulator, Silicon On an insulating substrate) layer, stopping the TSV On the surface of the second layer SOI, and filling the TSV with electroplating metal;
as shown in fig. 1, an SOI silicon wafer 101 is selected, wherein 102 is an SOI layer, the silicon wafer has two layers of SOI, from top to bottom, a first SOI layer 102 and a second SOI layer;
as shown in fig. 2, a TSV hole 103 is formed on the surface of the SOI wafer through photolithography and etching processes, wherein the diameter of the TSV hole ranges from 1um to 1000um, and the depth of the TSV hole ranges from 10um to 1000 um;
etching and stopping on the second SOI layer;
as shown in fig. 3, an insulating layer of silicon oxide or silicon nitride is deposited over the silicon wafer, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper to fill the TSV with copper metal, and densifying at 200-500 ℃ to make the copper more dense; removing copper on the surface of the silicon wafer by a copper CMP (chemical mechanical Polishing) process, so that only copper filling is left on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
b: forming a groove at the bottom of the TSV silicon wafer, etching the groove on the open face of the TSV, and corroding a metal column in the groove to obtain a double-sided adapter plate structure with the groove;
as shown in fig. 4, the other side of the thinned silicon wafer is subjected to dry etching on the thinned side by using photolithography and dry etching processes to form a cavity 104, wherein the cavity with a special morphology can also be subjected to wet etching; the depth range of the cavity is between 100nm and 700um, the shape can be square, round, oval, triangular and the like, the side wall can be vertical or inclined, and the etching is stopped on the SOI (namely the second SOI layer);
as shown in fig. 5, a cavity 105 is formed on the TSV opening surface by dry etching using photolithography and dry etching processes, and a wet etching method may be used for the cavity with a special morphology; the depth range of the cavity is between 100nm and 700um, the shape can be square, round, oval, triangular and the like, the side wall can be vertical or inclined, and the etching is stopped on the SOI (namely the first SOI layer 102);
as shown in fig. 6, the TSV copper pillar in the cavity is etched by a wet etching process, where the wet etching solution includes one or more of chemical substances such as hydrofluoric acid, phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, ammonia water, and hydrogen peroxide, and the concentration of the chemical substances is in a range from 1% to 90%; after the etching is finished, all the metal columns in the cavity are removed, and only one end of the bottom of the cavity is exposed for mutual connection.
C: embedding a chip with soldering tin into the groove on one surface of the TSV opening, and continuously etching the back oxide layer to expose one end of the TSV copper column;
as shown in fig. 6, a chip 106 with solder is embedded in a groove on one side of the TSV opening, and then an RDL interconnection layer is formed on the surface;
as shown in fig. 7, the back oxide layer (i.e., the second SOI layer) is continuously etched, so that one end of the TSV copper pillar is exposed;
d: embedding a chip with solder balls into a groove on the back surface of the adapter plate, filling colloid in gaps of cavities on two surfaces of the adapter plate for solidification, and removing the surface colloid to obtain an adapter plate structure with the chips embedded on two surfaces;
as shown in fig. 8, the chip 106 with solder balls is embedded into the groove on the back surface of the interposer, as shown in fig. 9, the gap between the cavities on both sides of the interposer is filled with glue for curing, as shown in fig. 10, the glue on the surface is removed to obtain the interposer structure with the chips embedded on both sides;
example 2
The method comprises the following steps:
a: manufacturing TSV on a silicon wafer with a double-layer SOI layer, stopping the TSV on the surface of the second layer SOI layer, continuously etching the TSV to the lower surface of the SOI layer, and electroplating metal to fill the TSV;
as shown in fig. 11, an SOI silicon wafer is selected, and the silicon wafer has two layers of SOI; through photoetching and etching processes, TSV holes are formed in the surface of the SOI silicon wafer, the diameter range of the holes is 1um to 1000um, and the depth ranges from 10um to 1000 um;
etching the TSV, stopping on the surface of the second layer of SOI, and continuously etching the TSV to the lower surface of the SOI;
depositing an insulating layer of silicon oxide or silicon nitride and the like above the silicon chip, or directly carrying out thermal oxidation, wherein the thickness of the insulating layer is between 10nm and 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper to fill the TSV with copper metal, and densifying at 200-500 ℃ to make the copper more dense; removing copper on the surface of the silicon wafer by a copper CMP process, and only filling copper on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
b: forming a groove at the bottom of the TSV silicon wafer, and etching to stop on the surface of the bottom SOI so as to expose the bottom end of the copper column;
as shown in fig. 11, the other surface of the thinned silicon wafer is subjected to dry etching to form a cavity on the thinned surface by using photolithography and dry etching processes, wherein the cavity with a special morphology can also be subjected to wet etching; the depth range of the cavity is between 100nm and 700um, the shape can be square, round, oval, triangular and the like, the side wall can be vertical or slope, and etching is stopped on the SOI to expose the bottom end of the copper column;
c: then, etching a groove on the TSV opening surface, and corroding the metal column in the groove to obtain a double-sided adapter plate structure with the groove;
as shown in fig. 11, a cavity is formed on the TSV opening surface by dry etching using photolithography and dry etching processes, and a wet etching method can be used for the cavity with a special morphology; the depth range of the cavity is between 100nm and 700um, the shape can be square, round, oval, triangular and the like, the side wall can be vertical or inclined, and the etching is stopped on the SOI;
corroding the TSV copper column in the cavity by using a wet etching process, wherein wet etching liquid comprises one or more of chemical substances such as hydrofluoric acid, phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, ammonia water, hydrogen peroxide and the like, and the concentration range of the wet etching liquid is 1-90%; after the etching is finished, all the metal columns in the cavity are removed, and only one end of the bottom of the cavity is exposed for mutual connection.
D: embedding a chip with soldering tin into a groove on one side of the TSV opening, embedding the chip with the soldering tin into a groove on the back side of the adapter plate, filling colloid in gaps of cavities on two sides of the adapter plate for solidification, and removing the surface colloid to obtain an adapter plate structure with the chips embedded on two sides;
as shown in fig. 12, a chip with solder is embedded in the groove on one side of the TSV opening; embedding a chip with soldering tin into the groove on the back of the adapter plate;
as shown in fig. 13, the gaps of the cavities on both sides of the adapter plate are filled with glue for curing;
as shown in fig. 14, the surface colloid is removed to obtain an interposer structure with chips embedded on both sides;
it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A method for embedding chips into cavities on the front side and the back side of an adapter plate is characterized by comprising the following steps:
a: the adapter plate adopts a silicon wafer with double SOI layers, the double SOI layers are a first layer SOI layer and a second layer SOI layer from the top to the bottom of the adapter plate, a silicon through hole is manufactured from the top of the adapter plate to the bottom of the adapter plate, the silicon through hole penetrates through the first layer SOI layer and stops on the second layer SOI layer to obtain the silicon wafer with the silicon through hole, and then the silicon through hole is electroplated and metal-filled to obtain the silicon wafer with metal filling;
b: forming a groove at the bottom of the silicon wafer filled with the metal, etching the groove on the opening surface of the silicon through hole, corroding the metal column in the groove, and forming a cavity on the front surface and the back surface to obtain the adapter plate with the grooves on the two surfaces;
c: embedding the chip that has soldering tin in the top recess of the keysets of double-sided area recess, then make RDL interconnection layer on this surface, continue to etch the second SOI layer at the bottom recess of the keysets of double-sided area recess, make metal column one end in the packing silicon through-hole expose, the recess of keysets bottom is embedded into to the chip that has the soldering tin ball, later pack the colloid solidification in the gap of top recess and bottom recess, get rid of the surface colloid, the keysets that has the chip is inlayed to the two-sided, accomplish the front and back two sides cavity embedding chip of keysets.
2. The method for embedding chips into cavities on both sides of an interposer as claimed in claim 1, wherein in step A, the through-silicon-via is fabricated by photolithography and etching.
3. The method of claim 2, wherein the through-silicon-via has a hole diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000 um.
4. The method for embedding chips into cavities on both sides of an interposer as claimed in claim 1, wherein in step a, the step of filling the through-silicon-via with plated metal comprises:
(1) depositing an insulating layer above a silicon wafer with a silicon through hole, or directly thermally oxidizing to form the insulating layer, and manufacturing a seed layer above the insulating layer;
(2) and (3) electroplating copper to fill the through silicon holes with copper metal, densifying at the temperature of 200-500 ℃ to make the copper more compact, removing the copper on the surface of the silicon wafer by using a copper chemical mechanical polishing process to make the silicon wafer only have the copper in the through silicon holes, and then removing or retaining the insulating layer on the surface of the silicon wafer.
5. The method according to claim 4, wherein in step (1), the insulating layer is silicon oxide or silicon nitride, and the thickness of the insulating layer is in the range of 10nm to 100 μm.
6. The method for embedding chips into cavities on the front side and the back side of an interposer as claimed in claim 4, wherein in step (1), a seed layer is formed on the insulating layer by physical sputtering, magnetron sputtering or evaporation, the thickness of the seed layer is in the range of 1nm to 100 μm, and the metal material of the seed layer is one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
7. The method of claim 1, wherein the step B of forming a recess in the bottom of the metal-filled silicon wafer comprises:
and carrying out dry etching on the thinning surface to form a cavity at the bottom of the silicon chip filled with the metal by using photoetching and dry etching processes, or forming the cavity in a wet etching mode, wherein the etching of the cavity is stopped at the second SOI layer, the depth range of the cavity is 100nm to 700um, and a groove is formed at the bottom.
8. The method for embedding chips into cavities on the front side and the back side of the interposer as claimed in claim 1, wherein in step B, the grooves are etched on the open side of the through-silicon via by photolithography and dry etching or wet etching, and the depth of the cavity is in the range of 100nm to 700 μm.
9. The method according to claim 1, wherein in step B, the metal posts in the grooves are etched by a wet etching process using a wet etching solution comprising one or more of hydrofluoric acid, phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, ammonia water, and hydrogen peroxide.
10. A method for embedding chips into cavities on the front side and the back side of an adapter plate is characterized by comprising the following steps:
a: the adapter plate adopts a silicon wafer with double SOI layers, the double SOI layers are a first layer SOI layer and a second layer SOI layer from the top to the bottom of the adapter plate, a silicon through hole is manufactured from the top of the adapter plate to the bottom of the adapter plate and penetrates through the first layer SOI layer and the second layer SOI layer to obtain the silicon wafer with the silicon through hole, and then the silicon through hole is electroplated and metal-filled to obtain the silicon wafer after metal filling;
b: forming grooves at the top and the bottom of the silicon wafer after metal filling, wherein the depth of the top groove is stopped on a first SOI layer, the depth of the bottom groove is stopped on a second SOI layer, then corroding metal columns in the top groove and the bottom groove, and forming cavities on the front side and the back side to obtain the adapter plate with grooves on the double sides;
c: all imbed the chip that has soldering tin in the top recess of the keysets of double-sided area recess and bottom recess, then at this surperficial preparation RDL interconnection layer, later pack the colloid solidification in the gap of top recess and bottom recess, get rid of the surface colloid, obtain the keysets that the chip was inlayed to the double-sided, accomplish the front and back both sides cavity embedding chip of keysets.
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