CN111968921B - PCB assembly mode with liquid heat dissipation function - Google Patents
PCB assembly mode with liquid heat dissipation function Download PDFInfo
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- CN111968921B CN111968921B CN202010855826.1A CN202010855826A CN111968921B CN 111968921 B CN111968921 B CN 111968921B CN 202010855826 A CN202010855826 A CN 202010855826A CN 111968921 B CN111968921 B CN 111968921B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to the technical field of semiconductors, in particular to a PCB assembly mode with a liquid heat dissipation function, which comprises the following steps: manufacturing a TSV, an RDL and a bonding pad on the front side of a silicon wafer, etching a cavity on the front side, performing temporary bonding, and thinning the back side of the silicon wafer to expose the TSV; manufacturing an RDL and a bonding pad on the back surface of a silicon wafer, etching a back cavity, embedding an intermediate radiator between the two cavities, embedding chips in the cavities on the two sides, and manufacturing the RDL and the bonding pad on the outer surface of each chip; and an outer layer radiator communicated with a liquid inlet of the intermediate radiator is welded on the outer layer of the chip, an outer layer chip is welded outside the outer layer radiator, the outer layer chip is interconnected with a surface bonding pad of the chip through a BGA (ball grid array) solder ball, and then the bottom of the outer layer chip is interconnected with the outer layer radiator to form a final structure. According to the invention, the upper surface and the lower surface of the power chip are simultaneously added with the liquid cooling micro-channel for heat dissipation, and meanwhile, other chips are welded on the two surfaces of the PCB, so that the integration level of the module is increased, and the use area of the PCB is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a PCB (printed circuit board) assembling mode with a liquid heat dissipation function.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
However, for a high-frequency micro-system, the area of the antenna array is smaller and smaller, and the distance between the antennas needs to be kept within a certain range, so that the whole module has excellent communication capability. However, for an analog device chip such as a radio frequency chip, the area of the analog device chip cannot be reduced by the same magnification as that of a digital chip, so that a radio frequency micro system with a very high frequency will not have enough area to simultaneously place a PA/LNA (power amplifier/low noise amplifier), and the PA/LNA needs to be stacked or vertically placed.
Therefore, the heat dissipation structure needs to adopt a more advanced liquid cooling or phase change refrigeration process, a metal processing mode is generally used as a base of the radio frequency module, a micro-flow channel is arranged in the base, and the module is fixed on the metal base by adopting a welding process to complete the placement of the chip. However, in the stacking technology, the heat on the power chip needs to be transferred to the heat dissipation liquid through several layers of media, and the efficiency is low.
In order to further reduce the distance between the heat dissipation micro-channel and the heat generating chip, the current trend is to directly weld the micro-channel radiator below the chip, so that the heat of the chip can be directly transferred into the micro-channel, and the heat dissipation capability of the system is increased. However, for a multilayer module, the upper chip still cannot contact the micro-channel, or only can perform liquid circulation through the micro-channel of the module, and compared with the direct heat dissipation of the micro-channel radiator at the bottom, the heat dissipation efficiency is large in difference, so that the working temperatures of the upper chip and the lower chip are inconsistent for a long time, and the reliability problem is caused.
Disclosure of Invention
The invention aims to solve the problems and provides a PCB assembly mode with a liquid heat dissipation function, which has a good heat dissipation effect and is suitable for a multilayer module.
According to the technical scheme of the invention, the PCB assembly mode with the liquid heat dissipation function comprises the following steps:
A. manufacturing a TSV (through silicon via), an RDL (redistribution layer) and a bonding pad on the front side of a silicon wafer, etching a cavity on the front side, performing temporary bonding, thinning the back side of the silicon wafer to expose the TSV, covering a passivation layer, and polishing to expose metal of the TSV;
B. manufacturing an RDL and a bonding pad on the back surface of a silicon wafer, etching a back cavity, etching to penetrate through the silicon wafer to enable the front cavity to be communicated with the back cavity, embedding an intermediate radiator with a micro-channel and a liquid inlet between the front cavity and the back cavity, embedding chips in the front cavity and the back cavity respectively, filling gaps between the chips and the silicon wafer, and manufacturing the RDL and the bonding pad on the outer surface of the chip;
C. an outer layer radiator with a micro-channel and a liquid inlet is welded on the outer layer of the chip, the liquid inlet of the outer layer radiator is communicated with the liquid inlet of the middle radiator, then an outer layer chip is welded outside the outer layer radiator in a chip mounting mode, the outer layer chip and a bonding pad on the surface of the chip are interconnected through BGA (ball grid array) welding balls, and then the bottom of the outer layer chip is interconnected with the outer layer radiator to form a final structure.
Further, the specific steps of the step a are as follows:
a1, manufacturing TSVs with different depths on the front side of the silicon wafer, manufacturing an insulating layer on the front side of the silicon wafer, manufacturing a seed layer on the insulating layer, electroplating copper to enable the TSVs to be filled with copper, removing the copper on the surface of the silicon wafer, and enabling the surface of the silicon wafer to be only filled with copper;
a2, manufacturing an RDL and a bonding pad on the front side of the silicon wafer through photoetching and electroplating processes;
a3, etching a front cavity on the front surface of the silicon wafer through photoetching and dry etching processes;
and A4, performing temporary bonding, thinning the reverse side of the silicon wafer to expose the bottom of the TSV, then manufacturing an insulating layer on the reverse side of the silicon wafer, and exposing the metal at the bottom of the TSV through a polishing process.
Further, the insulating layer on the surface of the silicon wafer is removed continuously after the copper on the surface of the silicon wafer is removed in the step A3.
Further, the specific steps of the step B are as follows:
b1, manufacturing an insulating layer on the reverse side of the silicon wafer, and manufacturing a seed layer on the insulating layer;
b2, photoetching and defining the RDL and the pad position on the reverse side of the silicon chip, and electroplating to obtain the RDL and pad metal;
b3, etching a back cavity on the back surface of the silicon wafer through photoetching and dry etching processes, continuously coating photoresist on the bottom of the back cavity and the back surface of the silicon wafer, exposing and opening the photoresist on the bottom of the back cavity, and etching by a dry method to penetrate through the bottom of the front cavity so as to enable the front cavity to be communicated with the back cavity;
b4, embedding an intermediate radiator with a micro-channel and a liquid inlet between the front cavity and the back cavity;
b5, embedding chips in the front cavity and the back cavity respectively, and filling the gap between the chips and the silicon wafer in a glue spraying or spin coating mode;
and B6, forming RDL and bonding pads on the outer surface of the chip through photoetching and electroplating processes.
The invention has the beneficial effects that: through two sides increase liquid cooling microchannel heat dissipation simultaneously about power chip, at other chips of PCB board both sides welding simultaneously, increased the integrated level of module, reduced PCB board usable floor area.
Drawings
FIG. 1a is a schematic view of the communication between the front cavity and the back cavity of the present invention.
Fig. 1b is a schematic view of the intermediate heat sink embedded in fig. 1 a.
FIG. 1c is a schematic diagram of the embedded chip based on FIG. 1 b.
FIG. 1d is a schematic view of the outer heat sink welded to the heat sink of FIG. 1 c.
FIG. 1e is a schematic view of the outer chip bonded on the basis of FIG. 1 c.
Description of reference numerals: 101-silicon chip, 102-front cavity, 103-back cavity, 104-intermediate heat sink, 105-chip, 106-outer heat sink, and 107-outer chip.
Detailed Description
The invention is further illustrated by the following examples and figures.
A PCB assembly mode with liquid heat dissipation function comprises the following steps:
A. manufacturing a TSV, an RDL and a bonding pad on the front side of a silicon wafer 101, etching a front side cavity 102, performing temporary bonding, thinning the back side of the silicon wafer 101 to expose the TSV, covering a passivation layer, and polishing to expose TSV metal;
as shown in fig. 1a, through photolithography and etching processes, TSV deep holes with different depths are formed in the front surface of a silicon wafer 101, wherein the diameter of the deep hole ranges from 1um to 1000um, and the depth ranges from 10um to 1000 um;
depositing insulating layers such as silicon oxide or silicon nitride on the front surface of the silicon chip, or directly thermally oxidizing to form the insulating layers, wherein the thickness of the insulating layers ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the seed layer can be made of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper to fill the TSV with copper, and densifying at 200-500 ℃ to make the copper more dense; removing copper on the surface of the silicon wafer by a copper CMP (chemical mechanical polishing) process, so that only copper filling is left on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
manufacturing an RDL and a bonding pad at the exposed end of the TSV opening through photoetching and electroplating processes, firstly manufacturing a seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation plating processes, wherein the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then, defining the RDL and the position of a bonding pad by photoetching, and electroplating to obtain the RDL and bonding pad metal, wherein the thickness of the bonding pad metal ranges from 1um to 100um, the bonding pad metal can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
then, a groove, namely a front cavity 102, is etched on the exposed end surface of the TSV through the processes of photoetching and dry etching, wherein the depth range of the groove is 1um to 1000um, and the length of the groove is 10um to 50000 um;
performing temporary bonding, thinning the reverse side of the silicon wafer to expose the bottom of the TSV, and then depositing an insulating layer of silicon oxide or silicon nitride and the like, or directly performing thermal oxidation, wherein the thickness of the insulating layer ranges from 10nm to 100 um;
exposing the metal at the bottom of the TSV through a polishing process;
the silicon chip and the temporary bonding slide glass in the step comprise 4, 6, 8 and 12-inch wafers, the thickness range is 200um to 2000um, the silicon chip and the temporary bonding slide glass can be made of other materials, such as glass, quartz, silicon carbide, alumina and other inorganic materials, epoxy resin, polyurethane and other organic materials, and the main function of the silicon chip and the temporary bonding slide glass is to provide a supporting function.
B. Manufacturing an RDL and a bonding pad on the back surface of a silicon chip 101, etching a back surface cavity 103, etching to penetrate through the silicon chip 101 to enable a front surface cavity 102 to be communicated with the back surface cavity 103, embedding an intermediate heat radiator 104 with a micro-channel and a liquid inlet between the front surface cavity 102 and the back surface cavity 103, then respectively embedding a chip 105 in the front surface cavity 102 and the back surface cavity 103, filling a gap between the chip 105 and the silicon chip 101, and manufacturing the RDL and the bonding pad on the outer surface of the chip 105;
as shown in fig. 1a, a seed layer is formed on the back surface of a silicon wafer 101 by physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be a layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;
then, defining the RDL and the position of a bonding pad by photoetching, and electroplating to obtain the RDL and the metal of the bonding pad, wherein the thickness of the metal ranges from 1um to 100um, the metal can be one layer or multiple layers, and the metal can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
continuously manufacturing a groove, namely a reverse cavity 103 on the surface by photoetching and dry etching processes, wherein the depth range of the groove is 1um to 1000um, and the length of the groove is 10um to 50000 um;
continuously coating glue on the bottom of the groove and the surface of the silicon wafer, exposing and opening the photoresist at the bottom of the groove, and etching by a dry method to penetrate through the bottom of the groove on the front side of the silicon wafer so as to enable the grooves on the two sides to be communicated;
as shown in fig. 1b, an intermediate heat sink 104 with a micro-channel and a liquid inlet is embedded in the middle of the cavity, and the intermediate heat sink 104 may be made of metal, silicon material or glass material; a microfluidic channel is arranged in the middle of the chamber;
as shown in fig. 1c, the chip 105 is embedded into the cavities on both sides, and the gap between the chip 105 and the cavity is filled by spraying or spin coating; then, manufacturing an RDL and a bonding pad on one surface of the chip through photoetching and electroplating processes;
C. an outer layer radiator 106 with a micro-channel and a liquid inlet is welded on the outer layer of the chip 105, the liquid inlet of the outer layer radiator 106 is communicated with the liquid inlet of the middle radiator 104, then an outer layer chip 107 is welded outside the outer layer radiator 106 in a chip mounting mode, the outer layer chip 107 and a surface bonding pad of the chip 106 are interconnected through BGA solder balls, then the bottom of the outer layer chip 107 is interconnected with the outer layer radiator 106, and a final structure is formed.
As shown in fig. 1d, a new outer layer heat sink 106 with micro-channel and liquid inlet is welded on the outer layer of the two-sided chip, so that the liquid inlet is communicated with the liquid inlet of the middle heat sink 104 embedded in the silicon chip;
as shown in fig. 1e, an outer layer chip 107 is bonded on the outer layer of the device by means of chip mounting, so that the outer layer chip 107 is connected with the surface pads of the chip 104 by means of BGA solder balls, and then the bottom of the outer layer chip 107 is connected with the micro channels of the outer layer heat sink 106, thereby forming a final structure.
Claims (4)
1. A PCB assembly mode with liquid heat dissipation function is characterized by comprising the following steps:
A. manufacturing a TSV, an RDL and a bonding pad on the front side of a silicon chip (101), etching a front cavity (102), performing temporary bonding, thinning the back side of the silicon chip (101) to expose the TSV, covering a passivation layer, and polishing to expose metal of the TSV;
B. manufacturing an RDL and a bonding pad on the reverse side of a silicon chip (101), etching a reverse side cavity (103), etching to penetrate through the silicon chip (101) to enable a front side cavity (102) to be communicated with the reverse side cavity (103), embedding an intermediate radiator (104) with a micro-channel and a liquid inlet between the front side cavity (102) and the reverse side cavity (103), then respectively embedding a chip (105) in the front side cavity (102) and the reverse side cavity (103), filling a gap between the chip (105) and the silicon chip (101), and manufacturing the RDL and the bonding pad on the outer surface of the chip (105);
C. an outer layer radiator (106) with a micro-channel and a liquid inlet is welded on the outer layer of the chip (105), the liquid inlet of the outer layer radiator (106) is communicated with the liquid inlet of the middle radiator (104), then an outer layer chip (107) is welded outside the outer layer radiator (106) in a chip mounting mode, the outer layer chip (107) is connected with a surface bonding pad of the chip (105) through BGA solder balls, then the bottom of the outer layer chip (107) is connected with the outer layer radiator (106), and a final structure is formed.
2. The assembly of PCB with liquid heat dissipation function of claim 1, wherein the specific steps of step A are:
a1, manufacturing TSVs with different depths on the front side of the silicon wafer (101), manufacturing an insulating layer on the front side of the silicon wafer (101), manufacturing a seed layer on the insulating layer, electroplating copper to enable copper metal to fill the TSVs, removing the copper on the surface of the silicon wafer (101), and enabling only the copper to be filled on the surface of the silicon wafer (101);
a2, manufacturing an RDL and a bonding pad on the front side of the silicon wafer (101) through the processes of photoetching and electroplating;
a3, etching a front cavity (102) on the front side of the silicon wafer (101) through the processes of photoetching and dry etching;
and A4, performing temporary bonding, thinning the reverse side of the silicon wafer (101) to expose the bottom of the TSV, then manufacturing an insulating layer on the reverse side of the silicon wafer (101), and exposing the metal at the bottom of the TSV through a polishing process.
3. The PCB assembly with liquid heat dissipation function according to claim 2, wherein the step A3 is performed after removing copper on the surface of the silicon wafer (101) and then removing the insulating layer on the surface of the silicon wafer (101) is performed.
4. The assembly of PCB with liquid heat dissipation function of claim 1, wherein the specific steps of step B are:
b1, manufacturing an insulating layer on the reverse side of the silicon wafer (101), and manufacturing a seed layer on the insulating layer;
b2, lithographically defining the positions of the RDL and the bonding pad on the reverse side of the silicon chip (101), and electroplating to form RDL and bonding pad metal;
b3, etching a back cavity (103) on the back surface of the silicon wafer (101) through photoetching and dry etching processes, continuously coating photoresist on the bottom of the back cavity (103) and the back surface of the silicon wafer (101), exposing and opening the photoresist at the bottom of the back cavity (103), and performing dry etching to penetrate through the bottom of the front cavity (102) so as to enable the front cavity (102) to be communicated with the back cavity (103);
b4, embedding an intermediate heat sink (104) with a micro-channel and a liquid inlet between the front cavity (102) and the back cavity (103);
b5, embedding a chip (105) in the front cavity (102) and the back cavity (103) respectively, and filling a gap between the chip (105) and the silicon chip (101) in a glue spraying or spin coating mode;
and B6, forming RDL and bonding pads on the outer surface of the chip (105) through photoetching and electroplating processes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010855826.1A CN111968921B (en) | 2020-08-24 | 2020-08-24 | PCB assembly mode with liquid heat dissipation function |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010855826.1A CN111968921B (en) | 2020-08-24 | 2020-08-24 | PCB assembly mode with liquid heat dissipation function |
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| Publication Number | Publication Date |
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| CN111968921A CN111968921A (en) | 2020-11-20 |
| CN111968921B true CN111968921B (en) | 2022-04-15 |
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| CN112738978B (en) * | 2020-11-24 | 2022-04-12 | 鹤山市世拓电子科技有限公司 | Printed circuit board with micro-channel and manufacturing method thereof |
| CN113066778B (en) * | 2021-03-23 | 2024-02-13 | 浙江集迈科微电子有限公司 | Interposer stack structure and process |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107293496A (en) * | 2017-05-09 | 2017-10-24 | 中国电子科技集团公司第五十五研究所 | Chip-scale integrated microfluidic radiating module and preparation method |
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| CN111403348A (en) * | 2020-03-27 | 2020-07-10 | 华中科技大学 | Ceramic substrate containing micro-channel and preparation method thereof |
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| CN107293496A (en) * | 2017-05-09 | 2017-10-24 | 中国电子科技集团公司第五十五研究所 | Chip-scale integrated microfluidic radiating module and preparation method |
| CN108766897A (en) * | 2018-06-12 | 2018-11-06 | 厦门大学 | Realize the packaging method of the 3-D heterojunction structure of high-power GaN device layer heat dissipation |
| CN109585399A (en) * | 2018-11-22 | 2019-04-05 | 北京遥感设备研究所 | A kind of high-efficiency heat conduction chip substrate structure and preparation method |
| CN110010490A (en) * | 2018-12-25 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of manufacture craft of the radio frequency cube structure longitudinally interconnected |
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| CN110364501A (en) * | 2019-06-17 | 2019-10-22 | 中国科学院微电子研究所 | A kind of fluid channel radiator structure, manufacturing method and electronic device |
| CN210778566U (en) * | 2019-12-24 | 2020-06-16 | 四川九洲电器集团有限责任公司 | Chip embedded micro-channel radiator |
| CN111293078A (en) * | 2020-03-17 | 2020-06-16 | 浙江大学 | Method for embedding chips into cavities on front and back surfaces of adapter plate |
| CN111403348A (en) * | 2020-03-27 | 2020-07-10 | 华中科技大学 | Ceramic substrate containing micro-channel and preparation method thereof |
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