CN110010561B - Radio frequency structure with stacked multilayer chips and manufacturing method thereof - Google Patents
Radio frequency structure with stacked multilayer chips and manufacturing method thereof Download PDFInfo
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- CN110010561B CN110010561B CN201811650206.3A CN201811650206A CN110010561B CN 110010561 B CN110010561 B CN 110010561B CN 201811650206 A CN201811650206 A CN 201811650206A CN 110010561 B CN110010561 B CN 110010561B
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The invention discloses a radio frequency structure with stacked multilayer chips and a manufacturing method thereof, wherein the radio frequency structure comprises a radiating carrier plate and a base carrier plate, wherein the radiating carrier plate and the base carrier plate are bonded to form a module, and the module is stacked and welded with the module; the upper surface of the radiating carrier plate is provided with a groove for placing a chip, the groove area of the radiating carrier plate is provided with a metal column, and vertical through holes are formed in the periphery of the metal column; metal columns are arranged at the positions of the base carrier plate corresponding to the groove areas of the radiating carrier plate and are connected with the metal columns of the radiating carrier plate; a circulation port is arranged in the metal column arrangement area of the base support plate close to the heat dissipation support plate, through holes are arranged at two ends of the circulation port, and the through holes are communicated with the through holes of the heat dissipation support plate; the invention provides the capability of placing a plurality of radio frequency chips in a small area, and each chip has single liquid cooling heat dissipation capability, so that the normal work of a system can be ensured.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a radio frequency structure with stacked multilayer chips and a manufacturing method thereof.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
However, for a high-frequency micro-system, the area of the antenna array is smaller and smaller, and the distance between the antennas needs to be kept within a certain range, so that the whole module has excellent communication capability. However, for an analog device chip such as a radio frequency chip, the area of the analog device chip cannot be reduced by the same multiplying factor as that of a digital chip, so that a radio frequency micro system with a very high frequency rate cannot have enough area to simultaneously place the PA/LNA, the PA/LNA needs to be stacked, and thus it is very difficult to dissipate heat of an upper chip based on the heat conducting copper column.
Disclosure of Invention
The invention overcomes the defects of the prior art, provides the capability of placing a plurality of radio frequency chips in a small area, and ensures that each chip has single liquid cooling heat dissipation capability and the normal work of a system.
The technical scheme of the invention is as follows:
a radio frequency structure with stacked multilayer chips comprises a radiating carrier plate and a base carrier plate, wherein the radiating carrier plate and the base carrier plate are bonded to form a module, and the module is stacked and welded with the module; the upper surface of the radiating carrier plate is provided with a groove for placing a chip, the groove area of the radiating carrier plate is provided with a metal column, and vertical through holes are formed in the periphery of the metal column; metal columns are arranged at the positions of the base carrier plate corresponding to the groove areas of the radiating carrier plate and are connected with the metal columns of the radiating carrier plate; the metal column arrangement area of the base support plate is provided with a circulation port close to the heat dissipation support plate, through holes are arranged at two ends of the circulation port, and the through holes are communicated with the through holes of the heat dissipation support plate.
Furthermore, the chip comprises a digital radio frequency integrated chip and a radio frequency chip.
Further, the diameter range of the through hole is 1um to 1000um, and the depth range is 1um to 500 um.
Further, the width of the groove and the flow opening ranges from 1um to 1000um, and the depth ranges from 1um to 500 um.
A manufacturing method of a radio frequency structure with stacked multilayer chips comprises the following specific processing steps:
101) a heat dissipation carrier plate treatment step: the upper surface of the radiating support plate is provided with TSV holes through an etching process, and the depth of each TSV hole is smaller than the thickness of the radiating support plate; forming an insulating layer on the upper surface of the radiating carrier plate by adopting one of methods of silicon oxide deposition, silicon nitride deposition or direct thermal oxidation; manufacturing a seed layer on the insulating layer by adopting one of physical sputtering, magnetron sputtering or evaporation process; electroplating metal to fill the TSV hole to form a metal column, and densifying the metal column at the temperature of 200-500 ℃; removing surface metal on the upper surface of the heat dissipation carrier plate by using a CMP (chemical mechanical polishing) process, and leaving metal columns;
manufacturing a groove on the upper surface of the radiating carrier plate in a region corresponding to the metal column through an etching process to expose the metal column, depositing silicon oxide or silicon nitride in the groove to form an insulating layer with a certain thickness, and removing the exposed metal column in the groove through a wet etching process;
manufacturing a seed layer in the groove by one of physical sputtering, magnetron sputtering or evaporation process; electroplating metal, filling the bottom of the groove to form connecting metal, and densifying the connecting metal at the temperature of 200-500 ℃; removing metal on the surface of the groove by using a CMP (chemical mechanical polishing) process, and leaving connecting metal; a chip is welded in the groove through an eutectic bonding process, and a chip pin is connected with the connecting metal; manufacturing an RDL and a bonding pad on the upper surface of the heat dissipation carrier plate;
102) a circulation treatment step of the heat dissipation carrier plate: temporarily bonding the upper surface of the heat dissipation carrier plate treated in the step 101) with a temporary carrier plate; manufacturing blind holes around the metal columns on the upper surface of the radiating carrier plate through photoetching and dry etching processes, and thinning the lower surface of the radiating carrier plate through a grinding process to expose the blind holes; depositing an insulating layer formed by silicon oxide or silicon nitride on the lower surface of the bulk carrier plate, and exposing the metal columns and the blind holes by using a CMP (chemical mechanical polishing) process;
103) a base carrier plate treatment step: manufacturing TSV holes in the positions, corresponding to the metal columns of the radiating support plate, of the upper surface of the base support plate through an etching process, wherein the depth of each TSV hole is smaller than the thickness of the base support plate; forming an insulating layer on the upper surface of the base carrier plate by adopting one of methods of silicon oxide deposition, silicon nitride deposition or direct thermal oxidation; manufacturing a seed layer on the insulating layer by adopting one of physical sputtering, magnetron sputtering or evaporation process; electroplating metal, filling the TSV hole to form a metal column, and densifying the metal column at the temperature of 200-500 ℃; removing surface metal on the lower surface of the heat dissipation carrier plate by using a CMP (chemical mechanical polishing) process, and leaving metal columns;
104) base carrier plate circulation treatment: arranging a flow opening in the metal column area on the upper surface of the base carrier plate treated in the step 103) through photoetching and etching processes, wherein the metal column is exposed through the flow opening; depositing silicon oxide or silicon nitride above the circulation port to form an insulating layer, and removing the insulating layer on the surface of the metal column by using a dry etching or wet etching process; manufacturing blind holes on the upper surface of the base support plate at two ends of the flow port through a photoetching dry etching process, thinning the lower surface of the base support plate, and exposing the bottoms of the blind holes and the metal columns; depositing silicon oxide or silicon nitride on the lower surface of the base carrier plate to form an insulating layer, and exposing the metal columns and the blind holes by using a CMP (chemical mechanical polishing) process; manufacturing an RDL and a bonding pad on the lower surface of the base carrier plate through photoetching and electroplating processes;
105) bonding: bonding the lower surface of the radiating carrier plate and the upper surface of the base carrier plate to form a module;
106) a forming step: manufacturing modules embedded with different chips according to the steps, and stacking the modules through a wafer-level bonding process; and cutting the multilayer module stack to form the multilayer module stacked radio frequency structure.
Furthermore, the heat dissipation carrier plate and the base carrier plate are made of one of 4, 6, 8 and 12 inches, the thickness ranges from 200um to 2000um, and the material is one of silicon wafers, glass, quartz, silicon carbide, aluminum oxide, epoxy resin and polyurethane.
Furthermore, the diameter range of the TSV hole is 1um to 1000um, and the depth is 10um to 1000 um; the thickness of the insulating layer ranges from 10nm to 100um, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the seed layer is one or more layers.
Furthermore, the diameter range of the blind hole is 1um to 1000um, and the depth range is 1um to 500 um; the width range of the groove and the flow opening is between 1um and 1000um, and the depth is between 1um and 500 um; the thickness of the connecting metal is as follows; the thickness of the metal pad is between 100nm and 1000 um; the metal bonding pad adopts one of copper, aluminum, nickel, silver, gold and tin; the bonding pad is one or more layers.
Further, the temperature of the bonding process is controlled between 100 and 350 degrees.
Compared with the prior art, the invention has the advantages that: according to the invention, the radio frequency chips are stacked, and the liquid cooling radiator is arranged below the stacked chips, so that the capacity of placing a plurality of radio frequency chips in a small area can be realized, and each chip has single liquid cooling heat dissipation capacity, so that the normal work of the system can be ensured.
Drawings
FIG. 1 is a cross-sectional view of a heat-dissipating carrier plate with metal posts;
FIG. 2 is a cross-sectional view of FIG. 1 with grooves according to the present invention;
FIG. 3 is a cross-sectional view of the present invention of FIG. 2 with the chip and blind vias disposed;
FIG. 4 is a cross-sectional view of a heat-dissipating carrier according to the present invention;
FIG. 5 is a cross-sectional view of a base carrier of the present invention;
FIG. 6 is a cross-sectional view of the bond of FIGS. 4 and 5 in accordance with the present invention;
FIG. 7 is a cross-sectional view of the multi-chip of FIG. 3 in accordance with the present invention;
FIG. 8 is a cross-sectional view of the thinning of FIG. 7 of the present invention;
FIG. 9 is a cross-sectional view of the base carrier corresponding to FIG. 8 according to the present invention;
FIG. 10 is a cross-sectional view of the bond of FIGS. 9 and 10 in accordance with the present invention;
FIG. 11 is a cross-sectional view of a two-layer stack of the present invention;
FIG. 12 is a cross-sectional view of a multi-layer stack of the present invention.
The labels in the figure are: the heat dissipation carrier plate 101, the TSV holes 102, the metal pillars 103, the grooves 104, the connection metal 105, the chip 106, the RDL107, the blind holes 108, the submount carrier plate 109, the flow holes 110, and the pads 111.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1 to 6, a stacked rf structure with multiple layers of chips 106 includes a heat dissipation carrier 101 and a base carrier 109, wherein the heat dissipation carrier 101 and the base carrier 109 are bonded to form a module, and the module is stacked and soldered with the module; the upper surface of the heat dissipation carrier plate 101 is provided with a groove 104 for accommodating a chip 106, the area of the groove 104 of the heat dissipation carrier plate 101 is provided with a metal column 103, and vertical through holes are arranged around the metal column; the metal posts 103 are arranged at the corresponding positions of the base carrier plate 109 and the groove 104 region of the heat dissipation carrier plate 101 and connected with the metal posts 103 of the heat dissipation carrier plate 101; the metal posts 103 of the base carrier 109 are disposed with a flow opening 110 near the heat-dissipating carrier 101, and through holes are disposed at two ends of the flow opening 110 and are communicated with the through holes of the heat-dissipating carrier 101. The chip 106 includes a digital rf integrated chip 106 and an rf chip 106. The diameter of the through hole ranges from 1um to 1000um, and the depth ranges from 1um to 500 um. The width of the grooves 104 and the flow ports 110 ranges from 1um to 1000um, and the depth ranges from 1um to 500 um. The through hole is communicated with the circulation port 110, so that a circulation channel for liquid inlet and outlet is realized, a plurality of chips 106 are simultaneously cooled, and the cooling capacity is enhanced.
A manufacturing method of a radio frequency structure with stacked multilayer chips 106 specifically comprises the following steps:
101) a heat dissipation carrier plate 101 treatment step: the upper surface of the heat dissipation carrier plate 101 is provided with TSV holes 102 by an etching process, wherein some of the TSV holes 102 are disposed around the carrier plate and are mainly used for connecting other carrier plates, and the TSV holes 102 are mainly concentrated in the central area where the chip 106 is to be placed. TSV holes 102 range in diameter from 1um to 1000um and depth from 10um to 1000 um. The depth of the TSV holes 102 is smaller than the thickness of the heat dissipation carrier 101. The upper surface of the heat dissipation carrier plate 101 is formed with an insulating layer by one of methods of depositing silicon oxide, depositing silicon nitride or direct thermal oxidation, and the thickness of the insulating layer ranges from 10nm to 100 um. The seed layer is manufactured on the insulating layer by adopting one of physical sputtering, magnetron sputtering or evaporation process, the thickness range of the seed layer is 1nm to 100um, the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the seed layer has one or more layers. When the seed layer itself is a multi-layer structure, the same material is generally used for each layer. And electroplating metal to fill the TSV hole 102 and form the metal pillar 103, and densifying the metal pillar 103 at a temperature of 200 to 500 ℃. The CMP process removes the surface metal on the upper surface of the heat dissipation carrier 101, leaving the metal posts 103. The insulating layer on the upper surface of the heat dissipation carrier 101 may be removed by a dry etching process or a wet etching process, or may be left. The metal pillar 103 may have a single-layer structure or a multi-layer structure, and the material may be one of titanium, aluminum, silver, palladium, gold, thallium, tin, nickel, and the like, and when the metal pillar 103 has a multi-layer structure, each layer of the material is generally the same.
The upper surface of the heat-dissipating carrier plate 101 is provided with a groove 104 corresponding to the metal column 103 by an etching process, so that the metal column 103 is exposed, the width of the groove 104 ranges from 1um to 1000um, and the depth ranges from 1um to 500 um. And depositing silicon oxide or silicon nitride in the groove 104 to form an insulating layer with a certain thickness, wherein the thickness of the insulating layer is 100nm to 100um, and removing the metal column 103 exposed in the groove 104 by a wet etching process.
A seed layer is manufactured in the groove 104 through one of physical sputtering, magnetron sputtering or evaporation plating processes, the thickness range of the seed layer is 1nm to 100um, the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the seed layer is one or more layers. When the seed layer itself is a multi-layer structure, the same material is generally used for each layer. Electroplating metal to fill the bottom of the recess 104 to form a connecting metal 105, and densifying the connecting metal 105 at a temperature of 200 to 500 ℃, wherein the thickness of the connecting metal 105 ranges from 100nm to 1000 um. The CMP process removes the metal from the surface of the recess 104, leaving the link metal 105. The chip 106 is welded in the groove 104 through a eutectic bonding process, and the welding temperature is controlled between 100 and 350 degrees. The chip 106 pins are connected to the connecting metal 105, so that the chip 106 and the metal posts 103 are interconnected, and the RDL107 and the pads 111 are formed on the lower surface of the heat dissipation carrier 101.
102) A circulation processing step of the heat dissipation carrier plate 101: manufacturing a blind hole 108 around the metal column 103 on the upper surface of the heat dissipation carrier plate 101 processed in the step 101) by using a photoetching and dry etching process, wherein the diameter range of the blind hole 108 is 1um to 1000um, and the depth is 1um to 500 um. The upper surface of the heat-dissipating carrier 101 is temporarily bonded to the temporary carrier to protect the upper surface of the heat-dissipating carrier 101. The lower surface of the bulk carrier is thinned by a grinding process to expose the blind holes 108. An insulating layer formed by silicon oxide or silicon nitride is deposited on the lower surface of the bulk carrier plate, and the metal posts 103 and the blind holes 108 are exposed by a CMP process.
Etching notches (not shown in the figure) on the lower surface of the heat dissipation carrier plate 101 below the chip 106 by using photoetching and dry etching processes, wherein the width of each notch is 1um to 1000um, and the depth of each notch is 10um to 1000 um; the bottom of the notch may extend to the metal layer at the bottom of the chip 106, or a part of the material of the heat dissipation carrier 101 may be remained between the notch and the metal layer at the bottom of the chip 106 to form a micro-flow channel for liquid circulation and heat dissipation. The notch may be opened in the TSV hole 102 region, so that the metal pillar 103 stands up inside the groove 104, and may also avoid the metal pillar 103.
103) The base carrier 109 processing step: the TSV holes 102 are manufactured through an etching process at positions, corresponding to the metal columns 103 of the heat dissipation carrier plate 101, on the upper surface of the base carrier plate 109, the diameter range of the TSV holes 102 is from 1um to 1000um, and the depth is from 10um to 1000 um. The TSV holes 102 have a depth less than the thickness of the pedestal carrier 109. The upper surface of the base carrier plate 109 is formed with an insulating layer having a thickness in a range of 10nm to 100um by one of a deposited silicon oxide, a deposited silicon nitride, or a direct thermal oxidation method. The seed layer is manufactured on the insulating layer by adopting one of physical sputtering, magnetron sputtering or evaporation process, the thickness range of the seed layer is 1nm to 100um, the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the seed layer has one or more layers. When the seed layer itself is a multi-layer structure, the same material is generally used for each layer. And electroplating metal to fill the TSV hole 102 to form the metal pillar 103, and densifying the metal pillar 103 at a temperature of 200 to 500 ℃. The CMP process removes the surface metal of the lower surface of the heat dissipation carrier 101, leaving the metal posts 103. The insulating layer on the upper surface of the base carrier 109 may be removed by a dry etching or wet etching process, or may be left.
104) Base carrier 109 flow-through processing: arranging a circulation port 110 in the area of the metal column 103 on the upper surface of the base carrier plate 109 processed in the step 103) through photoetching and etching processes, wherein the metal column 103 is exposed out of the circulation port 110, the width range of the circulation port 110 is 1um to 1000um, and the depth of the circulation port 110 is 1um to 500 um. An insulating layer is formed by depositing silicon oxide or silicon nitride over the flow port 110 to a thickness of 100nm to 100 um. The flow through port 110 can avoid the area of the metal column 103 to indirectly flow, thereby reducing the heat dissipation effect to a certain extent. The insulating layer on the surface of the metal pillar 103 is removed by a dry etching or wet etching process. The blind holes 108 are manufactured at two ends of the circulation port 110 on the upper surface of the base carrier plate 109 through a photoetching dry etching process, the diameter range of the blind holes 108 is 10um to 1000um, and the depth range is 10um to 1000 um. The lower surface of the base carrier plate 109 is thinned to expose the bottom of the blind hole 108 and the metal pillar 103. Silicon oxide or silicon nitride is deposited on the upper surface of the base carrier plate 109 to form an insulating layer, and the metal posts 103 and the blind holes 108 are exposed by the CMP process. The RDL107 and the pads 111 are formed on the lower surface of the submount carrier 109 by photolithography and plating processes.
105) Bonding: the lower surface of the heat-dissipating carrier 101 is bonded to the upper surface of the base carrier 109 to form a module. The bonding temperature is controlled between 100 and 350 degrees.
106) A forming step: as shown in fig. 7 to 12, modules embedded with different chips 106 are fabricated according to the above steps, and a multi-layered module stack is performed through a wafer-level bonding process. For example, a module with the rf chip 106 and a module with the digital rf integrated chip 106 are manufactured, and the two are processed by a wafer level bonding process to manufacture a stacked wafer, which may be a large number of multi-layer stacks. And cutting the multilayer module stack to form the multilayer module stacked radio frequency structure. Wherein the carrier plate as the top layer of the stack is not provided with blind holes 108.
The heat dissipation carrier plate 101 and the base carrier plate 109 are made of one of 4, 6, 8, 12 inch wafers, have a thickness ranging from 200um to 2000um, are generally made of silicon wafers, can be made of other materials including inorganic materials such as glass, quartz, silicon carbide, aluminum oxide and the like, and can also be made of organic materials such as epoxy resin, polyurethane and the like, and have a main function of providing a supporting function.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (1)
1. A manufacturing method of a radio frequency structure with stacked multilayer chips is characterized in that the radio frequency structure comprises a radiating carrier plate and a base carrier plate, the radiating carrier plate and the base carrier plate are bonded to form a module, and the module is stacked and welded with the module; the upper surface of the radiating carrier plate is provided with a groove for placing a chip, the groove area of the radiating carrier plate is provided with a metal column, and vertical through holes are formed in the periphery of the metal column; metal columns are arranged at the positions of the base carrier plate corresponding to the groove areas of the radiating carrier plate and are connected with the metal columns of the radiating carrier plate; a circulation port is arranged in the metal column arrangement area of the base support plate close to the heat dissipation support plate, through holes are arranged at two ends of the circulation port, and the through holes are communicated with the through holes of the heat dissipation support plate; the chip comprises a digital radio frequency integrated chip; the diameter range of the through hole is 1um to 1000um, and the depth range is 1um to 500 um; the width range of the groove and the flow opening is between 1um and 1000um, and the depth is between 1um and 500 um; the specific treatment comprises the following steps:
101) a heat dissipation carrier plate treatment step: the upper surface of the radiating support plate is provided with TSV holes through an etching process, and the depth of each TSV hole is smaller than the thickness of the radiating support plate; forming an insulating layer on the upper surface of the radiating carrier plate by adopting one of methods of silicon oxide deposition, silicon nitride deposition or direct thermal oxidation; adopting one of magnetron sputtering or evaporation process on the insulating layer to manufacture a seed layer; electroplating metal to fill the TSV hole to form a metal column, and densifying the metal column at the temperature of 200-500 ℃; removing surface metal on the upper surface of the heat dissipation carrier plate by using a CMP (chemical mechanical polishing) process, and leaving metal columns;
manufacturing a groove on the upper surface of the radiating carrier plate in a region corresponding to the metal column through an etching process to expose the metal column, depositing silicon oxide or silicon nitride in the groove to form an insulating layer with a certain thickness, and removing the exposed metal column in the groove through a wet etching process;
manufacturing a seed layer in the groove by one of magnetron sputtering or evaporation process; electroplating metal, filling the bottom of the groove to form connecting metal, and densifying the connecting metal at the temperature of 200-500 ℃; removing metal on the surface of the groove by using a CMP (chemical mechanical polishing) process, and leaving connecting metal; a chip is welded in the groove through an eutectic bonding process, and a chip pin is connected with the connecting metal; manufacturing an RDL and a bonding pad on the upper surface of the heat dissipation carrier plate;
102) a circulation treatment step of the heat dissipation carrier plate: manufacturing blind holes around the metal columns on the upper surface of the heat dissipation carrier plate processed in the step 101) through a photoetching process, and temporarily bonding the upper surface of the heat dissipation carrier plate with a temporary carrier plate; thinning the lower surface of the bulk carrier plate by a grinding process to expose the blind holes; depositing an insulating layer formed by silicon oxide or silicon nitride on the lower surface of the bulk carrier plate, and exposing the metal columns and the blind holes by using a CMP (chemical mechanical polishing) process;
103) a base carrier plate treatment step: manufacturing TSV holes in the positions, corresponding to the metal columns of the radiating support plate, of the upper surface of the base support plate through an etching process, wherein the depth of each TSV hole is smaller than the thickness of the base support plate; forming an insulating layer on the upper surface of the base carrier plate by adopting one of methods of silicon oxide deposition, silicon nitride deposition or direct thermal oxidation; adopting one of magnetron sputtering or evaporation process on the insulating layer to manufacture a seed layer; electroplating metal, filling the TSV hole to form a metal column, and densifying the metal column at the temperature of 200-500 ℃; removing surface metal on the lower surface of the heat dissipation carrier plate by using a CMP (chemical mechanical polishing) process, and leaving metal columns;
104) base carrier plate circulation treatment: arranging a flow opening in the metal column area on the upper surface of the base carrier plate treated in the step 103) through a photoetching process, wherein the metal column is exposed out of the flow opening; depositing silicon oxide or silicon nitride above the circulation port to form an insulating layer, and removing the insulating layer on the surface of the metal column by using a dry etching or wet etching process; manufacturing blind holes on the upper surface of the base support plate at two ends of the flow port through a photoetching dry etching process, thinning the lower surface of the base support plate, and exposing the bottoms of the blind holes and the metal columns; depositing silicon oxide or silicon nitride on the lower surface of the base carrier plate to form an insulating layer, and exposing the metal columns and the blind holes by using a CMP (chemical mechanical polishing) process; manufacturing an RDL and a bonding pad on the lower surface of the base carrier plate through photoetching and electroplating processes;
105) bonding: bonding the lower surface of the radiating carrier plate and the upper surface of the base carrier plate to form a module; wherein, the metal column of the radiating carrier plate is connected with the metal column of the base carrier plate;
106) a forming step: manufacturing modules embedded with different chips according to the steps, and stacking the modules through a wafer-level bonding process; cutting the multilayer module stack to form a multilayer module stacked radio frequency structure;
the heat dissipation carrier plate and the base carrier plate are made of one of 4, 6, 8 and 12 inches, the thickness range is 200-2000 um, and the material is one of silicon wafers, glass, quartz, silicon carbide, aluminum oxide, epoxy resin and polyurethane;
the diameter range of the TSV hole is 1um to 1000um, and the depth is 10um to 1000 um; the thickness range of the insulating layer is between 10nm and 100um, the thickness range of the seed layer is between 1nm and 100um, the material of the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the structure of the seed layer is one or more layers;
the diameter range of the blind hole is 1um to 1000um, and the depth range is 1um to 500 um; the width range of the groove and the flow opening is between 1um and 1000um, and the depth is between 1um and 500 um; the thickness of the metal pad is between 100nm and 1000 um; the metal bonding pad adopts one of copper, aluminum, nickel, silver, gold and tin; the structure of the metal bonding pad is one layer or a plurality of layers;
the temperature of the bonding process is controlled between 100 and 350 degrees.
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| CN113161306B (en) * | 2021-04-15 | 2024-02-13 | 浙江集迈科微电子有限公司 | Efficient heat dissipation structure of chip and preparation process thereof |
| CN114300428A (en) * | 2021-12-21 | 2022-04-08 | 中国电子科技集团公司第五十八研究所 | Micro-channel packaging structure capable of six-surface heat dissipation and manufacturing method thereof |
| CN114429937B (en) * | 2022-01-28 | 2022-12-02 | 深圳卓锐思创科技有限公司 | Integrated circuit chip with multilayer structure |
| CN115050654B (en) * | 2022-08-17 | 2022-11-08 | 甬矽电子(宁波)股份有限公司 | Preparation method of fan-in type packaging structure and fan-in type packaging structure |
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| CN101916757B (en) * | 2010-07-23 | 2011-12-21 | 广东昭信光电科技有限公司 | Microfluid cooling silicon wafer level LED illuminating system |
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