CN111952196B - Groove chip embedding process - Google Patents

Groove chip embedding process Download PDF

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Publication number
CN111952196B
CN111952196B CN202010855815.3A CN202010855815A CN111952196B CN 111952196 B CN111952196 B CN 111952196B CN 202010855815 A CN202010855815 A CN 202010855815A CN 111952196 B CN111952196 B CN 111952196B
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substrate
tsv
metal
etching
passivation layer
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CN111952196A (en
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冯光建
黄雷
高群
郭西
顾毛毛
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a groove chip embedding process, which comprises the following steps: (a) Providing a substrate, etching TSVs with different depths on the front surface of the substrate, electroplating to enable metal to fill the TSVs, polishing to remove metal on the front surface of the substrate, manufacturing RDL and bonding pads on the front surface of the substrate, temporarily bonding the front surface of the substrate, and thinning the back surface of the substrate to enable the long TSVs to be exposed, so that a first substrate is obtained; (b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV; (c) And embedding a chip in the cavity, filling gaps between the chip and the cavity, and manufacturing an RDL and a bonding pad on the surface of the chip to obtain a final structure. According to the groove chip embedding process, the bottom of the cavity is protected by the photoresist, the TSV at the bottom of the cavity is opened by the etching process, so that damage of the whole etching to the passivation layer at the bottom of the cavity can be avoided, the opening of the passivation layer at the bottom of the TSV is facilitated, and the passivation layer at the bottom of the cavity is damaged.

Description

Groove chip embedding process
Technical Field
The invention relates to the technical field of semiconductors, in particular to a groove chip embedding process.
Background
Millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radar, airborne missile tracking systems, space spectrum detection, imaging and the like, and is expected to reach 11 hundred million dollars in 2018 market, so that the millimeter wave radio frequency technology becomes an emerging industry. New applications place new demands on the electrical performance, compact structure and system reliability of the product, and for wireless transmitting and receiving systems, it is not currently possible to integrate them on the same chip (SOC), so that it is necessary to integrate different chips, including radio frequency units, filters, power amplifiers, etc., into a single system to realize the functions of transmitting and receiving signals.
The traditional packaging technology installs various functional chips and passive devices on a substrate, has large occupied area and poor reliability, cannot meet the trend of increasingly miniaturization of a packaging system, and the three-dimensional heterogeneous packaging technology (system-in-package SIP) based on the standard silicon technology integrates chips with different functions of different substrates together by using a TSV technology and a cavity structure, so that stacking and interconnection of the chips can be realized in a smaller area, the area of the functional parts is greatly reduced, the reliability of the functional parts is increased, and the three-dimensional heterogeneous packaging technology becomes the future development direction of the industry more and more.
The radio frequency chip needs to perform heat dissipation and grounding interconnection on the bottom of the radio frequency chip, so that the bottom of the chip needs to be contacted with a TSV copper column, but for a structure in which the radio frequency chip is to be buried into a silicon cavity, if the radio frequency chip is firstly used as the TSV, the back of the adapter plate needs to be used as the cavity, and the bottom of the TSV is used as the bottom of the cavity.
However, in practical applications, the bottom of the cavity needs to be made into a passivation layer to insulate the chip and the interposer, the passivation layer is also deposited on the top of the TSV, and the passivation layer above needs to be re-opened to be interconnected with the bottom of the chip, and the process is generally implemented in a front dry etching manner in the industry, but as the height of the TSV metal column is smaller, the passivation layer at the bottom of the cavity is damaged by the whole etching.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a groove chip embedding process, avoids damage to a passivation layer at the bottom of a cavity by whole-surface etching, and is beneficial to opening the passivation layer at the bottom of a TSV. The technical scheme adopted by the invention is as follows:
A groove chip embedding process comprises the following steps:
(a) Providing a substrate, etching TSVs with different depths on the front surface of the substrate, electroplating to enable metal to fill the TSVs, polishing to remove metal on the front surface of the substrate, manufacturing RDL and bonding pads on the front surface of the substrate, temporarily bonding the front surface of the substrate, and thinning the back surface of the substrate to enable the bottoms of the long TSVs to be exposed to obtain a first substrate;
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(c) And embedding a chip in the cavity, filling gaps between the chip and the cavity, and manufacturing an RDL and a bonding pad on the surface of the chip to obtain a final structure.
Preferably, the recess chip embedding process, wherein the specific steps of the step (a) are as follows:
(a1) Manufacturing TSVs with different depths on the front surface of the substrate through photoetching and etching processes;
(a2) Depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer;
(a3) Electroplating copper to enable copper metal to be filled in the TSV, removing copper on the surface of the substrate, and enabling only copper filled in the surface of the substrate to be left;
(a4) RDL and bonding pads are manufactured on the front surface of the substrate through photoetching and electroplating processes;
(a5) And performing temporary bonding on the front surface of the substrate, thinning the back surface of the substrate to expose the TSV, performing passivation layer on the back surface, polishing to expose the TSV metal, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
Preferably, the recess chip embedding process, wherein the specific steps of the step (b) are as follows:
(b1) Etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(b3) And removing the photoresist, cleaning the substrate, and debonding.
Preferably, the recess chip embedding process, wherein the specific steps of the step (b) are as follows:
(b1) Etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer and a metal layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the metal layer and the passivation layer to expose the metal at the bottom of the TSV;
(b4) And removing the photoresist, cleaning the substrate, and debonding.
Preferably, the recess chip embedding process, wherein the specific steps of the step (b) are as follows:
(b1) Etching a cavity on the back surface of the first substrate through photoetching and dry etching to expose the bottom of the short TSV; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer;
(b3) And exposing the metal on the side wall of the TSV at the bottom of the cavity through dry etching or wet etching.
Preferably, in the recess chip embedding process, the diameter of the TSV is 1 um-1000 um, and the depth is 10 um-1000 um.
Preferably, in the recess chip embedding process, the thickness of the insulating layer is 0.01 um-100 um; the thickness of the seed layer is 0.001 um-100 um, and the seed layer is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Preferably, in the recess chip embedding process, the bonding pad is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Preferably, in the recess chip embedding process, the depth of the cavity is 10 um-1000 um.
The invention has the advantages that: according to the groove chip embedding process, the bottom of the cavity is protected by the photoresist, the TSV at the bottom of the cavity is opened by the etching process, so that damage of the whole etching to the passivation layer at the bottom of the cavity can be avoided, the opening of the passivation layer at the bottom of the TSV is facilitated, and the passivation layer at the bottom of the cavity is damaged.
Drawings
Fig. 1 is a schematic view of a substrate etched TSV hole of the present invention.
Fig. 2 is a schematic diagram of deposition of an insulating layer and a seed layer on the front side of a substrate according to the present invention.
FIG. 3 is a schematic diagram of the formation of RDL and bond pads on the backside of the substrate of the present invention.
Fig. 4 is a schematic view showing the exposure of metal in the bottom passivation layer of embodiment 1 TSV of the present invention.
Fig. 5 is a schematic diagram of a passivation layer deposition according to embodiment 1 of the present invention.
Fig. 6 is a schematic diagram of coating a photoresist on a substrate surface according to example 1 of the present invention.
Fig. 7 is a schematic diagram of photoresist removal according to example 1 of the present invention.
Fig. 8 is a schematic diagram of the final structure of embodiment 1 of the present invention.
Fig. 9 is a schematic view showing the bottom exposure of a short TSV according to embodiment 2 of the present invention.
Fig. 10 is a schematic diagram of the deposition of passivation and metal layers according to example 2 of the present invention.
Fig. 11 is a schematic view showing the bottom metal exposure of embodiment 2 TSV of the present invention.
Fig. 12 is a schematic diagram of photoresist removal according to embodiment 2 of the present invention.
Fig. 13 is a schematic diagram showing the final structure of embodiment 2 of the present invention.
Fig. 14 is a metal exposure schematic diagram of embodiment 3 of the present invention.
Fig. 15 is a schematic view of a cavity bottom TSV sidewall exposed metal in accordance with embodiment 3 of the present invention.
Fig. 16 is a schematic diagram of the final structure of embodiment 3 of the present invention.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
Embodiment one;
A groove chip embedding process comprises the following steps:
(a) Providing a substrate, etching TSVs 102 with different depths on the front surface of the substrate 101, electroplating to fill the TSVs with metal, polishing to remove metal on the front surface of the substrate, manufacturing RDLs and bonding pads on the front surface of the substrate, temporarily bonding the front surface of the substrate, and thinning the back surface of the substrate to expose the long TSVs to obtain a first substrate;
The specific steps of the step (a) are as follows:
(a1) As shown in fig. 1, TSVs with different depths are manufactured on the front surface of a substrate through photoetching and etching processes, the diameter of the TSVs ranges from 1um to 1000um, and the depth ranges from 10um to 1000um;
(a2) As shown in fig. 2, an insulating layer is deposited on the front surface of the substrate, a seed layer is manufactured on the insulating layer, the insulating layer is silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) Electroplating copper to enable copper metal to fill TSV 103, removing copper on the surface of the substrate, and enabling only copper filling to remain on the surface of the substrate;
electroplating copper 103 to fill TSV with copper metal, and densification at 200 to 500 ℃ to make copper denser; copper is removed from the surface of the substrate by a copper CMP process, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by dry etching or wet etching; the insulating layer on the surface of the substrate can also be reserved;
(a4) RDL and bonding pads are manufactured on the front surface of the substrate through photoetching and electroplating processes;
RDL and bonding pads are manufactured at the exposed end of the TSV through photoetching and electroplating processes, a seed layer is firstly manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and metal materials can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then photoetching to define RDL and pad positions, electroplating to form RDL and pad metal, wherein the thickness of the metal ranges from 1um to 100um, and the metal can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
The SOI substrate and the carrier sheet in the step comprise 4,6,8 and 12 inch substrates with the thickness ranging from 200um to 2000um, can be made of other materials, including inorganic materials such as glass, quartz, silicon carbide, alumina and the like, and can also be made of organic materials such as epoxy resin, polyurethane and the like, and the main function of the carrier sheet is to provide a supporting function.
As shown in fig. 3, temporary bonding is performed on the front surface of the substrate, then the back surface is thinned to expose the TSV, a passivation layer is formed on the back surface, the TSV metal is exposed by polishing, and then RDL and bonding pads are continuously manufactured;
(a5) And performing temporary bonding on the front surface of the substrate, thinning the back surface of the substrate to expose the TSV, performing passivation layer on the back surface, polishing to expose metal at the bottom of the TSV, and then manufacturing an RDL and a bonding pad to obtain the first substrate.
(B) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
the specific steps of the step (b) are as follows:
(b1) As shown in fig. 4, the cavity 104 is etched on the back of the first substrate by means of photolithography and dry etching, so that the bottom of the short TSV is exposed; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) As shown in fig. 5, a passivation layer 105 is deposited, wherein the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the passivation layer ranges from 10nm to 100 um; as shown in fig. 6, the surface is coated with photoresist 106, the bottom of the TSV is exposed by exposure and development, and the passivation layer is etched to expose the metal at the bottom of the TSV;
(b3) As shown in fig. 7, the photoresist is removed, the substrate is cleaned, and the bond is released.
(C) As shown in fig. 8, a chip 107 is embedded in the cavity, gaps between the chip and the cavity are filled, and RDL and pads 108 are fabricated on the chip surface to obtain the final structure.
Example 2:
A groove chip embedding process comprises the following steps:
(a) Providing a substrate, etching TSVs with different depths on the front surface of the substrate, electroplating to enable metal to fill the TSVs, polishing to remove metal on the front surface of the substrate, manufacturing RDL and bonding pads on the front surface of the substrate, temporarily bonding the front surface of the substrate, and thinning the back surface of the substrate to enable the long TSVs to be exposed, so that a first substrate is obtained;
The specific steps of the step (a) are as follows:
(a1) As shown in fig. 1, TSVs 102 with different depths are manufactured on the front surface of a substrate 101 through photoetching and etching processes, wherein the diameter of the TSVs ranges from 1um to 1000um, and the depth ranges from 10um to 1000um;
(a2) As shown in fig. 2, an insulating layer is deposited on the front surface of the substrate, a seed layer is manufactured on the insulating layer, the insulating layer is silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) Electroplating copper to enable copper metal to fill TSV 103, removing copper on the surface of the substrate, and enabling only copper filling to remain on the surface of the substrate;
electroplating copper 103 to fill TSV with copper metal, and densification at 200 to 500 ℃ to make copper denser; copper is removed from the surface of the substrate by a copper CMP process, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by dry etching or wet etching; the insulating layer on the surface of the substrate can also be reserved;
(a4) RDL and bonding pads are manufactured on the front surface of the substrate through photoetching and electroplating processes;
RDL and bonding pads are manufactured at the exposed end of the TSV through photoetching and electroplating processes, a seed layer is firstly manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and metal materials can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then photoetching to define RDL and pad positions, electroplating to form RDL and pad metal, wherein the thickness of the metal ranges from 1um to 100um, and the metal can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
The SOI substrate and the carrier sheet in the step comprise 4,6,8 and 12 inch substrates with the thickness ranging from 200um to 2000um, can be made of other materials, including inorganic materials such as glass, quartz, silicon carbide, alumina and the like, and can also be made of organic materials such as epoxy resin, polyurethane and the like, and the main function of the carrier sheet is to provide a supporting function.
As shown in fig. 3, temporary bonding is performed on the front surface of the substrate, then the back surface is thinned to expose the TSV, a passivation layer is formed on the back surface, the TSV metal is exposed by polishing, and then RDL and bonding pads are continuously manufactured;
(a5) And performing temporary bonding on the front surface of the substrate, thinning the back surface of the substrate to expose the TSV, performing passivation layer on the back surface, polishing to expose the TSV metal, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
(B) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
the specific steps of the step (b) are as follows:
(b1) As shown in fig. 9, the cavity is etched on the back of the first substrate by means of photoetching and dry etching, and the depth of the cavity is 10um to 1000um, so that the bottom of the short TSV is exposed; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer and a metal layer 109, wherein the passivation layer is silicon oxide or silicon nitride or is directly thermally oxidized, and the thickness of the passivation layer ranges from 10nm to 100 um; the thickness of the metal layer ranges from 1nm to 100um, and the metal layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(b3) As shown in fig. 10, photoresist is coated on the surface, the bottom of the TSV is exposed through exposure and development, and as shown in fig. 11, the metal layer and the passivation layer are etched to expose the metal at the bottom of the TSV;
(c) And removing the metal layer, embedding a chip in the cavity, filling gaps, and manufacturing RDL and bonding pads on the surface of the chip to complete the final structure.
As shown in fig. 12, removing the photoresist, removing the metal layer on the surface of the substrate, cleaning the substrate, and debonding;
as shown in fig. 13, a chip is embedded in the cavity, gaps are filled, RDL and pads are fabricated on the chip surface, and the final structure is completed.
Example 3:
A groove chip embedding process comprises the following steps:
(a) Providing a substrate, etching TSVs with different depths on the front surface of the substrate, electroplating to enable metal to fill the TSVs, polishing to remove metal on the front surface of the substrate, manufacturing RDL and bonding pads on the front surface of the substrate, temporarily bonding the front surface of the substrate, and thinning the back surface of the substrate to enable the long TSVs to be exposed, so that a first substrate is obtained;
The specific steps of the step (a) are as follows:
(a1) As shown in fig. 1, TSVs with different depths are manufactured on the front surface of a substrate through photoetching and etching processes, the diameter of the TSVs ranges from 1um to 1000um, and the depth ranges from 10um to 1000um;
(a2) As shown in fig. 2, an insulating layer is deposited on the front surface of the substrate, a seed layer is manufactured on the insulating layer, the insulating layer is silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) Electroplating copper to enable copper metal to be filled in the TSV, removing copper on the surface of the substrate, and enabling only copper filled in the surface of the substrate to be left;
electroplating copper 103 to fill TSV with copper metal, and densification at 200 to 500 ℃ to make copper denser; copper is removed from the surface of the substrate by a copper CMP process, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by dry etching or wet etching; the insulating layer on the surface of the substrate can also be reserved;
(a4) RDL and bonding pads are manufactured on the front surface of the substrate through photoetching and electroplating processes;
RDL and bonding pads are manufactured at the exposed end of the TSV through photoetching and electroplating processes, a seed layer is firstly manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and metal materials can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then photoetching to define RDL and pad positions, electroplating to form RDL and pad metal, wherein the thickness of the metal ranges from 1um to 100um, and the metal can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
The SOI substrate and the carrier sheet in the step comprise 4,6,8 and 12 inch substrates with the thickness ranging from 200um to 2000um, can be made of other materials, including inorganic materials such as glass, quartz, silicon carbide, alumina and the like, and can also be made of organic materials such as epoxy resin, polyurethane and the like, and the main function of the carrier sheet is to provide a supporting function.
As shown in fig. 3, temporary bonding is performed on the front surface of the substrate, then the back surface is thinned to expose the TSV, a passivation layer is formed on the back surface, the TSV metal is exposed by polishing, and then RDL and bonding pads are continuously manufactured;
(a5) And performing temporary bonding on the front surface of the substrate, thinning the back surface of the substrate to expose the TSV, performing passivation layer on the back surface, polishing to expose the TSV metal, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
(B) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
the specific steps of the step (b) are as follows:
(b1) As shown in fig. 14, cavities are etched on the back surface of the first substrate by photolithography and dry etching, and the depth of the cavities is 10um to 1000um, so that the bottoms of the short TSVs are exposed; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer; the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the passivation layer is between 10nm and 100 um;
(b3) As shown in fig. 15, the metal is exposed from the TSV sidewall at the bottom of the cavity by dry or wet etching.
(C) And embedding a chip into the cavity, filling gaps, and manufacturing RDL and bonding pads on the surface of the chip to complete the final structure.
As shown in fig. 16, a chip is embedded in the cavity, gaps are filled, RDL and pads are fabricated on the chip surface, and the final structure is completed.
According to the groove chip embedding process, the bottom of the cavity is protected by the photoresist, the TSV at the bottom of the cavity is opened by the etching process, so that damage of the whole etching to the passivation layer at the bottom of the cavity can be avoided, the opening of the passivation layer at the bottom of the TSV is facilitated, and the passivation layer at the bottom of the cavity is damaged.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.

Claims (5)

1. The groove chip embedding process is characterized by comprising the following steps of:
(a) Providing a substrate, etching TSVs with different depths on the front surface of the substrate, electroplating to enable metal to fill the TSVs, polishing to remove metal on the front surface of the substrate, manufacturing RDL and bonding pads on the front surface of the substrate, temporarily bonding the front surface of the substrate, and thinning the back surface of the substrate to enable the bottoms of the long TSVs to be exposed, so as to obtain a first substrate;
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(c) Embedding a chip in the cavity, filling gaps between the chip and the cavity, and manufacturing an RDL and a bonding pad on the surface of the chip to obtain a final structure;
the specific steps of the step (b) are as follows:
(b1) Etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(b3) Removing the photoresist, cleaning the substrate, and debonding;
Or the specific steps of the step (b) are as follows:
(b1) Etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer and a metal layer;
(b3) Coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the metal layer and the passivation layer to expose the metal at the bottom of the TSV;
Or the specific steps of the step (b) are as follows:
(b1) Etching a cavity on the back surface of the first substrate through photoetching and dry etching to expose the bottom of the short TSV; exposing the metal by dry etching or wet etching the passivation layer at the bottom of the TSV;
(b2) Depositing a passivation layer;
(b3) Exposing the side wall of the TSV at the bottom of the cavity to metal through dry etching or wet etching;
the specific steps of the step (a) are as follows:
(a1) Manufacturing TSVs with different depths on the front surface of the substrate through photoetching and etching processes;
(a2) Depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer;
(a3) Electroplating copper to enable copper metal to be filled in the TSV, removing copper on the surface of the substrate, and enabling only copper filled in the surface of the substrate to be left;
(a4) RDL and bonding pads are manufactured on the front surface of the substrate through photoetching and electroplating processes;
(a5) And performing temporary bonding on the front surface of the substrate, thinning the back surface of the substrate to expose the bottom of the TSV, performing passivation layer on the back surface, polishing to expose metal at the bottom of the TSV, and then manufacturing an RDL and a bonding pad to obtain the first substrate.
2. The recessed chip process of claim 1, wherein the TSV has a diameter of 1um to 1000um and a depth of 10um to 1000um.
3. The recessed chip embedding process of claim 1, wherein the insulating layer has a thickness of 0.01um to 100um; the thickness of the seed layer is 0.001 um-100 um, and the seed layer is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
4. The recess chip embedding process of claim 1, wherein the bonding pad is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
5. The recessed chip embedding process of claim 1, wherein the cavity depth is between 10um and 1000um.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112687673B (en) * 2020-12-28 2022-07-12 华进半导体封装先导技术研发中心有限公司 Chip embedded slide structure with different thicknesses and preparation method thereof
CN112736073B (en) * 2020-12-28 2022-07-12 华进半导体封装先导技术研发中心有限公司 Silicon-based optical computation heterogeneous integrated module
CN113345836A (en) * 2021-06-01 2021-09-03 浙江集迈科微电子有限公司 TSV electroplating process
CN114388366B (en) * 2022-03-22 2022-05-31 湖北江城芯片中试服务有限公司 Preparation method of packaging shell and preparation method of packaging chip
CN115290713B (en) * 2022-07-15 2023-08-22 广东芯阅科技有限公司 Electrochemical sensitive chip based on metallized through hole substrate technology and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203833606U (en) * 2014-04-30 2014-09-17 安徽北方芯动联科微系统技术有限公司 Lamination combined type MEMS chip
CN104795338A (en) * 2015-04-13 2015-07-22 华进半导体封装先导技术研发中心有限公司 Wafer-level low-cost packaging process and structure of backside-illuminated image chip
US9553080B1 (en) * 2015-09-18 2017-01-24 Globalfoundries Inc. Method and process for integration of TSV-middle in 3D IC stacks
CN110010561A (en) * 2018-12-31 2019-07-12 杭州臻镭微波技术有限公司 A kind of radio-frequency structure and preparation method thereof that multilayer chiop stacks
CN110867429A (en) * 2019-12-09 2020-03-06 上海先方半导体有限公司 TSV (through silicon via) adapter plate interconnection structure
CN111243970A (en) * 2020-02-28 2020-06-05 浙江集迈科微电子有限公司 Chip embedding process in cavity
CN111341665A (en) * 2020-02-29 2020-06-26 浙江集迈科微电子有限公司 Method for manufacturing chip embedded adapter plate groove
CN111341668A (en) * 2020-02-29 2020-06-26 浙江集迈科微电子有限公司 Method for embedding radio frequency chip in silicon cavity

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721353B1 (en) * 2005-07-08 2007-05-25 삼성전자주식회사 structure and fabrication method of chip-embedded interposer, wafer-level stack structure of different kinds of chips using the same, and resultant package structure
WO2012122388A2 (en) * 2011-03-08 2012-09-13 Georgia Tech Research Corporation Chip-last embedded interconnect structures and methods of making the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203833606U (en) * 2014-04-30 2014-09-17 安徽北方芯动联科微系统技术有限公司 Lamination combined type MEMS chip
CN104795338A (en) * 2015-04-13 2015-07-22 华进半导体封装先导技术研发中心有限公司 Wafer-level low-cost packaging process and structure of backside-illuminated image chip
US9553080B1 (en) * 2015-09-18 2017-01-24 Globalfoundries Inc. Method and process for integration of TSV-middle in 3D IC stacks
CN110010561A (en) * 2018-12-31 2019-07-12 杭州臻镭微波技术有限公司 A kind of radio-frequency structure and preparation method thereof that multilayer chiop stacks
CN110867429A (en) * 2019-12-09 2020-03-06 上海先方半导体有限公司 TSV (through silicon via) adapter plate interconnection structure
CN111243970A (en) * 2020-02-28 2020-06-05 浙江集迈科微电子有限公司 Chip embedding process in cavity
CN111341665A (en) * 2020-02-29 2020-06-26 浙江集迈科微电子有限公司 Method for manufacturing chip embedded adapter plate groove
CN111341668A (en) * 2020-02-29 2020-06-26 浙江集迈科微电子有限公司 Method for embedding radio frequency chip in silicon cavity

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