CN110010499B - Radio frequency chip system-in-package process with electromagnetic shielding function - Google Patents
Radio frequency chip system-in-package process with electromagnetic shielding function Download PDFInfo
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- CN110010499B CN110010499B CN201811176851.6A CN201811176851A CN110010499B CN 110010499 B CN110010499 B CN 110010499B CN 201811176851 A CN201811176851 A CN 201811176851A CN 110010499 B CN110010499 B CN 110010499B
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a radio frequency chip system-in-package process with an electromagnetic shielding function, which comprises the following steps: 101) a cover plate processing step, 102) a copper column processing step, 103) a cavity manufacturing step, 104) a base processing step and 105) a packaging step; the invention provides a radio frequency chip system-in-package process with an electromagnetic shielding function, which realizes the electromagnetic shielding function between radio frequency chips without increasing the cost and the occupied area.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a radio frequency chip system-in-package process with an electromagnetic shielding function.
Background
With the gradual reduction of the chip size, the traditional single chip type packaging process has been transited from the original slot type to the BGA, then to the WLCSP and finally to the Fan-out, but with the proposal of the system level functional module, the system level packaging mode gradually replaces the past single chip type, and the chips with different materials and different functions are integrated into a smaller area through the carrier, so that the unit occupied area of the chips is reduced, the signal interconnection line is shortened, and the assembly of the product is facilitated.
However, for the communication industry, the high frequency rf chip gradually replaces the original low frequency product, so that the problem of electromagnetic wave interference between the rf chip and the rf chip, between the rf chip and other functional chips, and between the rf system-level module and other rf system-level modules is more and more emphasized.
In order to deal with the problem, the increase of the electromagnetic shielding layer is the mainstream means at present, and is also the necessary protection means for preventing the electromagnetic wave pollution, and generally, the plastic body of the IC chip is non-conductive and has almost no shielding effect on the electromagnetic field. At present, a metal shielding cover is mostly arranged on the outer surface of a packaging body, and the mode has good shielding performance, but has large specific gravity, large occupied area, high cost and no corrosion resistance.
Disclosure of Invention
The invention overcomes the defects of the prior art, and provides the radio frequency chip system-in-package process with the electromagnetic shielding function, which realizes the electromagnetic shielding function between radio frequency chips under the condition of not increasing the cost and the occupied area.
The technical scheme of the invention is as follows:
a radio frequency chip system-in-package process with an electromagnetic shielding function structurally comprises a cover plate and a base, and specifically comprises the following steps:
101) a cover plate processing step: through photoetching and etching processes, TSV holes are formed in the surface of the cover plate, the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; arranging an insulating layer above the cover plate, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; copper is electroplated to fill the TSV hole with copper metal, densification is carried out at the temperature of 200-500 ℃, and the copper on the surface of the cover plate is removed through a CMP process, so that only the copper filled is left;
manufacturing a whole metal layer on the surface of the cover plate, wherein the whole metal layer comprises an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the metal layer is connected with one end of the copper column in the TSV hole by windowing through photoetching and dry etching processes;
102) copper column treatment: thinning the unexposed end of the copper column of the cover plate, exposing the other end of the copper column through the processes of grinding, wet etching and dry etching, covering an insulating layer on the exposed surface of the copper column, wherein the thickness of the insulating layer is in the range of 10nm to 1000um, windowing the surface of the insulating layer through the processes of photoetching and etching, and exposing the copper column after windowing;
103) a cavity manufacturing step: manufacturing a cavity on a base through photoetching and dry etching, wherein the cavity is cubic, cylindrical or hemispherical, the size range of the cavity is 10um to 10000um, and the size comprises the length, width and height of the cubic shape or the diameter and height of the cylindrical or hemispherical shape; manufacturing an insulating layer on one surface of the cover plate, which is provided with the cavity, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is plated to cover the surface of the cavity, the CMP process removes copper on the surface of the cover plate to only leave an insulating layer, and the insulating layer of the exposed head part of the copper column in the TSV hole is removed through photoetching and dry etching; manufacturing RDL and bonding metal on one surface of the cover plate with the cavity through photoetching and electroplating processes, so that the height range of the bonding pad reaches 10nm to 1000um, the bonding metal adopts one or more of copper, aluminum, nickel, silver, gold and tin, the bonding metal structure is one layer or multiple layers, and the thickness range of the bonding metal structure is 10nm to 1000 um;
104) a base treatment step: manufacturing TSV holes on the surface of the base through photoetching and etching processes, wherein the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; an insulating layer is arranged above the base, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; copper is electroplated to fill the TSV hole with copper metal, densification is carried out at the temperature of 200-500 ℃, and the copper on the surface of the cover plate is removed through a CMP process, so that only the copper filled is left;
the RDL is manufactured on the surface of the base, the process comprises the steps of manufacturing an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer is made of silicon oxide or silicon nitride; windowing through photoetching and dry etching processes to connect the RDL of the base with one end of the copper column of the TSV hole; the bonding pad and the RDL are positioned on the same surface, namely at one exposed end of the copper column of the TSV hole; thinning the metal-free surface of the base, and exposing the other end of the copper column through the processes of grinding, wet etching and dry etching; covering an insulating layer on the surface of the exposed copper pillar, wherein the thickness of the insulating layer ranges from 10nm to 1000um, windowing the surface of the insulating layer through photoetching and etching processes, and exposing the copper pillar after windowing; manufacturing an RDL on the surface of the base;
105) and (3) packaging: the functional chip is arranged on a bonding pad of the base in a eutectic bonding mode, and a pin of the functional chip is communicated with the bonding pad of the base through a routing process, wherein the thickness of the functional chip is between 50um and 600 um; bonding the cover plate and the base together in a wafer bonding mode, and cutting to obtain a final module; wherein the bonding temperature ranges from 200 to 500 degrees.
Further, step 101) forming an insulating layer by depositing silicon oxide or silicon nitride as an insulating layer over the cover plate, or by direct thermal oxidation.
Further, in the step 101), the metal layer of the cover plate comprises an RDL, and the RDL is not communicated with the top end of the copper pillar.
Further, the step 103) of manufacturing the RDL by using the photolithography and electroplating process includes manufacturing an insulating layer, wherein the insulating layer has a thickness ranging from 10nm to 1000um and is made of silicon oxide or silicon nitride; and manufacturing an RDL on the surface of the silicon wafer through photoetching and electroplating, wherein the RDL comprises routing and bonding.
Further, an insulating layer covers the surface of the RDL, a window is formed in the insulating layer to expose the bonding pad, the metal of the RDL adopts one or more of copper, aluminum, nickel, silver, gold and tin, the RDL is of one or more layers, and the thickness of the RDL ranges from 10nm to 1000 um; the pad is windowed to 10um to 10000um diameter.
Compared with the prior art, the invention has the advantages that: according to the invention, a silicon cavity structure is utilized, a metal layer is arranged in the silicon cavity, a closed environment with a complete metal cover is formed by wafer bonding, a single electromagnetic shielding environment is created for the radio frequency chip, and electromagnetic shielding among the radio frequency chips, the functional chips and the system level module and other modules is realized under the condition of not increasing the cost and the occupied area.
Drawings
FIG. 1 is a structural diagram of a TSV hole formed in a cover plate according to the present invention;
FIG. 2 is a block diagram of the copper pillar processing and cavity creation of the cover plate of the present invention;
FIG. 3 is a block diagram of the base treatment of the present invention;
FIG. 4 is a block diagram of the invention after packaging;
FIG. 5 is a block diagram of the cover plate of the present invention;
FIG. 6 is a block diagram of the preliminary treatment of the base of the present invention;
FIG. 7 is a block diagram of a functional chip mounted base of the present invention;
fig. 8 is a block diagram of another packaged version of the invention.
The labels in the figure are: the cover plate 101, the cover plate TSV hole 102, the base 201, the base TSV hole 202 and the functional chip 203.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described with reference to the following figures and detailed description.
Example 1:
as shown in fig. 1 to 8, a radio frequency chip system-in-package process with an electromagnetic shielding function structurally includes a cover plate 101 and a base 201, and the specific processing includes the following steps:
101) cover plate 101 processing steps: manufacturing a cover plate TSV hole 102 on the surface of a cover plate 101 through photoetching and etching processes, wherein the diameter range of the cover plate TSV hole 102 is 1um to 1000um, and the depth of the cover plate TSV hole 102 is 10um to 1000 um; an insulating layer is arranged above the cover plate 101, and the thickness of the insulating layer ranges from 10nm to 100 um; the insulating layer is formed over the cap plate 101 by depositing silicon oxide or silicon nitride as an insulating layer, or by direct thermal oxidation. A seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; copper is electroplated to fill the TSV holes 102 of the cover plate with copper metal, densification is carried out at a temperature of 200-500 ℃, and the copper on the surface of the cover plate 101 is removed through a CMP process, so that only the copper filling is left;
manufacturing a whole metal layer on the surface of the cover plate 101, wherein the whole metal layer comprises an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the metal layer is connected with one end of a copper column in the TSV hole 102 of the cover plate through windowing by photoetching and dry etching processes; the metal layer of the lid 101 includes RDL that is not in communication with the top of the copper pillar.
Specifically, as shown in fig. 1, a cover plate TSV hole 102 is manufactured on the surface of a cover plate 101 silicon wafer through photoetching and etching processes, wherein the diameter range of the cover plate TSV hole 102 is 1um to 1000um, and the depth is 10um to 1000 um; depositing an insulating layer of silicon oxide or silicon nitride and the like above the silicon chip, or directly carrying out thermal oxidation, wherein the thickness of the insulating layer is between 10nm and 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
copper is electroplated to fill the TSV with copper metal, and densification is carried out at the temperature of 200-500 ℃ to enable the copper to be more compact; removing copper on the surface of the silicon wafer by a copper CMP process, and only filling copper on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
manufacturing a whole metal layer (the metal layer can comprise RDL) on the surface of a silicon chip, wherein the process comprises the steps of manufacturing an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer can be made of silicon oxide or silicon nitride; windowing through photoetching and dry etching processes to connect the metal layer with one end of the TSV copper column;
manufacturing a whole metal layer or RDL with a special pattern on the surface of a silicon wafer through photoetching and electroplating processes; the RDL can also be not communicated with the top end of the copper column;
102) copper column treatment: thinning the unexposed end of the copper column of the cover plate 101, exposing the other end of the copper column through the processes of grinding, wet etching and dry etching, covering an insulating layer on the exposed surface of the copper column, wherein the thickness of the insulating layer is in the range of 10nm to 1000um, and the insulating layer can be made of silicon oxide or silicon nitride; windowing the surface of the insulating layer through photoetching and etching processes, and exposing the copper cylinder after windowing;
103) a cavity manufacturing step: a cavity is manufactured on the cover plate 101 through photoetching and dry etching, the shape of the cavity is cubic, cylindrical or hemispherical, the size range of the cavity is 10um to 10000um, and the size comprises the diameter and the height of the cubic, the length, the width and the height or the cylindrical or hemispherical shape; manufacturing an insulating layer on one surface of the cover plate 101, which is provided with the cavity, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is plated to cover the surface of the cavity, the CMP process removes copper on the surface of the cover plate 101 to leave only the insulating layer, and the insulating layer of the exposed head part of the copper column in the TSV hole 102 of the cover plate is removed through photoetching and dry etching; manufacturing RDL and bonding metal on one surface of the cover plate 101 with the cavity through photoetching and electroplating processes, so that the height range of the bonding pad reaches 10nm to 1000um, the bonding metal adopts one or more of copper, aluminum, nickel, silver, gold and tin, the bonding metal structure is one layer or multiple layers, and the thickness range of the bonding metal structure is 10nm to 1000 um; the RDL comprises an insulating layer, wherein the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer is made of silicon oxide or silicon nitride; and manufacturing an RDL on the surface of the silicon wafer through photoetching and electroplating, wherein the RDL comprises routing and bonding. Covering an insulating layer on the surface of the RDL, windowing the insulating layer to expose a bonding pad, wherein the metal of the RDL is one or more of copper, aluminum, nickel, silver, gold and tin, the RDL is one or more layers in structure, and the thickness of the RDL ranges from 10nm to 1000 um; the pad is windowed to 10um to 10000um diameter.
Specifically, cavities are manufactured on a wafer through photoetching and dry etching, and the cavities can be cubic, inverted trapezoidal, cylindrical or hemispherical; the size range is 10um to 10000um, and the size includes the length, width and height of a cube, an inverted trapezoid or the diameter or height of a cylinder and a hemisphere; depositing an insulating layer of silicon oxide or silicon nitride and the like on one surface with the cavity, or directly thermally oxidizing, wherein the thickness of the insulating layer is between 10nm and 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
copper is electroplated to cover the surface of the cavity with copper, and the copper CMP process removes copper on the surface of the silicon wafer to leave only an insulating layer on the surface of the silicon wafer; photoetching, etching, removing the insulating layer of the exposed head part of the TSV copper column, and removing by using a dry etching or wet etching process; manufacturing an RDL on one surface with the cavity through photoetching and electroplating processes, wherein the RDL is manufactured through the process of manufacturing an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer can be made of silicon oxide or silicon nitride; manufacturing RDL on the surface of the silicon wafer through photoetching and electroplating processes; the RDL comprises routing and bonding functions;
specifically, an insulating layer may be covered on the surface of the RDL, and a window may be formed in the insulating layer to expose the pad; the RDL metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the RDL metal is 10nm to 1000 um; the diameter of the pad is windowed to 10um to 10000 um;
or an insulating layer is not covered on the surface metal of the cavity, and the RDL or the bonding pad is directly manufactured on the surface of the silicon wafer through photoetching and electroplating processes;
manufacturing bonding metal on the surface of the silicon wafer by photoetching and electroplating processes, wherein the height range of the bonding pad is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be one layer or multiple layers, and the thickness range of the bonding pad is 10nm to 1000 um;
104) the base 201 processing steps: manufacturing a base TSV hole 202 on the surface of a base 201 through photoetching and etching processes, wherein the diameter range of the base TSV hole 202 is 1um to 1000um, and the depth of the base TSV hole is 10um to 1000 um; an insulating layer is arranged above the base 201, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; copper is electroplated to fill the TSV hole 202 of the base with copper metal, densification is performed at a temperature of 200-500 ℃, and the copper on the surface of the base 201 is removed through a CMP process to leave the copper filled;
the RDL is manufactured on the surface of the base 201, the process comprises the steps of manufacturing an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer is made of silicon oxide or silicon nitride; windowing through photoetching and dry etching processes to connect the RDL of the base 201 with one end of the copper column of the TSV hole 202 of the base; the bonding pad and the RDL are positioned on the same side, namely at the exposed end of the copper column of the TSV hole 202 of the base; thinning the metal-free surface of the base 201, and exposing the other end of the copper column through the processes of grinding, wet etching and dry etching; covering an insulating layer on the surface of the exposed copper pillar, wherein the thickness of the insulating layer ranges from 10nm to 1000um, windowing the surface of the insulating layer through photoetching and etching processes, and exposing the copper pillar after windowing; manufacturing an RDL on the surface of the base 201; covering an insulating layer on the surface of the RDL, windowing the insulating layer to expose a bonding pad, wherein the metal of the RDL is one or more of copper, aluminum, nickel, silver, gold and tin, the RDL is one or more layers in structure, and the thickness of the RDL ranges from 10nm to 1000 um; the pad is windowed to 10um to 10000um diameter.
Specifically, as shown in fig. 3, a base TSV hole 202 is formed on the surface of a base 201 silicon wafer through photolithography and etching processes, wherein the diameter range of the base TSV hole 202 is 1um to 1000um, and the depth is 10um to 1000 um; depositing an insulating layer of silicon oxide or silicon nitride and the like above the silicon chip, or directly carrying out thermal oxidation, wherein the thickness of the insulating layer is between 10nm and 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
copper is electroplated to fill the TSV hole 202 of the base with copper metal, and the copper is densified at a temperature of 200 to 500 ℃; removing copper on the surface of the silicon wafer by a copper CMP process, and only filling copper on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
the RDL is formed on the surface of the silicon wafer of the base 201, and the process is as described above, that is, the RDL includes forming an insulating layer, wherein the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer may be made of silicon oxide or silicon nitride; windowing through photoetching and dry etching processes to connect the RDL with one end of the TSV copper column; manufacturing RDL on the surface of the silicon wafer through photoetching and electroplating processes; the RDL comprises routing and bonding functions;
specifically, an insulating layer can be covered on the surface of the RDL, and a window is formed on the insulating layer to expose the bonding pad; the RDL metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the RDL metal is 10nm to 1000 um; the diameter of the pad is windowed to 10um to 10000 um;
manufacturing bonding metal on the surface of a silicon wafer by photoetching and electroplating processes, wherein the height range of a bonding pad is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the bonding pad is 10nm to 1000 um;
the bonding pad and the RDL are arranged on one side and are positioned at one exposed end of the TSV copper column;
thinning one surface of the base 201 wafer without the metal manufacturing process, and exposing the other end of the copper column through the processes of grinding, wet etching and dry etching; covering an insulating layer on the exposed surface of the copper pillar, wherein the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer can be made of silicon oxide or silicon nitride; windowing the surface of the insulating layer through photoetching and etching processes, and exposing the copper cylinder after windowing;
manufacturing an RDL on the surface of a silicon wafer of a base 201, wherein the process comprises the steps of manufacturing an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, and the material of the insulating layer can be silicon oxide or silicon nitride; manufacturing RDL on the surface of the silicon wafer through photoetching and electroplating processes; the RDL comprises routing and bonding functions;
an insulating layer can also be covered on the surface of the RDL, and a window is formed on the insulating layer to expose the bonding pad; the RDL metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the RDL metal is 10nm to 1000 um; the diameter of the pad is windowed to 10um to 10000 um;
manufacturing bonding metal on the surface of a silicon wafer by photoetching and electroplating processes, wherein the height range of a bonding pad is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the bonding pad is 10nm to 1000 um;
105) and (3) packaging: the functional chip 203 is arranged on a bonding pad of the base 201 in a eutectic bonding mode, and a pin of the functional chip 203 is communicated with the bonding pad of the base 201 through a routing process, wherein the thickness of the functional chip 203 is between 50um and 600 um; then the cover plate 101 and the base 201 are bonded together in a wafer bonding mode, and a final module is obtained by cutting; wherein the bonding temperature ranges from 200 to 500 degrees. As shown in fig. 4, the cover plate 101 wafer is covered on the base plate 201 wafer through the bonding pad metal fusion bonding by the wafer bonding process, wherein the bonding temperature ranges from 200 to 500 ℃; cutting the bonded wafer into a single packaging structure, and placing the single packaging structure on the protruding conductive column of the substrate or the PCB in a welding manner to complete communication of the radio frequency chip system-level packaging structure with the electromagnetic shielding function; and cutting the bonded wafer into single packaging modules.
Embodiment 2 is another specific implementation of the structure, and specifically includes the following steps:
the specific embodiment 2 includes:
201) manufacturing a cover plate 101 with a cavity structure and a bonding pad;
as shown in fig. 5, an insulating layer such as silicon oxide or silicon nitride is deposited on the surface of the silicon wafer of the cover plate 101 by photolithography and etching processes, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
manufacturing a bonding pad on the surface of a wafer through photoetching and electroplating processes, and then manufacturing a cavity on the wafer through photoetching and dry etching, wherein the cavity can be cubic, inverted trapezoid or cylindrical or hemispherical; the size range is 10um to 10000um, and the size includes the length, width and height of a cube, an inverted trapezoid or the diameter or height of a cylinder and a hemisphere;
or depositing an insulating layer such as silicon oxide or silicon nitride on the surface with the cavity, or directly thermally oxidizing, wherein the thickness of the insulating layer is in the range of 10nm to 100 um; photoetching, etching, removing the insulating layer on the welding pad part, and removing by using a dry etching or wet etching process;
b: manufacturing a groove, a TSV and an RDL structure on a base 201 wafer;
as shown in fig. 6, grooves are formed on the surface of the silicon wafer of the base 201 by a dry etching method, and the grooves may be cubic, inverted trapezoidal, cylindrical or hemispherical; the size range is 10um to 10000um, and the size includes the length, width and height of a cube, an inverted trapezoid or the diameter or height of a cylinder and a hemisphere; the silicon wafer in the step comprises 4, 6, 8 and 12 inch wafers, the thickness ranges from 200um to 2000um, other materials can be used, such as inorganic materials including glass, quartz, silicon carbide, alumina and the like, organic materials including epoxy resin, polyurethane and the like can be used, and the main function of the silicon wafer is to provide a supporting effect.
Depositing an insulating layer of silicon oxide or silicon nitride and the like above the silicon chip, or directly carrying out thermal oxidation, wherein the thickness of the insulating layer is between 10nm and 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper, so that a copper metal layer is fully paved on the surface of the groove, the thickness of the layer is between 100nm and 100um, and the copper on the surface of the silicon wafer is removed by a copper CMP process, so that only copper filling is left on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
through photoetching and etching processes, TSV holes are formed in the surface of a silicon wafer, the diameter range of the holes is 1um to 1000um, and the depth of the holes is 10um to 1000 um; depositing an insulating layer of silicon oxide or silicon nitride and the like above the silicon chip, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper to fill the TSV with copper metal, and densifying at 200-500 ℃ to make the copper more dense; removing copper on the surface of the silicon wafer by a copper CMP process, and only filling copper on the surface of the silicon wafer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved;
manufacturing an RDL on the surface of a silicon wafer, wherein the RDL is manufactured in the process of manufacturing an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer can be made of silicon oxide or silicon nitride; windowing through photoetching and dry etching processes to connect the RDL with one end of the TSV copper column; manufacturing RDL on the surface of the silicon wafer through photoetching and electroplating processes; the RDL comprises routing and bonding functions; the RDL can comprise a heat dissipation metal block, if the thickness requirement of the metal block is special, the heat dissipation metal block is manufactured through the processes of seed layer sputtering, photoetching, electroplating, seed layer removal and the like, and the heat dissipation metal block is connected with one end of the TSV copper column;
an insulating layer can also be covered on the surface of the RDL, and a window is formed on the insulating layer to expose the bonding pad; the RDL metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the RDL metal is 10nm to 1000 um; the diameter of the pad is windowed to 10um to 10000 um;
manufacturing bonding metal on the surface of a silicon wafer by photoetching and electroplating processes, wherein the height range of a bonding pad is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the bonding pad is 10nm to 1000 um;
the bonding pad can be one-sided or both-sided, and the RDL can be one-sided or both-sided;
the structure can be grooved firstly or can be grooved after TSV is finished, and the groove is formed after RDL.
C: placing the functional chip 203 in the groove of the base 201 wafer, and communicating the chip with the bonding pad of the base 201 wafer through a routing process; and bonding the upper cover wafer and the base 201 wafer together by using a wafer-level bonding process, and cutting to obtain single modules.
As shown in fig. 7, the functional chip 203 is soldered on the wafer of the base 201, and a signal is led out by wire bonding; as shown in fig. 8, the cover plate 101 is fused and bonded on the base 201 wafer through the pad metal by the wafer bonding process, wherein the bonding temperature ranges from 200 to 500 degrees; cutting the bonded wafer into a single packaging structure, and placing the single packaging structure on the protruding conductive column of the substrate or the PCB in a welding manner to complete communication of the side heat dissipation type sealed radio frequency chip packaging structure;
the foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (5)
1. A radio frequency chip system-in-package process with an electromagnetic shielding function is characterized in that the package comprises a cover plate and a base, and the specific processing comprises the following steps:
101) a cover plate processing step: through photoetching and etching processes, TSV holes are formed in the surface of the cover plate, the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; arranging an insulating layer above the cover plate, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; copper is electroplated to fill the TSV hole with copper metal, densification is carried out at the temperature of 200-500 ℃, and the copper on the surface of the cover plate is removed through a CMP process, so that only the copper filled is left;
manufacturing a whole metal layer on the surface of the cover plate, wherein the whole metal layer comprises an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the metal layer is connected with one end of the copper column in the TSV hole by windowing through photoetching and dry etching processes;
102) copper column treatment: thinning the unexposed end of the copper column of the cover plate, exposing the other end of the copper column through the processes of grinding, wet etching and dry etching, covering an insulating layer on the exposed surface of the copper column, wherein the thickness of the insulating layer is in the range of 10nm to 1000um, windowing the surface of the insulating layer through the processes of photoetching and etching, and exposing the copper column after windowing;
103) a cavity manufacturing step: manufacturing a cavity on a base through photoetching and dry etching, wherein the cavity is cubic, cylindrical or hemispherical, the size range of the cavity is 10um to 10000um, and the size comprises the length, width and height of the cubic shape or the diameter and height of the cylindrical or hemispherical shape; manufacturing an insulating layer on one surface of the cover plate, which is provided with the cavity, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is plated to cover the surface of the cavity, the CMP process removes copper on the surface of the cover plate to only leave an insulating layer, and the insulating layer of the exposed head part of the copper column in the TSV hole is removed through photoetching and dry etching; manufacturing RDL and bonding metal on one surface of the cover plate with the cavity through photoetching and electroplating processes, so that the height range of the bonding pad reaches 10nm to 1000um, the bonding metal adopts one or more of copper, aluminum, nickel, silver, gold and tin, the bonding metal structure is one layer or multiple layers, and the thickness range of the bonding metal structure is 10nm to 1000 um;
104) a base treatment step: manufacturing TSV holes on the surface of the upper base through photoetching and etching processes, wherein the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; an insulating layer is arranged above the base, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is arranged above the insulating layer, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; copper is electroplated to fill the TSV hole with copper metal, densification is carried out at the temperature of 200-500 ℃, and the copper on the surface of the cover plate is removed through a CMP process, so that only the copper filled is left;
the RDL is manufactured on the surface of the base, the process comprises the steps of manufacturing an insulating layer, the thickness of the insulating layer ranges from 10nm to 1000um, and the insulating layer is made of silicon oxide or silicon nitride; windowing through photoetching and dry etching processes to connect the RDL of the base with one end of the copper column of the TSV hole; the bonding pad and the RDL are positioned on the same surface, namely at one exposed end of the copper column of the TSV hole; thinning the metal-free surface of the base, and exposing the other end of the copper column through the processes of grinding, wet etching and dry etching; covering an insulating layer on the surface of the exposed copper pillar, wherein the thickness of the insulating layer ranges from 10nm to 1000um, windowing the surface of the insulating layer through photoetching and etching processes, and exposing the copper pillar after windowing; manufacturing an RDL on the surface of the base;
105) and (3) packaging: the functional chip is arranged on a bonding pad of the base in a eutectic bonding mode, and a pin of the functional chip is communicated with the bonding pad of the base through a routing process, wherein the thickness of the functional chip is between 50um and 600 um; bonding the cover plate and the base together in a wafer bonding mode, and cutting to obtain a final module; wherein the bonding temperature ranges from 200 to 500 degrees.
2. The radio frequency chip system-in-package process with the electromagnetic shielding function according to claim 1, wherein: step 101) forming an insulating layer over the cover plate by depositing silicon oxide or silicon nitride as the insulating layer, or by direct thermal oxidation.
3. The radio frequency chip system-in-package process with the electromagnetic shielding function according to claim 1, wherein: and 101) the metal layer of the cover plate comprises RDL, and the RDL is not communicated with the top end of the copper column.
4. The radio frequency chip system-in-package process with the electromagnetic shielding function according to claim 1, wherein: step 103), the RDL is manufactured through the photoetching and electroplating process in the step 103), wherein the RDL comprises an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, and the insulating layer is made of silicon oxide or silicon nitride; and manufacturing an RDL on the surface of the silicon wafer through photoetching and electroplating, wherein the RDL comprises a routing and a bonding block.
5. A radio frequency chip system-in-package process with electromagnetic shielding function as claimed in claim 1 or claim 4, wherein: covering an insulating layer on the surface of the RDL, windowing the insulating layer to expose a bonding pad, wherein the metal of the RDL is one or more of copper, aluminum, nickel, silver, gold and tin, the RDL is one or more layers in structure, and the thickness of the RDL ranges from 10nm to 1000 um; the pad is windowed to 10um to 10000um diameter.
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