CN110010543B - Radio frequency chip fan-out type system-in-package process - Google Patents
Radio frequency chip fan-out type system-in-package process Download PDFInfo
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- CN110010543B CN110010543B CN201811176817.9A CN201811176817A CN110010543B CN 110010543 B CN110010543 B CN 110010543B CN 201811176817 A CN201811176817 A CN 201811176817A CN 110010543 B CN110010543 B CN 110010543B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The invention discloses a radio frequency chip fan-out type system-in-package process, which comprises the following steps: 101) a carrier plate processing step, 102) a base processing step, and 103) a packaging step; the invention provides a fan-out system-in-package process of a radio frequency chip, which avoids the damage of secondary processing to the chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fan-out type system-in-package process of a radio frequency chip.
Background
The millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection and imaging and the like, is expected to reach 11 billion dollars in market in 2018, and becomes a new industry. The new application puts new requirements on the electrical performance, compact structure and system reliability of the product, and the wireless transmitting and receiving system cannot be integrated on the same chip (SOC) at present, so that different chips including a radio frequency unit, a filter, a power amplifier and the like need to be integrated into a separate system to realize the functions of transmitting and receiving signals.
The traditional packaging technology is characterized in that various functional chips and passive devices are mounted on a substrate, the occupied area is large, the reliability is poor, and the trend of more and more miniaturization of a packaging system cannot be met.
However, as technology develops, the PAD density of chip interconnection becomes higher and higher, and the traditional BGA technology cannot support such high-density interconnection, so that the fan-out package design has highlighted its great role. The fan-out type is characterized in that PADs of various chips in a system-level chip are rearranged through an RDL (remote desktop library) process, and then each PAD can correspond to a solder ball by means of enlarging a ball placing area on an adapter plate, so that the purpose of PAD redistribution is achieved.
The traditional fan-out type packaging often needs to be re-wired and interconnected with TSV after a chip is attached to an adapter board, and secondary damage is easily caused to the chip.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides a fan-out system-in-package process of a radio frequency chip, which avoids the damage of secondary processing to the chip.
The technical scheme of the invention is as follows:
a radio frequency chip fan-out type system-in-package process specifically comprises the following steps:
101) a carrier plate treatment step: gluing the upper surface of the carrier plate, wherein the thickness of the glue ranges from 100nm to 100um, and bonding the functional chip on the carrier plate;
coating a dielectric layer on the carrier plate, wherein the thickness of the dielectric layer ranges from 50um to 500um, and the material of the dielectric layer is plastic package material, epoxy resin, phenolic resin, silicon oxide or silicon nitride particles;
curing the dielectric layer, polishing the surface of the dielectric layer, and exposing the PAD of the chip by photoetching and etching processes; or directly polishing the surface of the chip, and exposing the PAD of the chip by a dry etching or wet cleaning process;
manufacturing an RDL and a bonding PAD on the surface of the chip through photoetching and electroplating processes, and windowing through photoetching and dry etching processes to connect the RDL with a PAD of the chip; wherein, the bonding pad is manufactured on the surface of the carrier plate through photoetching and electroplating processes; the bonding pad is made of one or more of copper, aluminum, nickel, silver, gold and tin, and has one or more layers with the thickness ranging from 10nm to 1000 um;
102) a base treatment step; manufacturing TSV holes on the upper surface of the base through photoetching and etching processes, wherein the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; forming an insulating layer on the upper surface of the base by depositing silicon oxide or silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer ranges from 10nm to 100um, and then manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process, wherein the thickness of the seed layer ranges from 1nm to 100um, the seed layer is one or more layers, and the metal of the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is electroplated to fill the TSV hole with copper metal, the copper is densified at the temperature of 200-500 ℃, and only copper is left on the upper surface of the base through a CMP process to form a copper column;
manufacturing an RDL on the upper surface of the base, wherein the RDL is manufactured in the process of manufacturing an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, the insulating layer is made of silicon oxide or silicon nitride, windowing is performed through photoetching and dry etching processes to enable the RDL to be connected with the copper column, and the RDL is manufactured on the upper surface of the base through photoetching and electroplating processes and comprises a wiring layer, a heat conduction metal layer and a bonding pad with a bonding function; the RDL adopts one or more of copper, aluminum, nickel, silver, gold and tin as metal, the structure of the RDL is one layer or a plurality of layers, and the thickness range of the RDL is 10nm to 1000 um;
the bonding pad is manufactured on the upper surface of the base through photoetching and electroplating processes, the height range of the bonding pad is 10nm to 1000um, the bonding pad adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the structure of the bonding pad is one layer or multiple layers; the bonding pad and the RDL are positioned on the same surface;
thinning the lower surface of the base to expose the TSV hole, and manufacturing an RDL on the lower surface of the base in the same manner as the upper surface;
103) and (3) packaging: the base and the carrier plate are bonded, the carrier plate is removed, a single module is obtained through cutting, and the single module is placed on a substrate with a bonding pad or a PCB through a welding process to complete interconnection of a chip and the outside.
Furthermore, the glue is UV glue or hot melt glue.
Further, the insulating layer on the upper surface of the base is removed by a dry etching or wet etching process.
Furthermore, the RDL surface of the upper surface of the base covers an insulating layer, a window is formed in the insulating layer to expose the position of the bonding pad, and the diameter of the window is 10um to 10000 um.
Furthermore, the base adopts one of 4, 6, 8 and 12 inches in size specification, the thickness range is 200um to 2000um, and silicon chips, glass, quartz, silicon carbide, aluminum oxide, epoxy resin or polyurethane are adopted.
Compared with the prior art, the invention has the advantages that: according to the invention, the TSV is directly manufactured on the base adapter plate and the wiring is performed again, and the chip of the fan-out structure is directly bonded on the base adapter plate through a metal bonding process, so that the risk of damage to the chip caused by secondary processing is avoided.
Drawings
FIG. 1 is a schematic diagram of a carrier structure according to the present invention;
FIG. 2 is a structural diagram of a carrier plate with a dielectric layer;
FIG. 3 is a top view of a carrier plate according to the present invention;
FIG. 4 is a structural diagram of a carrier pad disposed on a carrier according to the present invention;
FIG. 5 is a structural diagram of a base and a carrier of the present invention;
FIG. 6 is a structural diagram of the base and carrier bonding of the present invention;
FIG. 7 is a block diagram of the dechucking plate of FIG. 6 according to the present invention;
FIG. 8 is a block diagram of a single module of the present invention;
fig. 9 is a structural view of the present invention.
The labels in the figure are: the chip package comprises a carrier plate 101, a functional chip 102, glue 103, a dielectric layer 104, a carrier plate bonding pad 105, a base 201, a substrate 301 and a bonding pad 302.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1 to 9, a radio frequency chip fan-out system-in-package process specifically includes the following steps:
101) a carrier board 101 processing step: the upper surface of the carrier plate 101 is coated with glue 103, the thickness range of the glue 103 is between 100nm and 100um, and the glue 103 is UV glue 103 or hot melt glue 103. The functional chip 102 is bonded to the carrier 101 to form the form shown in fig. 3.
The carrier plate 101 is coated with a dielectric layer 104, the thickness of the dielectric layer 104 ranges from 50um to 500um, and the material thereof is plastic package material, epoxy resin, phenolic resin, silicon oxide or silicon nitride particles. That is, the material may be an organic material such as a molding compound, epoxy resin, or phenol resin, or a viscous material such as silicon oxide or silicon nitride particles, which is used to cover the functional chip 102.
And curing the dielectric layer 104, polishing the surface of the dielectric layer, and exposing the PAD of the chip by photoetching and etching processes. Or directly polishing the surface of the chip, and exposing the PAD of the chip by a dry etching or wet cleaning process.
As shown in fig. 4, the RDL and the carrier PAD 105 are fabricated on the surface of the chip by photolithography and electroplating processes, and then the RDL and the PAD of the chip are connected by windowing by photolithography and dry etching processes. The bonding pad 302 is fabricated on the surface of the carrier 101 by photolithography and electroplating processes. An insulating layer may also be covered on the RDL surface, and a window is opened on the insulating layer to expose the carrier pad 105. The metal of the carrier pad 105 may be copper, aluminum, nickel, silver, gold, tin, etc., and may be one layer or multiple layers, with a thickness ranging from 10nm to 1000 um. Carrier plate pad 105 is windowed to 10um to 10000um diameter.
102) The base 201. TSV holes are manufactured on the upper surface of the base 201 through photoetching and etching processes, the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um. An insulating layer is formed on the upper surface of the base 201 through silicon oxide or silicon nitride deposition or direct thermal oxidation, the thickness of the insulating layer ranges from 10nm to 100um, then a seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the structure of the seed layer is one or more layers, and the metal of the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Copper is electroplated to fill the TSV holes with copper, the copper is densified at a temperature of 200 to 500 ℃, and the copper pillar is formed by leaving only copper on the top surface of the base 201 by a CMP process. The insulating layer on the upper surface of the base 201 can be removed by a dry etching process or a wet etching process. An insulating layer may also remain on the upper surface of the base 201.
The RDL is manufactured on the upper surface of the base 201, the process includes manufacturing an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, the insulating layer is made of silicon oxide or silicon nitride, windowing is conducted through photoetching and dry etching processes, the RDL is connected with the copper columns, the RDL is manufactured on the upper surface of the base 201 through photoetching and electroplating processes, and the RDL comprises a pad 302 with wiring and bonding functions. An insulating layer may also be applied to the surface of the RDL, and a window may be opened in the insulating layer to expose the pad 302. The pad 302 is windowed to 10um to 10000um diameter. The metal of the RDL adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the RDL has a structure of one layer or a plurality of layers, and the thickness of the RDL ranges from 10nm to 1000 um.
The bonding pad is manufactured on the upper surface of the base 201 through photoetching and electroplating processes, the height range of the bonding pad is 10nm to 1000um, the bonding pad adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the structure of the bonding pad is one layer or multiple layers. The bond pad and the RDL are located on the same surface. Here the RDL comprises a thermally conductive metal layer.
The base 201 is made of one of 4, 6, 8 and 12-inch wafers, the thickness range is 200um to 2000um, a silicon wafer is generally adopted, other materials can be adopted, including inorganic materials such as glass, quartz, silicon carbide and aluminum oxide, organic materials such as epoxy resin and polyurethane can be adopted, and the main function of the base is to provide a supporting function.
The lower surface of the base 201 is thinned to expose the TSV hole, and the RDL manufactured on the lower surface of the base 201 is in the same upper surface manufacturing mode as follows: the RDL is formed on the bottom surface of the base 201 by forming an insulating layer with a thickness ranging from 10nm to 1000um, which may be silicon oxide or silicon nitride. And windowing through photoetching and dry etching processes to connect the RDL with one end of the TSV copper column. Through photoetching and electroplating processes, an RDL is manufactured on the lower surface of the base 201, and the RDL comprises a pad with routing and bonding functions.
An insulating layer may be covered on the surface of the RDL, and a window may be formed in the insulating layer to expose the pad. The RDL metal may be copper, aluminum, nickel, silver, gold, tin, etc., and may be one layer or multiple layers, with a thickness ranging from 10nm to 1000 um. The pad 302 is windowed to 10um to 10000um diameter.
Bonding metal is manufactured on the surface of a silicon wafer through photoetching and electroplating processes to form a bonding pad, the height range of the bonding pad is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be one layer or multiple layers, and the thickness range of the bonding pad is 10nm to 1000 um.
Here the bond pad and RDL are on the same side.
103) And (3) packaging: the base 201 and the carrier plate 101 are bonded, the carrier plate 101 is removed, a single module is obtained by cutting, and the single module is placed on the substrate 301 with the bonding pad 302 or the PCB through a welding process to complete the interconnection of the chip and the outside.
Specifically, as shown in fig. 6, a base 201 silicon wafer and a carrier 101 are wafer-level bonded by a eutectic soldering process, and the bonding temperature is controlled to be 200 to 500 degrees.
As shown in fig. 7, the carrier 101 is removed to expose the dielectric layer 104, and the residual glue 103 on the surface of the dielectric layer 104 is cleaned.
As shown in fig. 8, a single die set is obtained by dicing.
As shown in fig. 9, the module is placed on a substrate 301 or PCB board with pads 302 by a soldering process to complete the interconnection of the chip and the outside world.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (5)
1. A radio frequency chip fan-out type system-in-package technology is characterized by comprising the following steps:
101) a carrier plate treatment step: gluing the upper surface of the carrier plate, wherein the thickness of the glue ranges from 100nm to 100um, and bonding the functional chip on the carrier plate;
coating a dielectric layer on the carrier plate, wherein the thickness of the dielectric layer ranges from 50um to 500um, and the material of the dielectric layer is epoxy resin, phenolic resin, silicon oxide or silicon nitride particles;
curing the dielectric layer, polishing the surface of the dielectric layer, and exposing the PAD of the chip by photoetching and etching processes; or directly polishing the surface of the chip, and exposing the PAD of the chip by a dry etching or wet cleaning process;
manufacturing an RDL and a bonding PAD on the surface of the chip through photoetching and electroplating processes, and windowing through photoetching and dry etching processes to connect the RDL with a PAD of the chip; wherein, the bonding pad is manufactured on the surface of the carrier plate through photoetching and electroplating processes; the bonding pad is made of one or more of copper, aluminum, nickel, silver, gold and tin, and has one or more layers with the thickness ranging from 10nm to 1000 um;
102) a base treatment step: manufacturing TSV holes on the upper surface of the base through photoetching and etching processes, wherein the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; forming an insulating layer on the upper surface of the base by depositing silicon oxide or silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer ranges from 10nm to 100um, and then manufacturing a seed layer above the insulating layer by a magnetron sputtering or evaporation process, wherein the thickness of the seed layer ranges from 1nm to 100um, the seed layer is one or more layers, and the metal of the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is electroplated to fill the TSV hole with copper metal, the copper is densified at the temperature of 200-500 ℃, and only copper is left on the upper surface of the base through a CMP process to form a copper column;
manufacturing an RDL on the upper surface of the base, wherein the RDL is manufactured in the process of manufacturing an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, the insulating layer is made of silicon oxide or silicon nitride, windowing is performed through photoetching and dry etching processes to enable the RDL to be connected with the copper column, and the RDL is manufactured on the upper surface of the base through photoetching and electroplating processes and comprises a wiring layer, a heat conduction metal layer and a bonding pad with a bonding function; the RDL adopts one or more of copper, aluminum, nickel, silver, gold and tin as metal, the structure of the RDL is one layer or a plurality of layers, and the thickness range of the RDL is 10nm to 1000 um;
the bonding pad is manufactured on the upper surface of the base through photoetching and electroplating processes, the height range of the bonding pad is 10nm to 1000um, the bonding pad adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the structure of the bonding pad is one layer or multiple layers; the bonding pad and the RDL are positioned on the same surface;
thinning the lower surface of the base to expose the TSV hole, and manufacturing an RDL on the lower surface of the base in the same manner as the upper surface;
103) and (3) packaging: the base and the carrier plate are bonded, the carrier plate is removed, a single module is obtained through cutting, and the single module is placed on a substrate with a bonding pad or a PCB through a welding process to complete interconnection of a chip and the outside.
2. The radio frequency chip fan-out system-in-package process of claim 1, wherein: the glue is UV glue or hot melt glue.
3. The radio frequency chip fan-out system-in-package process of claim 1, wherein: and removing the insulating layer on the upper surface of the base by using a dry etching or wet etching process.
4. The radio frequency chip fan-out system-in-package process of claim 1, wherein: the RDL surface of base upper surface covers the insulating layer, and the position that exposes the pad is windowed on the insulating layer, and the diameter of windowing is 10um to 10000 um.
5. The radio frequency chip fan-out system-in-package process of claim 1, wherein: the base adopts one of 4, 6, 8, 12 cun specification, and the thickness range is 200um to 2000um, adopts silicon chip, glass, quartz, carborundum, aluminium oxide, epoxy or polyurethane.
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| CN201811176817.9A CN110010543B (en) | 2018-10-10 | 2018-10-10 | Radio frequency chip fan-out type system-in-package process |
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| CN110010543B true CN110010543B (en) | 2021-04-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165479A (en) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | Manufacture method of multi-chip and system-level packaging structure |
| CN103534803A (en) * | 2011-05-05 | 2014-01-22 | 英特尔公司 | Radio- and electromagnetic interference through-silicon vias for stacked-die packages, and methods of making same |
| CN105047652A (en) * | 2015-09-01 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device packaging structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103534803A (en) * | 2011-05-05 | 2014-01-22 | 英特尔公司 | Radio- and electromagnetic interference through-silicon vias for stacked-die packages, and methods of making same |
| CN103165479A (en) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | Manufacture method of multi-chip and system-level packaging structure |
| CN105047652A (en) * | 2015-09-01 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device packaging structure and manufacturing method thereof |
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