CN111341668A - Method for embedding radio frequency chip in silicon cavity - Google Patents

Method for embedding radio frequency chip in silicon cavity Download PDF

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Publication number
CN111341668A
CN111341668A CN202010132314.2A CN202010132314A CN111341668A CN 111341668 A CN111341668 A CN 111341668A CN 202010132314 A CN202010132314 A CN 202010132314A CN 111341668 A CN111341668 A CN 111341668A
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cavity
carrier plate
metal
layer
chip
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郁发新
冯光建
王永河
马飞
程明芳
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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Priority to CN202010132314.2A priority Critical patent/CN111341668A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a method for embedding a radio frequency chip in a silicon cavity, which specifically comprises the following steps: 101) a metal column forming step: 102) a cavity manufacturing step, 103) a chip embedding step; the invention provides the embedding method of the radio frequency chip in the silicon cavity, which has the advantages of convenient manufacture and simplified process and can realize the heat dissipation and the grounding interconnection at the bottom of the radio frequency chip.

Description

Method for embedding radio frequency chip in silicon cavity
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for embedding a radio frequency chip in a silicon cavity.
Background
The millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection and imaging and the like, is expected to reach 11 billion dollars in market in 2018, and becomes a new industry. The new application puts new requirements on the electrical performance, compact structure and system reliability of the product, and the wireless transmitting and receiving system cannot be integrated on the same chip (SOC) at present, so that different chips including a radio frequency unit, a filter, a power amplifier and the like need to be integrated into a separate system to realize the functions of transmitting and receiving signals.
In the traditional packaging process, various functional chips and passive devices are mounted on a substrate, so that the occupied area is large, the reliability is poor, and the trend of more and more miniaturization of a packaging system cannot be met.
According to the three-dimensional heterogeneous technology based on the cavity structure, a radio frequency chip is often required to be embedded in the cavity, and the surface interconnection of the PAD and the transfer board of the chip is facilitated. However, the bottom of the radio frequency chip needs to be subjected to heat dissipation and grounding interconnection, so that the bottom of the chip needs to be contacted with a TSV copper column. For the structure that the radio frequency chip is embedded into the silicon cavity, if the TSV is made first, the cavity needs to be made on the back of the adapter plate, the bottom of the cavity is made at the bottom of the TSV, then interconnection is made, the depths of the TSV have differences, and the bottom made in this way is uneven and not beneficial to grounding interconnection of the chip.
Disclosure of Invention
The invention overcomes the defects of the prior art, and provides the embedding method of the radio frequency chip in the silicon cavity, which has the advantages of convenient manufacture, simplified process and realization of heat dissipation and grounding interconnection at the bottom of the radio frequency chip.
The technical scheme of the invention is as follows:
a method for embedding a radio frequency chip in a silicon cavity specifically comprises the following steps:
101) a metal column forming step: through photoetching and etching processes, TSV holes are formed in the lower surface of a carrier plate with an SOI layer, silicon oxide or silicon nitride is deposited on the lower surface of the carrier plate, or an insulating layer is formed through direct thermal oxidation; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process, electroplating metal to fill the TSV hole with the metal to form a metal column, and densifying the metal column at a temperature of 200-500 ℃ to make the metal column more dense; removing the metal on the upper surface of the carrier plate by a CMP process, so that only the filled metal is left on the upper surface of the carrier plate;
102) a cavity manufacturing step: thinning the upper surface of the carrier plate, wherein the thinned thickness is between 100nm and 700 um; the thinning treatment is directly carried out on the back of the carrier plate, or the surface of the carrier plate, which is provided with the TSV holes, is protected by a temporary bonding process, and then a slide glass is used for supporting the back of the thinned carrier plate;
performing dry etching or wet etching on the surface of the TSV hole region arranged on the upper surface of the carrier plate by using a dry etching process to form a cavity; the overall shape of the cavity is square, round, oval or triangular, and the side wall of the cavity is arranged vertically or obliquely; wherein, the cavity is corroded and stopped at the SOI layer of the carrier plate;
the conversion gas continuously etches the SOI layer and the carrier plate to expose the metal column;
103) chip embedding: embedding the chip with solder on the surface into the cavity, and heating to interconnect the solder and the metal column; and filling glue in gaps between the chip and the cavity by using a bottom glue filling or surface spin coating process, and removing residual glue on the surface of the chip by using a dry etching or wet etching process after curing to obtain the structure of embedding the radio frequency chip in the silicon cavity.
Furthermore, the diameter range of the TSV hole is between 1um and 1000um, and the depth of the TSV hole is between 10um and 1000 um; the thickness of the insulating layer ranges from 10nm to 100 um; the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Furthermore, the size of the carrier plate is one of 4, 6, 8 and 12 inches, the thickness of the carrier plate is 200um to 2000um, and the carrier plate is made of one of silicon, glass, quartz, silicon carbide, aluminum oxide, epoxy resin or polyurethane.
Further, the TSV hole in the step 101) is etched to stay at the SOI layer, and then the gas exchange is carried out to continue etching so that the bottom of the TSV penetrates through the SOI layer.
Compared with the prior art, the invention has the advantages that: according to the invention, the carrier plate with the SOI layer is used as the base material, the etching process is optimized, and the silicon oxide layer in the SOI layer is used as the barrier layer, so that the height and the flatness of the TSV copper column at the bottom of the cavity are greatly increased, and the bottom of the radio frequency chip is efficiently contacted with the TSV copper column.
Drawings
Fig. 1 is a schematic view of a carrier according to the present invention;
FIG. 2 is a schematic diagram of the TSV hole made in FIG. 1 according to the present invention;
FIG. 3 is a schematic diagram of the present invention for fabricating metal pillars on FIG. 2;
FIG. 4 is a schematic illustration of the cavity created in FIG. 3 according to the present invention;
FIG. 5 is a schematic view of the invention showing the bottom of the metal pillar exposed in FIG. 4;
FIG. 6 is a schematic diagram of the present invention showing the chip disposed on FIG. 5;
FIG. 7 is a schematic illustration of the application of glue of FIG. 6 in accordance with the present invention;
FIG. 8 is a schematic view of the present invention;
fig. 9 is a schematic diagram of a carrier board provided with TSV holes through an SOI layer according to the present invention;
FIG. 10 is a schematic view of the present invention illustrating the fabrication of metal pillars on FIG. 9;
FIG. 11 is a schematic view of the present invention showing the metal pillar exposed by the cavity formed in FIG. 10;
FIG. 12 is a schematic diagram of the present invention showing the chip mounted on FIG. 11;
FIG. 13 is a schematic illustration of the application of glue of FIG. 12 in accordance with the present invention;
fig. 14 is another schematic of the present invention.
The labels in the figure are: the structure comprises a carrier plate 101, an SOI layer 102, TSV holes 103, metal pillars 104, a cavity 105, a chip 107 and glue 108.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1 to 8, a method for embedding a radio frequency chip in a silicon cavity specifically includes the following steps:
101) a metal column forming step: through photoetching and etching processes, TSV holes 103 are formed in the lower surface of a carrier plate 101 with an SOI layer 102, the diameter range of the TSV holes 103 is 1um to 1000um, and the depth of the TSV holes 103 is 10um to 1000 um. Depositing silicon oxide or silicon nitride on the lower surface of the carrier plate 101, or directly thermally oxidizing to form an insulating layer; the thickness of the insulating layer ranges between 10nm and 100 um. A seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like. Electroplating metal to fill the TSV hole 103 with the metal to form a metal column 104, and densifying the metal column 104 at a temperature of 200 to 500 ℃ to make the metal column 104 denser; the metal on the upper surface of the carrier plate 101 is removed by a CMP process, so that only the filled metal remains on the upper surface of the carrier plate 101. The metal is usually copper, and the insulating layer on the lower surface of the carrier 101 may be removed by dry etching or wet etching, and may naturally remain.
102) A cavity manufacturing step: thinning the upper surface of the carrier plate 101, wherein the thinned thickness is between 100nm and 700 um; the thinning is directly performed on the back of the carrier plate 101, or a temporary bonding process is used for protecting one surface of the carrier plate 101, which is provided with the TSV holes 103, and a carrier sheet is used for supporting the back of the thinned carrier plate 101.
Performing dry etching or wet etching on the surface of the region where the TSV hole 103 is formed in the upper surface of the carrier plate 101 by using a dry etching process to form a cavity 105; the overall shape of the cavity 105 is square, circular, oval or triangular, and the side wall of the cavity 105 is arranged vertically or obliquely; wherein the cavity 105 etches the SOI layer 102 that stops at the carrier 101. The switching gas continues to etch the SOI layer 102 and the carrier 101, exposing the metal pillars 104.
103) Chip embedding: the chip 107 with solder on its surface is embedded in the cavity 105 and heated to interconnect the solder with the metal pillar 104. And filling the gap between the chip 107 and the cavity 105 with glue 108 through a bottom filling process 108 or a surface spin coating process, and removing residual glue 108 on the surface of the chip 107 through a dry etching or wet etching process after curing to obtain the structure of embedding the radio frequency chip 107 in the silicon cavity 105.
Wherein, support plate 101 size is one of 4, 6, 8, 12 cun, and support plate 101 thickness is 200um to 2000um, and the material that its adopted is one in silicon, glass, quartz, carborundum, aluminium oxide, epoxy or polyurethane.
Example 2:
as shown in fig. 9 to 14, the embodiment 2 is different from the embodiment 1 in that the TSV hole 103 in the step 101) is etched to stay in the SOI layer 102, and then the gas exchange etching is continued to make the bottom of the TSV penetrate through the SOI layer 102. The other processes are the same. The method comprises the following specific steps:
a method for embedding a radio frequency chip in a silicon cavity specifically comprises the following steps:
101) a metal column forming step: through photoetching and etching processes, TSV holes 103 are formed in the lower surface of a carrier plate 101 with an SOI layer 102, the diameter range of the TSV holes 103 is 1um to 1000um, and the depth of the TSV holes 103 is 10um to 1000 um. The TSV 103 is etched to stay on the SOI layer 102, and then the gas is exchanged to continue etching so that the bottom of the TSV penetrates through the SOI layer 102.
Depositing silicon oxide or silicon nitride on the lower surface of the carrier plate 101, or directly thermally oxidizing to form an insulating layer; the thickness of the insulating layer ranges between 10nm and 100 um. A seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like. Electroplating metal to fill the TSV hole 103 with the metal to form a metal column 104, and densifying the metal column 104 at a temperature of 200 to 500 ℃ to make the metal column 104 denser; the metal on the upper surface of the carrier plate 101 is removed by a CMP process, so that only the filled metal remains on the upper surface of the carrier plate 101. The metal is usually copper, and the insulating layer on the lower surface of the carrier 101 may be removed by dry etching or wet etching, and may naturally remain.
102) A cavity manufacturing step: thinning the upper surface of the carrier plate 101, wherein the thinned thickness is between 100nm and 700 um; the thinning is directly performed on the back of the carrier plate 101, or a temporary bonding process is used for protecting one surface of the carrier plate 101, which is provided with the TSV holes 103, and a carrier sheet is used for supporting the back of the thinned carrier plate 101.
Performing dry etching or wet etching on the surface of the region where the TSV hole 103 is formed in the upper surface of the carrier plate 101 by using a dry etching process to form a cavity 105; the overall shape of the cavity 105 is square, circular, oval or triangular, and the side wall of the cavity 105 is arranged vertically or obliquely; wherein the cavity 105 etches the SOI layer 102 that stops at the carrier 101.
103) Chip embedding: the chip 107 with solder on its surface is embedded in the cavity 105 and heated to interconnect the solder with the metal pillar 104. And filling the gap between the chip 107 and the cavity 105 with glue 108 through a bottom filling process 108 or a surface spin coating process, and removing residual glue 108 on the surface of the chip 107 through a dry etching or wet etching process after curing to obtain the structure of embedding the radio frequency chip 107 in the silicon cavity 105.
Wherein, support plate 101 size is one of 4, 6, 8, 12 cun, and support plate 101 thickness is 200um to 2000um, and the material that its adopted is one in silicon, glass, quartz, carborundum, aluminium oxide, epoxy or polyurethane.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.

Claims (4)

1. A method for embedding a radio frequency chip in a silicon cavity is characterized by comprising the following steps:
101) a metal column forming step: through photoetching and etching processes, TSV holes are formed in the lower surface of a carrier plate with an SOI layer, silicon oxide or silicon nitride is deposited on the lower surface of the carrier plate, or an insulating layer is formed through direct thermal oxidation; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process, electroplating metal to fill the TSV hole with the metal to form a metal column, and densifying the metal column at a temperature of 200-500 ℃ to make the metal column more dense; removing the metal on the upper surface of the carrier plate by a CMP process, so that only the filled metal is left on the upper surface of the carrier plate;
102) a cavity manufacturing step: thinning the upper surface of the carrier plate, wherein the thinned thickness is between 100nm and 700 um; the thinning treatment is directly carried out on the back of the carrier plate, or the surface of the carrier plate, which is provided with the TSV holes, is protected by a temporary bonding process, and then a slide glass is used for supporting the back of the thinned carrier plate;
performing dry etching or wet etching on the surface of the TSV hole region arranged on the upper surface of the carrier plate by using a dry etching process to form a cavity; the overall shape of the cavity is square, round, oval or triangular, and the side wall of the cavity is arranged vertically or obliquely; wherein, the cavity is corroded and stopped at the SOI layer of the carrier plate;
the conversion gas continuously etches the SOI layer and the carrier plate to expose the metal column;
103) chip embedding: embedding the chip with solder on the surface into the cavity, and heating to interconnect the solder and the metal column; and filling glue in gaps between the chip and the cavity by using a bottom glue filling or surface spin coating process, and removing residual glue on the surface of the chip by using a dry etching or wet etching process after curing to obtain the structure of embedding the radio frequency chip in the silicon cavity.
2. The method of claim 1, wherein the TSV hole has a diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000 um; the thickness of the insulating layer ranges from 10nm to 100 um; the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
3. The method of claim 1, wherein the carrier has a size of 4, 6, 8, or 12 inches, a thickness of 200um to 2000um, and is made of one of silicon, glass, quartz, silicon carbide, alumina, epoxy resin, or polyurethane.
4. The method as claimed in claim 1, wherein the TSV hole in step 101) is etched to stay in the SOI layer, and then the gas exchange etching is continued to make the bottom of the TSV penetrate through the SOI layer.
CN202010132314.2A 2020-02-29 2020-02-29 Method for embedding radio frequency chip in silicon cavity Pending CN111341668A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111952196A (en) * 2020-08-24 2020-11-17 浙江集迈科微电子有限公司 Groove chip embedding process
CN111952243A (en) * 2020-08-24 2020-11-17 浙江集迈科微电子有限公司 Groove chip embedding process

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895579A (en) * 2016-06-08 2016-08-24 无锡微奥科技有限公司 Silicon on insulator (SOI) substrate based processing method of TSV wafer
US20190393191A1 (en) * 2016-12-27 2019-12-26 Intel IP Corporation Packages of stacking integrated circuits
CN111243970A (en) * 2020-02-28 2020-06-05 浙江集迈科微电子有限公司 Chip embedding process in cavity

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895579A (en) * 2016-06-08 2016-08-24 无锡微奥科技有限公司 Silicon on insulator (SOI) substrate based processing method of TSV wafer
US20190393191A1 (en) * 2016-12-27 2019-12-26 Intel IP Corporation Packages of stacking integrated circuits
CN111243970A (en) * 2020-02-28 2020-06-05 浙江集迈科微电子有限公司 Chip embedding process in cavity

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111952196A (en) * 2020-08-24 2020-11-17 浙江集迈科微电子有限公司 Groove chip embedding process
CN111952243A (en) * 2020-08-24 2020-11-17 浙江集迈科微电子有限公司 Groove chip embedding process
CN111952243B (en) * 2020-08-24 2023-04-07 浙江集迈科微电子有限公司 Groove chip embedding process
CN111952196B (en) * 2020-08-24 2024-04-26 浙江集迈科微电子有限公司 Groove chip embedding process

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