CN111952194A - Liquid cooling heat dissipation process for radio frequency chip - Google Patents
Liquid cooling heat dissipation process for radio frequency chip Download PDFInfo
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- CN111952194A CN111952194A CN202010855293.7A CN202010855293A CN111952194A CN 111952194 A CN111952194 A CN 111952194A CN 202010855293 A CN202010855293 A CN 202010855293A CN 111952194 A CN111952194 A CN 111952194A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
The invention provides a liquid cooling heat dissipation process of a radio frequency chip, which comprises the following steps: (a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable metal to fill the TSVs, manufacturing an RDL (remote description language) and a bonding pad, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottoms of the long TSVs to be exposed, and obtaining a first substrate; (b) etching a cavity on the back of the first substrate to expose the metal at the bottom of the TSV, embedding a chip into the cavity, and manufacturing an RDL and a bonding pad on the back of the first substrate; (c) etching the cavity on the substrate surface on the back of the chip to the bottom of the chip, and continuing to etch to enable the cavity to reach the inside of the chip, so that the cavity directly reaches the heat dissipation area of the chip, and obtaining a first substrate; (d) and forming a final structure with micro-channel heat dissipation. According to the liquid-cooling heat dissipation process for the radio frequency chip, the groove is directly formed in the bottom of the chip heating device in a mode of forming the groove in the bottom of the substrate, heat of the chip can be rapidly transferred through the liquid-cooling heat dissipation channel, and the heat dissipation capacity of a system is greatly improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a liquid cooling heat dissipation process for a radio frequency chip.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
However, for a high-frequency micro-system, the area of the antenna array is smaller and smaller, and the distance between the antennas needs to be kept within a certain range, so that the whole module has excellent communication capability. However, for an analog device chip such as a radio frequency chip, the area of the analog device chip cannot be reduced by the same magnification as that of a digital chip, so that a radio frequency micro system with a very high frequency will not have enough area to simultaneously place the PA/LNA, and the PA/LNA needs to be stacked or vertically placed.
Therefore, the heat dissipation structure needs to adopt a more advanced liquid cooling or phase change refrigeration process, a metal processing mode is generally used as a base of the radio frequency module, a micro-flow channel is arranged in the base, and the module is fixed on the metal base by adopting a welding process to complete the placement of the chip. However, in the stacking technology, the heat on the power chip needs to be transferred to the heat dissipation liquid through several layers of media, and the efficiency is low.
In order to further reduce the distance between the heat dissipation micro-channel and the heat-generating chip, the current trend is to use a semiconductor as the micro-channel and interconnect the semiconductor and the heat-generating chip through a bonding process, so that the heat dissipation efficiency of the chip can be greatly increased.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a liquid cooling heat dissipation process for a radio frequency chip, and improves the heat dissipation capacity of the chip. The technical scheme adopted by the invention is as follows:
a liquid cooling heat dissipation process for a radio frequency chip comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottom of the long TSV to be exposed, and obtaining a first substrate;
(b) etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the cavity, exposing the bottom of the TSV through exposure and development, etching the passivation layer to expose metal at the bottom of the TSV, embedding a chip into the cavity, and manufacturing an RDL (remote description language) and a bonding pad on the back of the first substrate;
(c) removing the temporary bonding on the front side of the substrate, performing temporary bonding on the back side of the substrate, etching the cavity on the substrate surface on the back side of the chip to the bottom of the chip, continuing etching to enable the cavity to reach the interior of the chip, and enabling the cavity to reach the heat dissipation area of the chip directly to obtain a second substrate;
(d) and forming a final structure with micro-channel heat dissipation.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(a1) manufacturing TSV with different depths on the front side of the substrate through photoetching and etching processes;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer;
(a3) electroplating copper to enable the TSV to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
(a5) and carrying out temporary bonding on the front side of the substrate, then thinning the back side of the substrate to expose the TSV, carrying out passivation layer on the back side, polishing to expose the metal of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(b1) etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(b3) removing the photoresist, cleaning the substrate, and debonding;
(b4) coating an adhesive layer at the bottom of the cavity, soldering tin or melting a gold-tin solder sheet, embedding the chip, and filling a gap part between the chip and the cavity with colloid;
(b5) and manufacturing the RDL and the bonding pad on the back of the first substrate.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(c1) removing the temporary bonding on the front surface of the substrate, coating temporary bonding glue on the back surface of the chip, and then performing temporary bonding;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) continuously etching the passivation layer and the adhesive layer at the bottom of the chip to enable the cavity to reach the bottom of the chip directly;
(c4) and continuing etching to enable the cavity to reach the inside of the chip and reach the heat dissipation area of the chip, and obtaining a second substrate.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(c1) removing the temporary bonding on the front surface of the substrate, coating temporary bonding glue on the back surface of the chip, and then performing temporary bonding;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) continuously etching the passivation layer and the adhesive layer at the bottom of the chip to enable the cavity to reach the bottom of the chip directly;
(c4) and continuously etching the cavity in the region outside the chip, and continuously etching the cavity at the bottom of the chip to reach the inside of the chip and reach the heat dissipation region of the chip to obtain a second substrate.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(c1) removing the temporary bonding on the front surface of the substrate, coating temporary bonding glue on the back surface of the chip, and then performing temporary bonding;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) and continuously etching to enable the cavity to reach the surface of the chip and to transversely penetrate through the whole chip to obtain a second substrate.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(d1) providing a TSV adapter plate with a groove and a pad structure, and bonding the TSV adapter plate with a second substrate to form a closed micro-channel region;
(d2) etching a liquid inlet and a liquid outlet at the bottom of the TSV adapter plate to enable the sealed micro-channel area to be communicated with the outside to obtain a third substrate;
(d3) and cutting the third substrate to obtain a single module, and fixing the module on the substrate to form a final structure with micro-channel heat dissipation.
Preferably, the liquid cooling heat dissipation process for the radio frequency chip includes the following specific steps:
(d1) manufacturing a metal module with a micro-channel;
(d2) embedding a metal module with a micro-channel into the cavity of the second substrate to enable the surface of the metal module to be in contact with the bottom of the cavity, then planting balls on a bonding pad on the front side of the first substrate to obtain a third substrate, and welding the third substrate and a base material to form a final structure with micro-channel heat dissipation.
The invention has the advantages that: according to the liquid cooling heat dissipation process for the radio frequency chip, the groove is directly formed at the bottom of the chip heating device by the mode of forming the groove at the bottom of the substrate, and then the heat of the chip can be rapidly transferred out by connecting the material with strong heat conduction capability and the liquid cooling heat dissipation channel formed by the material, so that the heat dissipation capability of the system is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a substrate etching TSV hole of the invention.
Fig. 2 is a schematic diagram of a metal-filled TSV according to the present invention.
Fig. 3 is a schematic view of a first substrate of the present invention.
FIG. 4 is a schematic diagram of a first substrate backside etch cavity of the present invention.
Fig. 5 is a schematic diagram illustrating the TSV bottom metal exposure according to the present invention.
Fig. 6 is a schematic diagram of temporary bonding of the back side of a substrate according to embodiment 1 of the present invention.
FIG. 7 is a schematic diagram of etching a cavity from the substrate side to the bottom of the chip according to embodiment 1 of the present invention.
FIG. 8 is a schematic diagram of embodiment 1 of the present invention showing the cavity reaching the bottom of the chip.
Fig. 9 is a schematic view of a second substrate of embodiment 1 of the present invention.
Fig. 10 is a schematic diagram of bonding a TSV interposer and a second substrate according to embodiment 1 of the present invention.
Fig. 11 is a schematic view of a third substrate in embodiment 1 of the present invention.
FIG. 12 is a schematic diagram of a final structure with micro channels for heat dissipation in example 1 of the present invention.
FIG. 13 is a schematic diagram of etching a cavity from the substrate side to the bottom of a chip in example 2 of the present invention.
Fig. 14 is a schematic view of embodiment 2 of the invention showing the cavity reaching the bottom of the chip.
Fig. 15 is a schematic view of a second substrate according to embodiment 2 of the present invention.
Fig. 16 is a schematic diagram of bonding a TSV interposer and a first substrate according to embodiment 2 of the present invention.
Fig. 17 is a schematic diagram of a final structure with micro channels for heat dissipation in embodiment 2 of the present invention.
Fig. 18 is a schematic view of a second substrate of embodiment 3 of the present invention.
FIG. 19 is a schematic view showing the structure of a mold block with microchannels according to example 3 of the present invention.
Fig. 20 is a schematic diagram of a final structure with micro channels for heat dissipation in embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
The first embodiment;
a liquid cooling heat dissipation process for a radio frequency chip comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottom of the long TSV to be exposed, and obtaining a first substrate;
the specific steps of the step (a) are as follows:
(a1) as shown in fig. 1, TSVs 102 with different depths are manufactured on the front surface of a substrate 101 through photolithography and etching processes, wherein the deep holes have a diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000 um;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer, wherein the insulating layer is made of silicon oxide or silicon nitride or is directly thermally oxidized, and the thickness of the insulating layer is in the range of 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) as shown in fig. 2, copper is electroplated, densification at a temperature of 200 to 500 degrees to make the copper denser; the copper CMP process removes the copper on the surface of the substrate, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by a dry etching or wet etching process; the insulating layer on the surface of the substrate can also be reserved;
(a4) manufacturing an RDL and a bonding pad 104 on the front side of the substrate through photoetching and electroplating processes;
firstly, a seed layer is manufactured above an insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, then RDL and a pad position are defined through photoetching, RDL and pad metal are manufactured through electroplating, the thickness of the metal ranges from 1um to 100um, the metal material can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a5) as shown in fig. 3, the front side of the substrate is temporarily bonded, the back side of the substrate is thinned to expose the TSV, a passivation layer is formed on the back side, the TSV metal is exposed by polishing, and then the RDL and the bonding pad are manufactured to obtain the first substrate.
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the cavity, exposing the bottom of the TSV through exposure and development, etching the passivation layer to expose metal at the bottom of the TSV, embedding a chip into the cavity, and manufacturing an RDL (remote description language) and a bonding pad on the back of the first substrate;
the specific steps of the step (b) are as follows:
(b1) as shown in fig. 4, a cavity 105 is etched on the back surface of the first substrate in a photoetching and dry etching manner, wherein the depth of the cavity is 10um to 1000um, so that the bottom of the short TSV is exposed; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) as shown in fig. 5, depositing a passivation layer 106, wherein the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, the thickness of the passivation layer ranges from 10nm to 100um, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose the metal at the bottom of the TSV;
(b3) removing the photoresist, cleaning the substrate, and debonding;
(b4) coating an adhesive layer at the bottom of the cavity, soldering tin or melting a gold-tin solder sheet, embedding the chip, and filling a gap part between the chip and the cavity with colloid;
(b5) and manufacturing the RDL and the bonding pad on the back of the first substrate.
(c) Removing the temporary bonding on the front side of the substrate, performing temporary bonding on the back side of the substrate, etching the cavity on the substrate surface on the back side of the chip to the bottom of the chip, continuing etching to enable the cavity to reach the interior of the chip, and enabling the cavity to reach the heat dissipation area of the chip directly to obtain a second substrate;
the specific steps of the step (c) are as follows:
(c1) as shown in fig. 6, the temporary bonding on the front side of the substrate is removed, the temporary bonding glue 109 is coated on the back side of the substrate, and then the temporary bonding is performed;
(c2) as shown in fig. 7, the cavity 110 is etched on the substrate surface of the back surface of the chip to the bottom of the chip, and the depth of the etched cavity is 10um to 1000 um;
(c3) as shown in fig. 8, the passivation layer and the adhesive layer at the bottom of the chip are etched continuously to make the cavity reach the bottom of the chip;
(c4) as shown in fig. 9, the etching is continued to make the cavity reach the inside of the chip and reach the heat dissipation area of the chip, and a second substrate is obtained.
(d) And forming a final structure with micro-channel heat dissipation.
The specific steps of the step (d) are as follows:
(d1) as shown in fig. 10, providing a TSV interposer with a groove and a pad structure, and bonding the TSV interposer and a second substrate to form a closed microchannel region;
(d2) as shown in fig. 11, a liquid inlet and a liquid outlet are etched at the bottom of the TSV interposer, so that the closed microchannel region is communicated with the outside, and a third substrate is obtained;
(d3) as shown in fig. 12, the third substrate is diced to obtain a single module, and the module is fixed on the substrate to form a final structure with micro-channels for heat dissipation.
Example 2:
a liquid cooling heat dissipation process for a radio frequency chip comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottom of the long TSV to be exposed, and obtaining a first substrate;
the specific steps of the step (a) are as follows:
(a1) as shown in fig. 1, TSVs 102 with different depths are manufactured on the front surface of a substrate 101 through photolithography and etching processes, wherein the deep holes have a diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000 um;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer, wherein the insulating layer is made of silicon oxide or silicon nitride or is directly thermally oxidized, and the thickness of the insulating layer is in the range of 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) as shown in fig. 2, copper is electroplated, densification at a temperature of 200 to 500 degrees to make the copper denser; the copper CMP process removes the copper on the surface of the substrate, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by a dry etching or wet etching process; the insulating layer on the surface of the substrate can also be reserved;
(a4) manufacturing an RDL and a bonding pad 104 on the front side of the substrate through photoetching and electroplating processes;
firstly, a seed layer is manufactured above an insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, then RDL and a pad position are defined through photoetching, RDL and pad metal are manufactured through electroplating, the thickness of the metal ranges from 1um to 100um, the metal material can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a5) as shown in fig. 3, the front side of the substrate is temporarily bonded, the back side of the substrate is thinned to expose the TSV, a passivation layer is formed on the back side, the TSV metal is exposed by polishing, and then the RDL and the bonding pad are manufactured to obtain the first substrate.
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the cavity, exposing the bottom of the TSV through exposure and development, etching the passivation layer to expose metal at the bottom of the TSV, embedding a chip into the cavity, and manufacturing an RDL (remote description language) and a bonding pad on the back of the first substrate;
the specific steps of the step (b) are as follows:
(b1) as shown in fig. 4, a cavity 105 is etched on the back surface of the first substrate in a photoetching and dry etching manner, wherein the depth of the cavity is 10um to 1000um, so that the bottom of the short TSV is exposed; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) as shown in fig. 5, depositing a passivation layer 106, wherein the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, the thickness of the passivation layer ranges from 10nm to 100um, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose the metal at the bottom of the TSV;
(b3) removing the photoresist, cleaning the substrate, and debonding;
(b4) coating an adhesive layer at the bottom of the cavity, soldering tin or melting a gold-tin solder sheet, embedding the chip, and filling a gap part between the chip and the cavity with colloid;
(b5) and manufacturing the RDL and the bonding pad on the back of the first substrate.
(c) Removing the temporary bonding on the front side of the substrate, performing temporary bonding on the back side of the chip, etching the cavity on the substrate side of the back side of the chip to the bottom of the chip, continuing etching to enable the cavity to reach the interior of the chip, and enabling the cavity to reach the heat dissipation area of the chip directly to obtain a first substrate;
the specific steps of the step (c) are as follows:
(c1) as shown in fig. 6, the temporary bonding on the front side of the substrate is removed, the temporary bonding 109 is coated on the back side of the chip, and then the temporary bonding is performed;
(c2) as shown in fig. 13, the cavity is etched from the substrate surface of the back surface of the chip to the bottom of the chip, and the depth of the etched cavity is 10um to 1000 um;
(c3) as shown in fig. 14, the passivation layer and the adhesive layer on the bottom of the chip are etched continuously to make the cavity reach the bottom of the chip;
(c4) as shown in fig. 15, the cavity is etched continuously in the region outside the chip, and the cavity at the bottom of the chip is etched continuously to reach the inside of the chip and reach the heat dissipation region of the chip, so as to obtain the second substrate.
(d) And forming a final structure with micro-channel heat dissipation.
The specific steps of the step (d) are as follows:
(d1) as shown in fig. 16, providing a TSV interposer with a groove and a pad structure, and bonding the TSV interposer and a second substrate to form a closed microchannel region;
(d2) etching a liquid inlet and a liquid outlet at the bottom of the TSV adapter plate to enable the sealed micro-channel area to be communicated with the outside to obtain a third substrate;
(d3) as shown in fig. 17, the third substrate is diced to obtain a single module, and the module is fixed on the substrate to form a final structure with micro-channels for heat dissipation. The substrate is made of a PCB or other materials.
Example 3:
a liquid cooling heat dissipation process for a radio frequency chip comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottom of the long TSV to be exposed, and obtaining a first substrate;
the specific steps of the step (a) are as follows:
(a1) as shown in fig. 1, TSVs 102 with different depths are manufactured on the front surface of a substrate 101 through photolithography and etching processes, wherein the deep holes have a diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000 um;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer, wherein the insulating layer is made of silicon oxide or silicon nitride or is directly thermally oxidized, and the thickness of the insulating layer is in the range of 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) as shown in fig. 2, copper is electroplated, densification at a temperature of 200 to 500 degrees to make the copper denser; the copper CMP process removes the copper on the surface of the substrate, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by a dry etching or wet etching process; the insulating layer on the surface of the substrate can also be reserved;
(a4) manufacturing an RDL and a bonding pad 104 on the front side of the substrate through photoetching and electroplating processes;
firstly, a seed layer is manufactured above an insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, then RDL and a pad position are defined through photoetching, RDL and pad metal are manufactured through electroplating, the thickness of the metal ranges from 1um to 100um, the metal material can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a5) as shown in fig. 3, the front side of the substrate is temporarily bonded, the back side of the substrate is thinned to expose the TSV, a passivation layer is formed on the back side, the TSV metal is exposed by polishing, and then the RDL and the bonding pad are manufactured to obtain the first substrate.
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the cavity, exposing the bottom of the TSV through exposure and development, etching the passivation layer to expose metal at the bottom of the TSV, embedding a chip into the cavity, and manufacturing an RDL (remote description language) and a bonding pad on the back of the first substrate;
the specific steps of the step (b) are as follows:
(b1) as shown in fig. 4, a cavity 105 is etched on the back surface of the first substrate in a photoetching and dry etching manner, wherein the depth of the cavity is 10um to 1000um, so that the bottom of the short TSV is exposed; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) as shown in fig. 5, depositing a passivation layer 106, wherein the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, the thickness of the passivation layer ranges from 10nm to 100um, coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose the metal at the bottom of the TSV;
(b3) removing the photoresist, cleaning the substrate, and debonding;
(b4) coating an adhesive layer at the bottom of the cavity, soldering tin or melting a gold-tin solder sheet, embedding the chip, and filling a gap part between the chip and the cavity with colloid;
(b5) and manufacturing the RDL and the bonding pad on the back of the first substrate.
(c) Removing the temporary bonding on the front side of the substrate, performing temporary bonding on the back side of the substrate, etching the cavity on the substrate surface on the back side of the chip to the bottom of the chip, continuing etching to enable the cavity to reach the interior of the chip, and enabling the cavity to reach the heat dissipation area of the chip directly to obtain a second substrate;
the specific steps of the step (c) are as follows:
(c1) as shown in fig. 18, the temporary bonding on the front side of the substrate is removed, the temporary bonding glue is coated on the back side of the chip, and then the temporary bonding is performed;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) and continuously etching to enable the cavity to reach the surface of the chip and to transversely penetrate through the whole chip to obtain a second substrate.
(d) And forming a final structure with micro-channel heat dissipation.
The specific steps of the step (d) are as follows:
(d1) as shown in fig. 19, a metal module with micro channels is manufactured, the module may be a single layer or a plurality of layers, and the metal material may be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, or the like;
(d2) as shown in fig. 20, a metal module with a microchannel is embedded in the cavity of the second substrate, so that the surface of the metal module contacts with the bottom of the cavity, then a pad is mounted on the front surface of the second substrate to obtain a third substrate, and the third substrate is welded with the base material to form a final structure with microchannel heat dissipation.
According to the liquid cooling heat dissipation process for the radio frequency chip, the groove is directly formed at the bottom of the chip heating device by the mode of forming the groove at the bottom of the substrate, and then the heat of the chip can be rapidly transferred out by connecting the material with strong heat conduction capability and the liquid cooling heat dissipation channel formed by the material, so that the heat dissipation capability of the system is greatly improved.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (8)
1. A liquid cooling heat dissipation process for a radio frequency chip is characterized by comprising the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the lower part of the long TSV to be exposed, and obtaining a first substrate;
(b) etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the cavity, exposing the bottom of the TSV through exposure and development, etching the passivation layer to expose metal at the bottom of the TSV, embedding a chip into the cavity, and manufacturing an RDL (remote description language) and a bonding pad on the back of the first substrate;
(c) removing the temporary bonding on the front side of the substrate, performing temporary bonding on the back side of the substrate, etching the cavity on the substrate surface on the back side of the chip to the bottom of the chip, continuing etching to enable the cavity to reach the interior of the chip, and enabling the cavity to reach the heat dissipation area of the chip directly to obtain a second substrate;
(d) and forming a final structure with micro-channel heat dissipation.
2. The liquid cooling heat dissipation process for the radio frequency chip as claimed in claim 1, wherein the specific steps of the step (a) are as follows:
(a1) manufacturing TSV with different depths on the front side of the substrate through photoetching and etching processes;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer;
(a3) electroplating copper to enable the TSV to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
(a5) and carrying out temporary bonding on the front side of the substrate, then thinning the back side of the substrate to expose the TSV, carrying out passivation layer on the back side, polishing to expose the metal of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
3. The liquid cooling heat dissipation process for the radio frequency chip as claimed in claim 1, wherein the step (b) comprises the following steps:
(b1) etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(b3) removing the photoresist, cleaning the substrate, and debonding;
(b4) coating an adhesive layer at the bottom of the cavity, soldering tin or melting a gold-tin solder sheet, embedding the chip, and filling a gap part between the chip and the cavity with colloid;
(b5) and manufacturing the RDL and the bonding pad on the back of the first substrate.
4. The liquid cooling heat dissipation process for the radio frequency chip as claimed in claim 1, wherein the specific steps of the step (c) are as follows:
(c1) removing the temporary bonding on the front surface of the substrate, coating temporary bonding glue on the back surface of the chip, and then performing temporary bonding;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) continuously etching the passivation layer and the adhesive layer at the bottom of the chip to enable the cavity to reach the bottom of the chip directly;
(c4) and continuing etching to enable the cavity to reach the inside of the chip and reach the heat dissipation area of the chip, and obtaining a second substrate.
5. The liquid cooling heat dissipation process for the radio frequency chip as claimed in claim 1, wherein the specific steps of the step (c) are as follows:
(c1) removing the temporary bonding on the front surface of the substrate, coating temporary bonding glue on the back surface of the chip, and then performing temporary bonding;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) continuously etching the passivation layer and the adhesive layer at the bottom of the chip to enable the cavity to reach the bottom of the chip directly;
(c4) and continuously etching the cavity in the region outside the chip, and continuously etching the cavity at the bottom of the chip to reach the inside of the chip and reach the heat dissipation region of the chip to obtain a second substrate.
6. The liquid cooling heat dissipation process for the radio frequency chip as claimed in claim 1, wherein the specific steps of the step (c) are as follows:
(c1) removing the temporary bonding on the front surface of the substrate, coating temporary bonding glue on the back surface of the chip, and then performing temporary bonding;
(c2) etching a cavity from the substrate surface on the back of the chip to the bottom of the chip, wherein the depth of the etched cavity is 10um to 1000 um;
(c3) and continuously etching to enable the cavity to reach the surface of the chip and to transversely penetrate through the whole chip to obtain a second substrate.
7. The liquid cooling heat dissipation process for the radio frequency chip as claimed in claim 4 or 5, wherein the step (d) comprises the following steps:
(d1) providing a TSV adapter plate with a groove and a pad structure, and bonding the TSV adapter plate with a second substrate to form a closed micro-channel region;
(d2) etching a liquid inlet and a liquid outlet at the bottom of the TSV adapter plate to enable the sealed micro-channel area to be communicated with the outside to obtain a third substrate;
(d3) and cutting the third substrate to obtain a single module, and fixing the module on the substrate to form a final structure with micro-channel heat dissipation.
8. The liquid cooling heat dissipation process for RF chips as claimed in claim 6, wherein the step (d) comprises the following steps:
(d1) manufacturing a metal module with a micro-channel;
(d2) embedding a metal module with a micro-channel into the cavity of the second substrate to enable the surface of the metal module to be in contact with the bottom of the cavity, then planting balls on a bonding pad on the front side of the first substrate to obtain a third substrate, and welding the third substrate and a base material to form a final structure with micro-channel heat dissipation.
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