CN111952196A - Groove chip embedding process - Google Patents

Groove chip embedding process Download PDF

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Publication number
CN111952196A
CN111952196A CN202010855815.3A CN202010855815A CN111952196A CN 111952196 A CN111952196 A CN 111952196A CN 202010855815 A CN202010855815 A CN 202010855815A CN 111952196 A CN111952196 A CN 111952196A
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substrate
tsv
passivation layer
etching
metal
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CN111952196B (en
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冯光建
黄雷
高群
郭西
顾毛毛
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The invention provides a groove chip embedding process, which comprises the following steps: (a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the back of the long TSV to be exposed, and obtaining a first substrate; (b) etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing the bottom of the TSV through exposure and development, and etching the passivation layer to expose metal at the bottom of the TSV; (c) and embedding a chip in the cavity, filling a gap between the chip and the cavity, and manufacturing an RDL and a bonding pad on the surface of the chip to obtain a final structure. According to the groove chip embedding process, the TSV at the bottom of the cavity is opened by the etching process in a mode of protecting the bottom of the cavity through the photoresist, so that the damage of the whole etching to the passivation layer at the bottom of the cavity can be avoided, the opening of the passivation layer at the bottom of the TSV is facilitated, and the passivation layer at the bottom of the cavity is damaged.

Description

Groove chip embedding process
Technical Field
The invention relates to the technical field of semiconductors, in particular to a groove chip embedding process.
Background
The millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection and imaging and the like, is expected to reach 11 billion dollars in market in 2018, and becomes a new industry. The new application puts new requirements on the electrical performance, compact structure and system reliability of the product, and the wireless transmitting and receiving system cannot be integrated on the same chip (SOC) at present, so that different chips including a radio frequency unit, a filter, a power amplifier and the like need to be integrated into a separate system to realize the functions of transmitting and receiving signals.
In the traditional packaging process, various functional chips and passive devices are mounted on a substrate, so that the occupied area is large, the reliability is poor, and the trend of more and more miniaturization of a packaging system cannot be met.
The bottom of the radio frequency chip needs to be subjected to heat dissipation and grounding interconnection, so that the bottom of the chip needs to be contacted with a TSV copper column, but for a structure that the radio frequency chip is buried into a silicon cavity, if the TSV is made first, a cavity needs to be made at the back of the adapter plate, and the bottom of the TSV is made as the bottom of the cavity.
However, in practical applications, a passivation layer is required to be formed at the bottom of the cavity to insulate the chip and the interposer, the passivation layer is also deposited at the top end of the TSV, and the passivation layer on the cavity needs to be reopened to be interconnected with the bottom of the chip.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a groove chip embedding process, which avoids the damage of the whole etching to the passivation layer at the bottom of the cavity and is beneficial to the opening of the passivation layer at the bottom of the TSV. The technical scheme adopted by the invention is as follows:
a groove chip embedding process comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottom of the long TSV to be exposed, and obtaining a first substrate;
(b) etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing the bottom of the TSV through exposure and development, and etching the passivation layer to expose metal at the bottom of the TSV;
(c) and embedding a chip in the cavity, filling a gap between the chip and the cavity, and manufacturing an RDL and a bonding pad on the surface of the chip to obtain a final structure.
Preferably, in the groove chip embedding process, the specific steps of step (a) are as follows:
(a1) manufacturing TSV with different depths on the front side of the substrate through photoetching and etching processes;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer;
(a3) electroplating copper to enable the TSV to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
(a5) and carrying out temporary bonding on the front side of the substrate, then thinning the back side of the substrate to expose the TSV, carrying out passivation layer on the back side, polishing to expose the metal of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
Preferably, in the groove chip embedding process, the specific step of the step (b) is:
(b1) etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(b3) and removing the photoresist, cleaning the substrate and debonding.
Preferably, in the groove chip embedding process, the specific step of the step (b) is:
(b1) etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer and a metal layer, coating photoresist on the surface of the passivation layer and exposing the bottom of the TSV through exposure and development, and etching the metal layer and the passivation layer to expose the metal at the bottom of the TSV;
(b4) and removing the photoresist, cleaning the substrate and debonding.
Preferably, in the groove chip embedding process, the specific step of the step (b) is:
(b1) etching a cavity on the back of the first substrate through photoetching and dry etching to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer;
(b3) and exposing the metal on the TSV side wall at the bottom of the cavity by dry etching or wet etching.
Preferably, the groove chip embedding process, wherein the diameter of the TSV is 1 um-1000 um, and the depth is 10 um-1000 um.
Preferably, the groove chip embedding process is carried out, wherein the thickness of the insulating layer is 0.01 um-100 um; the thickness of the seed layer is 0.001-100 um, and the seed layer is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Preferably, in the groove chip embedding process, the bonding pad is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Preferably, the groove chip embedding process, wherein the cavity depth is 10 um-1000 um.
The invention has the advantages that: according to the groove chip embedding process, the TSV at the bottom of the cavity is opened by the etching process in a mode of protecting the bottom of the cavity through the photoresist, so that the damage of the whole etching to the passivation layer at the bottom of the cavity can be avoided, the opening of the passivation layer at the bottom of the TSV is facilitated, and the passivation layer at the bottom of the cavity is damaged.
Drawings
FIG. 1 is a schematic diagram of a substrate etching TSV hole of the invention.
FIG. 2 is a schematic diagram of the front side of the substrate deposited with an insulating layer and a seed layer.
Fig. 3 is a schematic diagram of RDL and bonding pad formation on the back side of the substrate according to the present invention.
Fig. 4 is a schematic diagram of a TSV bottom passivation layer with exposed metal in embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of depositing a passivation layer according to embodiment 1 of the present invention.
FIG. 6 is a schematic view of the substrate surface coated with a photoresist in example 1 of the present invention.
FIG. 7 is a schematic diagram of removing photoresist according to embodiment 1 of the present invention.
Fig. 8 is a schematic view of the final structure of embodiment 1 of the present invention.
Fig. 9 is a schematic diagram of the short TSV bottom exposed in embodiment 2 of the present invention.
Fig. 10 is a schematic diagram of depositing a passivation layer and a metal layer according to embodiment 2 of the present invention.
Fig. 11 is a schematic diagram illustrating the TSV bottom metal exposure in embodiment 2 of the present invention.
FIG. 12 is a schematic diagram of removing photoresist in embodiment 2 of the present invention.
Fig. 13 is a schematic view of the final structure of embodiment 2 of the present invention.
Fig. 14 is a schematic illustration of metal exposure in embodiment 3 of the present invention.
Fig. 15 is a schematic view of exposing metal on the sidewall of the cavity bottom TSV in embodiment 3 of the invention.
Fig. 16 is a schematic diagram of the final structure of embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
The first embodiment;
a groove chip embedding process comprises the following steps:
(a) providing a substrate, etching the TSV 102 with different depths on the front surface of the substrate 101, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front surface of the substrate, manufacturing an RDL and a bonding pad on the front surface of the substrate, performing temporary bonding on the front surface of the substrate, and thinning the back surface of the substrate to enable the back of the long TSV to be exposed, so that a first substrate is obtained;
the specific steps of the step (a) are as follows:
(a1) as shown in fig. 1, TSVs with different depths are manufactured on the front side of the substrate through photoetching and etching processes, wherein the diameter range of the TSVs is 1um to 1000um, and the depth is 10um to 1000 um;
(a2) as shown in fig. 2, an insulating layer is deposited on the front surface of the substrate, a seed layer is manufactured on the insulating layer, the insulating layer is made of silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) electroplating copper to enable the TSV 103 to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate to remain;
electroplating copper 103 to make the TSV full of copper metal, and densifying at 200-500 ℃ to make the copper more dense; the copper CMP process removes the copper on the surface of the substrate, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by a dry etching or wet etching process; the insulating layer on the surface of the substrate can also be reserved;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
manufacturing an RDL and a bonding pad at the exposed end of the TSV opening through photoetching and electroplating processes, firstly manufacturing a seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation plating processes, wherein the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then, defining the RDL and the position of a bonding pad by photoetching, and electroplating to obtain the RDL and the metal of the bonding pad, wherein the thickness of the metal ranges from 1um to 100um, the metal can be one layer or multiple layers, and the metal can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
the SOI substrate and the carrier of the step comprise 4, 6, 8 and 12 inch substrates, the thickness range is 200um to 2000um, and the SOI substrate and the carrier can be made of other materials, such as glass, quartz, silicon carbide, alumina and other inorganic materials, epoxy resin, polyurethane and other organic materials, and the main function of the SOI substrate and the carrier is to provide a supporting function.
As shown in fig. 3, performing temporary bonding on the front surface of the substrate, then thinning the back surface to expose the TSV, performing a passivation layer on the back surface to expose the TSV metal by polishing, and then continuing to fabricate the RDL and the bonding pad;
(a5) and carrying out temporary bonding on the front surface of the substrate, then thinning the back surface of the substrate to expose the TSV, carrying out passivation layer on the back surface, polishing to expose the metal at the bottom of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing the bottom of the TSV through exposure and development, and etching the passivation layer to expose metal at the bottom of the TSV;
the concrete steps of the step (b) are as follows:
(b1) as shown in fig. 4, the cavity 104 is etched on the back side of the first substrate by means of photolithography and dry etching, so that the bottom of the short TSV is exposed; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) as shown in fig. 5, a passivation layer 105 is deposited, the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the passivation layer ranges from 10nm to 100 um; as shown in fig. 6, the surface is coated with a photoresist 106, exposed and developed to expose the bottom of the TSV, and the passivation layer is etched to expose the metal at the bottom of the TSV;
(b3) as shown in fig. 7, the photoresist is removed, the substrate is cleaned, and the bonding is released.
(c) As shown in fig. 8, a chip 107 is embedded in the cavity, a gap between the chip and the cavity is filled, and an RDL and a bonding pad 108 are formed on the surface of the chip, so as to obtain a final structure.
Example 2:
a groove chip embedding process comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the back of the long TSV to be exposed, and obtaining a first substrate;
the specific steps of the step (a) are as follows:
(a1) as shown in fig. 1, TSVs 102 with different depths are manufactured on the front surface of a substrate 101 through photolithography and etching processes, wherein the diameter of the TSV ranges from 1um to 1000um, and the depth ranges from 10um to 1000 um;
(a2) as shown in fig. 2, an insulating layer is deposited on the front surface of the substrate, a seed layer is manufactured on the insulating layer, the insulating layer is made of silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) electroplating copper to enable the TSV 103 to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate to remain;
electroplating copper 103 to make the TSV full of copper metal, and densifying at 200-500 ℃ to make the copper more dense; the copper CMP process removes the copper on the surface of the substrate, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by a dry etching or wet etching process; the insulating layer on the surface of the substrate can also be reserved;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
manufacturing an RDL and a bonding pad at the exposed end of the TSV opening through photoetching and electroplating processes, firstly manufacturing a seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation plating processes, wherein the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then, defining the RDL and the position of a bonding pad by photoetching, and electroplating to obtain the RDL and the metal of the bonding pad, wherein the thickness of the metal ranges from 1um to 100um, the metal can be one layer or multiple layers, and the metal can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
the SOI substrate and the carrier of the step comprise 4, 6, 8 and 12 inch substrates, the thickness range is 200um to 2000um, and the SOI substrate and the carrier can be made of other materials, such as glass, quartz, silicon carbide, alumina and other inorganic materials, epoxy resin, polyurethane and other organic materials, and the main function of the SOI substrate and the carrier is to provide a supporting function.
As shown in fig. 3, performing temporary bonding on the front surface of the substrate, then thinning the back surface to expose the TSV, performing a passivation layer on the back surface to expose the TSV metal by polishing, and then continuing to fabricate the RDL and the bonding pad;
(a5) and carrying out temporary bonding on the front side of the substrate, then thinning the back side of the substrate to expose the TSV, carrying out passivation layer on the back side, polishing to expose the metal of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing the bottom of the TSV through exposure and development, and etching the passivation layer to expose metal at the bottom of the TSV;
the concrete steps of the step (b) are as follows:
(b1) as shown in fig. 9, a cavity is etched on the back surface of the first substrate by means of photolithography and dry etching, the depth of the cavity is 10um to 1000um, so that the bottom of the short TSV is exposed; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer and a metal layer 109, wherein the passivation layer is silicon oxide or silicon nitride or is directly thermally oxidized, and the thickness of the passivation layer ranges from 10nm to 100 um; the thickness of the metal layer ranges from 1nm to 100um, the metal layer can be a layer or a plurality of layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(b3) coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the metal layer and the passivation layer to expose the metal on the bottom of the TSV as shown in FIG. 11;
(c) and removing the metal layer, embedding a chip in the cavity, filling the gap, and manufacturing the RDL and the bonding pad on the surface of the chip to finish the final structure.
As shown in fig. 12, the photoresist is removed, the metal layer on the surface of the substrate is removed, the substrate is cleaned, and bonding is released;
as shown in fig. 13, a chip is embedded in the cavity, the gap is filled, and RDLs and pads are fabricated on the surface of the chip to complete the final structure.
Example 3:
a groove chip embedding process comprises the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the back of the long TSV to be exposed, and obtaining a first substrate;
the specific steps of the step (a) are as follows:
(a1) as shown in fig. 1, TSVs with different depths are manufactured on the front side of the substrate through photoetching and etching processes, wherein the diameter range of the TSVs is 1um to 1000um, and the depth is 10um to 1000 um;
(a2) as shown in fig. 2, an insulating layer is deposited on the front surface of the substrate, a seed layer is manufactured on the insulating layer, the insulating layer is made of silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
(a3) electroplating copper to enable the TSV to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate;
electroplating copper 103 to make the TSV full of copper metal, and densifying at 200-500 ℃ to make the copper more dense; the copper CMP process removes the copper on the surface of the substrate, so that only copper filling is left on the surface of the substrate; the insulating layer on the surface of the substrate can be removed by a dry etching or wet etching process; the insulating layer on the surface of the substrate can also be reserved;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
manufacturing an RDL and a bonding pad at the exposed end of the TSV opening through photoetching and electroplating processes, firstly manufacturing a seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation plating processes, wherein the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; then, defining the RDL and the position of a bonding pad by photoetching, and electroplating to obtain the RDL and the metal of the bonding pad, wherein the thickness of the metal ranges from 1um to 100um, the metal can be one layer or multiple layers, and the metal can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
the SOI substrate and the carrier of the step comprise 4, 6, 8 and 12 inch substrates, the thickness range is 200um to 2000um, and the SOI substrate and the carrier can be made of other materials, such as glass, quartz, silicon carbide, alumina and other inorganic materials, epoxy resin, polyurethane and other organic materials, and the main function of the SOI substrate and the carrier is to provide a supporting function.
As shown in fig. 3, performing temporary bonding on the front surface of the substrate, then thinning the back surface to expose the TSV, performing a passivation layer on the back surface to expose the TSV metal by polishing, and then continuing to fabricate the RDL and the bonding pad;
(a5) and carrying out temporary bonding on the front side of the substrate, then thinning the back side of the substrate to expose the TSV, carrying out passivation layer on the back side, polishing to expose the metal of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
(b) Etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing the bottom of the TSV through exposure and development, and etching the passivation layer to expose metal at the bottom of the TSV;
the specific steps of the step (b) are as follows:
(b1) as shown in fig. 14, a cavity is etched on the back surface of the first substrate by photolithography and dry etching, the cavity depth is 10um to 1000um, and the bottom of the short TSV is exposed; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer; the passivation layer is an insulating layer such as silicon oxide or silicon nitride, or is directly thermally oxidized, and the thickness of the passivation layer ranges from 10nm to 100 um;
(b3) as shown in fig. 15, the metal is exposed on the bottom TSV sidewalls of the cavity by dry or wet etching.
(c) And embedding a chip in the cavity, filling the gap, and manufacturing an RDL and a bonding pad on the surface of the chip to finish the final structure.
As shown in fig. 16, a chip is embedded in the cavity, the gap is filled, and RDLs and pads are fabricated on the surface of the chip to complete the final structure.
According to the groove chip embedding process, the TSV at the bottom of the cavity is opened by the etching process in a mode of protecting the bottom of the cavity through the photoresist, so that the damage of the whole etching to the passivation layer at the bottom of the cavity can be avoided, the opening of the passivation layer at the bottom of the TSV is facilitated, and the passivation layer at the bottom of the cavity is damaged.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.

Claims (9)

1. A groove chip embedding process is characterized by comprising the following steps:
(a) providing a substrate, etching TSVs with different depths on the front side of the substrate, electroplating to enable the TSV to be filled with metal, polishing to remove the metal on the front side of the substrate, manufacturing an RDL and a bonding pad on the front side of the substrate, temporarily bonding the front side of the substrate, thinning the back side of the substrate to enable the bottom of the long TSV to be exposed, and obtaining a first substrate;
(b) etching a cavity on the back of the first substrate to expose the bottom of the short TSV, depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing the bottom of the TSV through exposure and development, and etching the passivation layer to expose metal at the bottom of the TSV;
(c) and embedding a chip in the cavity, filling a gap between the chip and the cavity, and manufacturing an RDL and a bonding pad on the surface of the chip to obtain a final structure.
2. The recess chip embedding process of claim 1, wherein the specific steps of step (a) are:
(a1) manufacturing TSV with different depths on the front side of the substrate through photoetching and etching processes;
(a2) depositing an insulating layer on the front surface of the substrate, and manufacturing a seed layer on the insulating layer;
(a3) electroplating copper to enable the TSV to be filled with the copper, removing the copper on the surface of the substrate, and enabling only the copper to be filled on the surface of the substrate;
(a4) manufacturing an RDL and a bonding pad on the front side of the substrate through photoetching and electroplating processes;
(a5) and carrying out temporary bonding on the front surface of the substrate, then thinning the back surface of the substrate to expose the bottom of the TSV, carrying out passivation layer on the back surface, polishing to expose the metal at the bottom of the TSV, and then manufacturing the RDL and the bonding pad to obtain the first substrate.
3. The recess chip embedding process of claim 1, wherein the specific steps of step (b) are:
(b1) etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer, coating photoresist on the surface of the passivation layer, exposing and developing to expose the bottom of the TSV, and etching the passivation layer to expose metal at the bottom of the TSV;
(b3) and removing the photoresist, cleaning the substrate and debonding.
4. The recess chip embedding process of claim 1, wherein the specific steps of step (b) are:
(b1) etching a cavity on the back of the first substrate in a photoetching and dry etching mode to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer and a metal layer;
(b3) and coating photoresist on the surface, exposing and developing to expose the bottom of the TSV, and etching the metal layer and the passivation layer to expose the metal at the bottom of the TSV.
5. The recess chip embedding process of claim 1, wherein the specific steps of step (b) are:
(b1) etching a cavity on the back of the first substrate through photoetching and dry etching to expose the bottom of the short TSV; etching the passivation layer at the bottom of the TSV by a dry etching method or a wet etching method to expose the metal;
(b2) depositing a passivation layer;
(b3) and exposing the metal on the TSV side wall at the bottom of the cavity by dry etching or wet etching.
6. The recess chip embedding process of claim 1, wherein the TSV has a diameter of 1um to 1000um and a depth of 10um to 1000 um.
7. The recess chip embedding process of claim 2, wherein the thickness of the insulating layer is 0.01um to 100 um; the thickness of the seed layer is 0.001-100 um, and the seed layer is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
8. The recess chip embedding process of claim 1, wherein the bonding pad is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
9. The recess chip embedding process of claim 1, wherein the cavity depth is 10um to 1000 um.
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