CN115527868A - Three-dimensional stacked fan-out type chip packaging method and packaging structure - Google Patents

Three-dimensional stacked fan-out type chip packaging method and packaging structure Download PDF

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CN115527868A
CN115527868A CN202210321547.6A CN202210321547A CN115527868A CN 115527868 A CN115527868 A CN 115527868A CN 202210321547 A CN202210321547 A CN 202210321547A CN 115527868 A CN115527868 A CN 115527868A
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substrate
chips
forming
metal pad
layer
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马力
项敏
季蓉
郑子企
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a packaging method and a packaging structure of a three-dimensional stacked fan-out chip, wherein the method comprises the following steps: providing a first substrate, a second substrate and a plurality of chips, wherein the edge area of the first substrate is provided with a plurality of first electric interconnection structures, and the edge area of the second substrate is provided with a plurality of second electric interconnection structures corresponding to the first electric interconnection structures; forming a channel in a central region of the first surface of the first substrate and securing the first surfaces of the plurality of chips within the channel, the plurality of chips being electrically connected to the first electrical interconnect structure; respectively carrying out hybrid bonding on the first surface of the first substrate and the second surfaces of the plurality of chips and the second substrate; forming a first rewiring layer on the second surface of the bonded first substrate; and forming a first metal pad on one side of the bonded second substrate, which is far away from the first substrate. The method can realize the interconnection of ultra-high density and ultra-short distance of the embedded chip, improve the integration level of the structure to the chip, reduce the whole packaging thickness and achieve the ultra-thin purpose.

Description

Three-dimensional stacked fan-out type chip packaging method and packaging structure
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a three-dimensional stacked fan-out type chip packaging method and a three-dimensional stacked fan-out type chip packaging structure.
Background
In a fan-out package, as shown in fig. 1, the die 10 is placed in a silicon-based socket,
and the photoresist is used for fixing the two parts into a whole. On the front side of the wafer, solder balls 14 are fabricated,
and the bonding pad is connected with the outside, penetrates to the back of the wafer through the silicon through hole 11, and is manufactured into a bonding pad 12, so that more connections with the outside are realized, and the purpose of high-density integrated packaging of the chip is achieved. However, in the above structure, the chip 10 is placed with the chip side facing up, and the through-silicon vias 11 are arranged at the edge of the silicon trench, so that the distribution density is low, and the improvement capability of the performance of the packaged device is limited. And the structure is a single-layer carrier, and the integration density is low.
In view of the above problems, there is a need for a package structure and a package method for fan-out chips stacked in three dimensions, which are reasonable in design and effectively solve the above problems.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a method and a structure for packaging a three-dimensionally stacked fan-out chip.
One aspect of the present invention provides a method of packaging a three-dimensionally stacked fan-out type chip, the method comprising:
providing a first substrate, a second substrate and a plurality of chips, wherein an edge area of the first substrate is provided with a plurality of first electrical interconnection structures, and an edge area of the second substrate is provided with a plurality of second electrical interconnection structures corresponding to the first electrical interconnection structures;
forming a slot in a central region of the first surface of the first substrate and securing the first surfaces of the plurality of dies within the slot, wherein the plurality of dies are electrically connected to the first electrical interconnect;
respectively carrying out hybrid bonding on the first surface of the first substrate and the second surfaces of the plurality of chips and the second substrate;
forming a first rewiring layer on the second surface of the bonded first substrate;
and forming a first metal pad on one side of the bonded second substrate, which is far away from the first substrate.
Optionally, a first passivation layer and a second metal pad are disposed on a side of the second substrate facing the first substrate;
the hybrid bonding of the first surface of the first substrate and the second surfaces of the plurality of chips with the second substrate, respectively, includes:
forming a second passivation layer and a third metal pad on the first surface of the first substrate and the second surfaces of the plurality of chips;
and bonding the first passivation layer and the second passivation layer, and bonding the second metal pad and the third metal pad.
Optionally, the second surfaces of the plurality of chips are provided with fourth metal pads,
before forming the second passivation layer and the third metal pad on the first surface of the first substrate and the second surfaces of the plurality of chips, the method further includes:
forming a first dielectric layer on the first surface of the first substrate and the surface of the fourth metal pad, and patterning the first dielectric layer;
and forming a second redistribution layer on the patterned first dielectric layer, and patterning the second redistribution layer.
Optionally, forming a first redistribution layer on the second surface of the first substrate after bonding includes:
thinning the second surface of the first substrate to expose the first electrical interconnect structure;
and forming a first rewiring layer on the thinned second surface of the first substrate.
Optionally, forming a first metal pad on a side of the second substrate facing away from the first substrate after bonding includes:
fixing the second surface of the first substrate on a temporary carrying disc;
thinning a side of the second substrate facing away from the first substrate to expose the second electrical interconnection structure;
forming the first metal pad on one side of the thinned second substrate, which is far away from the substrate;
separating the second surface of the first substrate from the temporary boat.
Optionally, after forming the first redistribution layer on the second surface of the first substrate after bonding, the method further includes:
patterning the first redistribution layer;
forming a second dielectric layer on the patterned first redistribution layer, and patterning the second dielectric layer;
and forming a plurality of solder balls on the patterned second dielectric layer.
Optionally, the plurality of chips are chips of the same type, or the plurality of chips are chips of different types, respectively.
Optionally, the second surfaces of the plurality of chips are lower than the surface of the tank.
Optionally, the first surfaces of the chips are back surfaces of the chips.
Another aspect of the present invention provides a three-dimensional stacked fan-out chip package structure, which is packaged by the packaging method described above.
According to the packaging method and the packaging structure of the three-dimensional stacked fan-out chip, the groove body is formed on the first surface of the first substrate, the first surfaces of the chips are fixed in the groove body, and the thickness of the total thickness formed by the chips and the first substrate is not much different from that of the first substrate, so that the thickness of the embedded packaging structure can be effectively reduced; the first surface of the first substrate and the second surfaces of the plurality of chips are respectively in hybrid bonding with the second substrate, so that the ultrashort distance interconnection of the packaging structure is realized, the overall performance and the integration level of the packaging structure are improved, the overall packaging thickness of the packaging structure is reduced, and the ultrathin packaging is realized.
Drawings
FIG. 1 is a schematic diagram of a fan-out package with embedded structures in the prior art;
FIG. 2 is a flow chart illustrating a method for packaging a three-dimensional stacked fan-out chip in accordance with an embodiment of the present invention;
fig. 3 to fig. 15 are schematic views illustrating a packaging process of a three-dimensional stacked fan-out chip package structure according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention is further described in detail with reference to the accompanying drawings and the detailed description below.
As shown in fig. 2, an aspect of the present invention provides a three-dimensional stacked fan-out chip packaging method S100, where the packaging method S100 includes:
s110, providing a first substrate, a second substrate and a plurality of chips, wherein a plurality of first electrical interconnection structures are arranged on the edge area of the first substrate, and a plurality of second electrical interconnection structures corresponding to the first electrical interconnection structures are arranged on the edge area of the second substrate.
Specifically, as shown in fig. 10 to 15, a first substrate 110, a second substrate 120, and a plurality of chips 130 are provided, wherein an edge region of the first substrate 110 is provided with a plurality of first electrical interconnection structures 111, and an edge region of the second substrate 120 is provided with a plurality of second electrical interconnection structures 121 corresponding to the first electrical interconnection structures 111. In this embodiment, the first substrate 110 is a silicon substrate, and may also be glass, metal, organic substrate, etc., and those skilled in the art can select the substrate according to actual needs, and the embodiment is not limited in particular.
It should be noted that the plurality of chips 130 may be chips of the same type or chips of different types, and this embodiment is not limited in particular. The number of the chips 130 is not limited in this embodiment, and may be set according to actual needs, and in this embodiment, the chips 130 are transversely fixed in the slot body 112.
It should be further noted that in the present embodiment, the first electrical interconnection structure 111 and the second electrical interconnection structure 121 both use through silicon vias, and other electrical interconnection structures may also be used, and the present embodiment is not particularly limited. Specifically, as shown in fig. 3, blind vias may be formed on the first surface of the first substrate 110 by etching, and then formed into the first electrical interconnection structure 111, that is, a through-silicon via, by electroplating, chemical plating, and the like. The first electrical interconnection structure 111 may be formed by other processes, and of course, a plurality of second electrical interconnection structures 121 may be formed on the surface of the second substrate 120 facing the first substrate 110 by the same process. The present embodiment is not particularly limited. And the vertical electrical interconnection of the silicon through holes is realized by adopting a silicon through hole technology, so that the packaging height is reduced.
S120, forming a slot in a central region of the first surface of the first substrate, and fixing the first surfaces of the plurality of chips in the slot, wherein the plurality of chips are electrically connected to the first electrical interconnection structure.
In the present embodiment, the first surfaces of the chips 130 are the back surfaces of the chips 130, that is, the chips 130 are fixed in the slot 112 with the front surfaces facing upward.
Specifically, as shown in fig. 4, a groove 112 may be formed in a central region of the first surface of the first substrate 110 by using photolithography and etching processes, and the first surfaces of the plurality of chips 130 may be fixed in the groove 112, that is, the back surfaces of the plurality of chips 130 may be fixed in the groove 112.
Illustratively, as shown in fig. 5, the second surface of the plurality of chips 130 is provided with fourth metal pads 131, that is, the front surface of the plurality of chips 130 is provided with fourth metal pads 131.
Securing first surfaces of the plurality of chips within the pocket, comprising:
as shown in fig. 5, a first adhesive 132 is formed on a first surface of the plurality of chips 130 to fix the plurality of chips 130 in the slot 112. That is, the first adhesive 132 is formed on the back surfaces of the plurality of chips 130, and the back surfaces of the plurality of chips 130 are fixed in the tank 112 by the first adhesive 132.
A second adhesive 133 is formed on the first surface of the first substrate 110 and the surface of the fourth metal pad 131, and a part of the second adhesive 133 is filled into the gap between the sidewall of the slot body 112 and the chips 130 and the gap between the chips 130, so as to further fix the chips 130.
The second adhesive (not shown) on the first surface of the first substrate 110 and the second surfaces of the plurality of chips is removed to expose the fourth metal pads 131.
The plurality of chips 130 are electrically connected to the first electrical interconnection structure 111, that is, the plurality of chips 130 are electrically connected to the plurality of first electrical interconnection structures 111 through the fourth metal pads 131, so as to lead out signals of the plurality of chips 130.
Illustratively, as shown in fig. 5, the second surfaces of the plurality of chips 130 are lower than the surface of the slot 112, so that the surface of the fourth metal pad 131 is flush with the first surface of the first substrate 110, and is used for paving the bonding between the first substrate 110 and the second substrate 120.
And S130, respectively carrying out hybrid bonding on the first surface of the first substrate and the second surfaces of the plurality of chips and a second substrate.
As shown in fig. 10, the first surface of the first substrate 110 and the second surfaces of the plurality of chips 130 are hybrid-bonded to the second substrate 120, respectively.
Specifically, as shown in fig. 10, a side of the second substrate 120 facing the first substrate 110 is provided with a first passivation layer 122 and a second metal pad 123.
The hybrid bonding of the first surface of the first substrate 110 and the second surfaces of the plurality of chips 130 to the second substrate 120, respectively, includes:
as shown in fig. 8 and 9, a second passivation layer 113 and a third metal pad 114 are formed on the first surface of the first substrate 110 and the second surfaces of the plurality of chips 130. After the third metal pad 114 is formed, the surfaces of the third metal pad 114 and the second passivation layer 113 are polished by using a chemical mechanical polishing technique, so that the surfaces of the third metal pad 114 and the second passivation layer 113 are flush.
The first passivation layer 122 is bonded to the second passivation layer 113, and the second metal pad 123 is bonded to the third metal pad 114. Specifically, the contact surfaces of the first passivation layer 122 and the second passivation layer 113 are flat, the first passivation layer 122 is aligned with the second passivation layer 113, the first passivation layer 122 is connected with the second passivation layer 113 through high-temperature pressing, and then baking is performed at a temperature above 200 ℃, so that the second metal pad 123 and the third metal pad 114 are thermally expanded to form a bond.
It should be noted that in this embodiment, the materials of the first passivation layer 122 and the second passivation layer 113 may be silicon dioxide materials or silicon nitride materials, or may be other materials that perform a passivation function, and this embodiment is not limited thereto. The second metal pad 123 and the third metal pad 114 may be copper pads, or may also be made of other metal materials, and this embodiment is not limited in particular. The second metal pad 123 is bonded to the third metal pad 114, that is, a pad is formed by thermal expansion of copper.
It should be noted that the second substrate 120 provided in this embodiment may be a silicon substrate, but is not limited thereto, and may also be another type of substrate such as SOI. The second substrate 120 may be a wafer, but is not limited thereto, and the second substrate 120 may also be a wafer with embedded chips or other chip wafers. That is, in the present embodiment, the structure of the second substrate 120 is not particularly limited as long as the first substrate 110 and the second substrate 120 can be hybrid bonded. The bonding scheme may be a bonding (face-back) of the first surface (front surface) of the first substrate 110 and the second surface (back surface) of the other substrate, and the positions may be reversed, that is, the first surface (front surface) of the first substrate 110 is bonded to the first surface (front surface) of the other substrate or the second surface (back surface) of the first substrate 110 is bonded to the second surface (back surface) of the other substrate. As shown in fig. 10, in the present embodiment, the second substrate 120 has a similar structure to the first substrate 110, a first slot 124 is disposed on a side of the second substrate 120 facing the first substrate 110, a plurality of first chips 140 are fixed in the first slot 124, and a first passivation layer 122 and a second metal pad 123 are respectively formed on a side of the second substrate 120 facing the first substrate 110 and a surface of the plurality of first chips 140 facing the first substrate 110. The first surface of the first substrate 110 is bonded to a surface of the second substrate 120 facing the first substrate 110 (face-face).
The first surface of the first substrate 110 and the second surfaces of the plurality of chips 130 are respectively mixed and bonded with the second substrate 120, so that signal interconnection among the chips can be realized.
Illustratively, before forming the second passivation layer and the third metal pad on the first surface of the first substrate and the second surfaces of the plurality of chips, the method further includes:
first, a first dielectric layer is formed on the first surface of the first substrate and the surface of the fourth metal pad, and the first dielectric layer is patterned.
Specifically, as shown in fig. 6, a first dielectric layer 134 is coated on the first surface of the first substrate 110 and the surface of the fourth metal pad 131, the material of the first dielectric layer 134 is Polyimide (PI), polybenzoxazole (PBO), etc., the coating method is usually wafer spin coating, and the embodiment is not limited in particular. A photoresist layer is applied to the surface of the first dielectric layer 134 and patterned by exposure and development to form a plurality of first openings (not shown).
And secondly, forming a second rewiring layer on the patterned first dielectric layer, and patterning the second rewiring layer.
Specifically, as shown in fig. 7, a second redistribution layer 135 is deposited on the patterned first dielectric layer 134 by sputtering, electroplating, or the like, the material of the second redistribution layer 135 is usually titanium and copper, and the deposition method and the metal material are not particularly limited in this embodiment. The second rewiring layer 135 is patterned by a photolithography and etching process. The etching process may be wet etching or dry etching, and this embodiment is not particularly limited. Depositing the second redistribution layer 135 on the patterned first dielectric layer 134 may provide a higher interconnection density to meet the requirements of high performance devices.
And S140, forming a first rewiring layer on the second surface of the bonded first substrate.
First, the second surface of the first substrate is thinned to expose the first electrical interconnection structure.
Specifically, as shown in fig. 11, the second surface of the first substrate 110 is thinned by a process such as grinding to expose the first electrical interconnection structure 111, that is, to expose the through-silicon via. Further preferably, the second surface of the first substrate 110 may be thinned to the first surfaces of the plurality of chips 130, that is, the second surface of the first substrate 110 may be thinned to the back surfaces of the plurality of chips 130, so that the package thickness may be reduced to the maximum, and the ultra-thin purpose is achieved.
And secondly, forming a first rewiring layer on the thinned second surface of the first substrate.
Specifically, as shown in fig. 12, a first redistribution layer 150 is deposited on the second surface of the thinned first substrate 110. The deposition method is sputtering, electroplating, etc., and the material of the first redistribution layer 150 is usually titanium and copper, and the deposition method and the metal material are not particularly limited in this embodiment.
After forming the first redistribution layer on the bonded second surface of the first substrate, the method may further include:
first, the first redistribution layer is patterned.
As shown in fig. 12, the first re-wiring layer 150 is patterned through a photolithography and etching process.
And secondly, forming a second dielectric layer on the patterned first redistribution layer, and patterning the second dielectric layer.
As shown in fig. 12, a second dielectric layer 160 is coated on the first redistribution layer 150 after the patterning, and the second dielectric layer 160 is patterned by photolithography and etching processes to form a plurality of second openings (not shown). The material of the second dielectric layer 160 is Polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in this embodiment.
And thirdly, forming a plurality of solder balls on the patterned second dielectric layer.
As shown in fig. 12, ball-planting is performed at the plurality of second openings of the patterned second dielectric layer 160 to form a plurality of solder balls 170, and the external substrate and the chip are connected through the solder balls 170. That is, the connection with the outside is realized through the solder balls 170, and of course, the connection with the outside may also be realized through other manners, and the embodiment is not particularly limited.
S150, forming a first metal pad on one side of the bonded second substrate, which is far away from the first substrate.
First, the second surface of the first substrate is fixed on a temporary boat.
As shown in fig. 13, specifically, the first surface of the first substrate 110 is fixed on the temporary boat 126 by an adhesive layer 125. The adhesive layer 125 encapsulates the plurality of solder balls 170 and protects the solder balls 170.
And secondly, thinning one side of the second substrate, which is deviated from the first substrate, so as to expose the second electric interconnection structure.
As shown in fig. 14, a side of the second substrate 120 facing away from the first substrate 110 is thinned by a grinding process or the like to expose the second electrical interconnection structure 121, that is, to expose the through-silicon via on the side of the second substrate 120 facing away from the first substrate 110. The thinning degree of the second substrate 120 can be selected according to actual needs, and the embodiment is not particularly limited.
And thirdly, forming the first metal pad on one side of the thinned second substrate, which is deviated from the substrate.
As shown in fig. 14, a first metal pad 180 is formed on a side of the thinned second substrate 120 away from the first substrate 110 by a plating, sputtering, or the like. The first metal pad 180 may be used to connect more chips or substrates. For example, the first metal pad 180 may be connected to a plurality of second substrates 120, or may be connected to a plurality of other chips, which is not limited in this embodiment.
Finally, the second surface of the first substrate is separated from the temporary boat.
As shown in fig. 15, the second surface of the first substrate 110 is separated from the temporary boat 126 using a temporary glass boat separation technique, completing the package.
According to the three-dimensional stacked fan-out chip packaging method, the groove body is formed on the first surface of the first substrate, the first surfaces of the chips are fixed in the groove body, the total thickness formed by the chips and the first substrate is not much different from the thickness of the first substrate, and therefore the thickness of the embedded packaging structure can be effectively reduced; the first surface of the first substrate and the second surfaces of the plurality of chips are respectively in hybrid bonding with the second substrate, so that the ultrashort distance interconnection of the packaging structure is realized, the overall performance and the integration level of the packaging structure are improved, the overall packaging thickness of the packaging structure is reduced, and the ultrathin packaging is realized.
As shown in fig. 15, another aspect of the present invention provides a three-dimensional stacked fan-out chip package structure 100, which is packaged by the packaging method S100 described above. The package structure 100 includes a first substrate 110, a second substrate 120, and a plurality of chips 130; wherein an edge region of the first substrate 110 is provided with a plurality of first electrical interconnection structures 111, and an edge region of the second substrate 120 is provided with a plurality of second electrical interconnection structures 121 corresponding to the first electrical interconnection structures 111. In this embodiment, the first substrate 110 is a silicon substrate, and may also be glass, metal, organic substrate, etc., and those skilled in the art can select the substrate according to actual needs, and the embodiment is not limited in particular.
In the present embodiment, the first substrate 110 is a silicon substrate, and may also be a glass, metal, organic substrate, etc., and those skilled in the art can select the substrate according to actual needs, and the present embodiment is not particularly limited. In this embodiment, the first electrical interconnection structure 111 is a through silicon via, and other electrical interconnection structures may also be used, which is not specifically limited in this embodiment. The vertical electrical interconnection of the silicon through holes is realized by adopting a silicon through hole technology, and the packaging height is reduced.
A central region of the first surface of the first substrate 110 is provided with a slot 112, a plurality of chips 130 are fixedly disposed in the slot 112, and the plurality of chips 130 are electrically connected with the first electrical interconnection structure 111. It should be noted that the plurality of chips 130 may be chips of the same type or chips of different types, and this embodiment is not limited in particular. The number of the chips 130 is not limited in this embodiment, and may be set according to actual needs, and in this embodiment, the chips 130 are transversely fixed in the slot body 112. In the present embodiment, the first surface of the plurality of chips 130 refers to the back surface of the chip, that is, the plurality of chips 130 are fixed in the slot 112 in a manner that the front surface faces upward.
The first surface of the first substrate 110 and the second surfaces of the plurality of chips 130 are hybrid bonded to the second substrate 120 through hybrid bonding structures (not shown). The first substrate 110 and the second substrate 120 are mixed and bonded, so that on one hand, signal interconnection among chips can be achieved, and on the other hand, ultra-high-density and ultra-short-distance interconnection embedded in the chips can be achieved.
The second surface of the first substrate 110 is provided with a first re-wiring layer 150. The material of the first redistribution layer 150 is typically titanium and copper, and this embodiment is not particularly limited to the material of the first redistribution layer 150. The first redistribution layer 150 may provide a higher interconnection density, improving device performance.
A side of the second substrate 120 facing away from the first substrate 110 is provided with a first metal pad 180. More chips may be connected through the first metal pad 180.
Illustratively, as shown in fig. 15, the hybrid bonding structure includes a first passivation layer 122 and a second metal pad 123 disposed on a side of the second substrate 120 facing the first substrate 110, and a second passivation layer 113 and a third metal pad 114 disposed on a first surface of the first substrate 110 and a second surface of the plurality of chips 130. The first passivation layer 122 is in hybrid bonding connection with the second passivation layer 113, and the second metal pad 123 is in hybrid bonding connection with the third metal pad 114.
It should be noted that in this embodiment, the materials of the first passivation layer 122 and the second passivation layer 113 may be a silicon dioxide material or a silicon nitride material, or may be other materials that perform a passivation function, and the embodiment is not limited thereto. The second metal pad 123 and the third metal pad 114 may be copper pads, or may be made of other metal materials, and this embodiment is not particularly limited.
For example, as shown in fig. 15, a fourth metal pad 131 is disposed on the second surface of the multiple chips 130, that is, the fourth metal pad 131 is disposed on the front surface of the multiple chips 130, and the fourth metal pad 131 is a metal copper pad, and may also be a pad made of another material, which is not specifically limited in this embodiment.
It should be noted that the second surfaces of the plurality of chips 130 are lower than the surface of the slot 112, so that the surface of the fourth metal pad 131 is flush with the first surface of the first substrate 110.
The package structure 100 further includes a first dielectric layer 134 and a second redistribution layer 135. The first dielectric layer 134 is disposed on the first surface of the first substrate 110 and the surface of the fourth metal pad 131. A second rewiring layer 135 is sandwiched between the first dielectric layer 134 and the hybrid bond structure. In this embodiment, the material of the first dielectric layer 134 is Polyimide (PI), polybenzoxazole (PBO), etc., and this embodiment is not particularly limited. The material of the second redistribution layer 135 is typically titanium and copper, and this embodiment is not particularly limited.
The package structure 100 further includes a second dielectric layer 160 and a plurality of solder balls 170, the second dielectric layer 160 is disposed on the first redistribution layer 150, and the plurality of solder balls 170 is disposed on the second dielectric layer 160. In this embodiment, the material of the second dielectric layer 160 is Polyimide (PI), polybenzoxazole (PBO), etc., and this embodiment is not particularly limited. The package structure may be connected to the outside through the solder balls 170, or may be connected to the outside through other manners, which is not limited in this embodiment.
Illustratively, as shown in fig. 15, a first adhesive layer 132 is disposed between the first surfaces of the plurality of chips 130 and the bottom of the tank 112, and a second adhesive layer 133 is disposed between the plurality of chips 130 and the sidewall of the tank 112. The first adhesive layer 132 and the second adhesive layer 133 can better fix the plurality of chips 130 in the slot 112.
It should be noted that the second substrate 120 provided in this embodiment may be a silicon substrate, but is not limited thereto, and may also be another type of substrate such as SOI. The second substrate 120 may be a wafer, but is not limited thereto, and the second substrate 120 may also be a wafer with embedded chips or other chip wafers. That is, in the present embodiment, the structure of the second substrate 120 is not particularly limited as long as the first substrate 110 and the second substrate 120 can be bonded and connected by the hybrid bonding structure.
As shown in fig. 15, in the present embodiment, the second substrate 120 has a similar structure to the first substrate 110, the surface of the second substrate 120 facing the first substrate 110 is provided with a first groove 124, the first grooves 124 are fixed with a plurality of first chips 140, and the first passivation layer 122 and the second metal pad 123 are respectively formed on a side of the second substrate 120 facing the first substrate 110 and a surface of the first chips 140 facing the first substrate 110. Of course, the second substrate 120 may have other structures, and this embodiment is not particularly limited.
The three-dimensional stacked fan-out type chip packaging structure comprises a first substrate, a second substrate and a plurality of chips, wherein a plurality of first electric interconnection structures are arranged in the edge area of the first substrate, and a plurality of second electric interconnection structures corresponding to the first electric interconnection structures are arranged in the edge area of the second substrate; a groove body is arranged in the central area of the first surface of the first substrate, a plurality of chips are fixedly arranged in the groove body, and the plurality of chips are electrically connected with the first electrical interconnection structure; the first surface of the first substrate and the second surfaces of the plurality of chips are in hybrid bonding with the second substrate through a hybrid bonding structure; a first rewiring layer is arranged on the second surface of the first substrate; one side of the second substrate, which is far away from the first substrate, is provided with a first metal bonding pad for connecting more chips. The packaging structure can realize the interconnection of ultra-high density and ultra-short distance of the embedded chip, simultaneously improve the integration level of the structure to the chip, reduce the whole packaging thickness and achieve the ultra-thin purpose.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A method of three-dimensionally stacked fan-out die packaging, the method comprising:
providing a first substrate, a second substrate and a plurality of chips, wherein the edge area of the first substrate is provided with a plurality of first electric interconnection structures, and the edge area of the second substrate is provided with a plurality of second electric interconnection structures corresponding to the first electric interconnection structures;
forming a channel in a central region of the first surface of the first substrate and securing the first surfaces of the plurality of dies within the channel, wherein the plurality of dies are electrically connected to the first electrical interconnect structure;
respectively carrying out hybrid bonding on the first surface of the first substrate and the second surfaces of the chips and the second substrate;
forming a first rewiring layer on the second surface of the bonded first substrate;
and forming a first metal pad on one side of the bonded second substrate, which is far away from the first substrate.
2. The method according to claim 1, characterized in that a side of the second substrate facing the first substrate is provided with a first passivation layer and a second metal pad;
the hybrid bonding of the first surface of the first substrate and the second surfaces of the plurality of chips with the second substrate, respectively, includes:
forming a second passivation layer and a third metal pad on the first surface of the first substrate and the second surfaces of the plurality of chips;
and bonding the first passivation layer and the second passivation layer, and bonding the second metal pad and the third metal pad.
3. The method of claim 2, wherein the second surfaces of the plurality of chips are provided with fourth metal pads,
before forming the second passivation layer and the third metal pad on the first surface of the first substrate and the second surfaces of the plurality of chips, the method further includes:
forming a first dielectric layer on the first surface of the first substrate and the surface of the fourth metal pad, and patterning the first dielectric layer;
and forming a second rewiring layer on the patterned first dielectric layer, and patterning the second rewiring layer.
4. The method of claim 1, wherein forming a first redistribution layer on the bonded second surface of the first substrate comprises:
thinning the second surface of the first substrate to expose the first electrical interconnection structure;
and forming a first rewiring layer on the thinned second surface of the first substrate.
5. The method of claim 1, wherein forming a first metal pad on a side of the second substrate facing away from the first substrate after bonding comprises:
fixing the second surface of the first substrate on a temporary carrier disc;
thinning a side of the second substrate facing away from the first substrate to expose the second electrical interconnection structure;
forming the first metal pad on one side of the thinned second substrate, which is far away from the substrate;
separating the second surface of the first substrate from the temporary boat.
6. The method of claim 1, wherein after forming a first redistribution layer on the bonded second surface of the first substrate, the method further comprises:
patterning the first redistribution layer;
forming a second dielectric layer on the patterned first redistribution layer, and patterning the second dielectric layer;
and forming a plurality of solder balls on the patterned second dielectric layer.
7. The method of any one of claims 1 to 6, wherein the plurality of chips are the same type of chip or the plurality of chips are different types of chips respectively.
8. The method of any one of claims 1 to 6, wherein the second surface of the plurality of chips is lower than the surface of the channel.
9. The method of any of claims 1 to 6, wherein the first surface of the plurality of chips is a back surface of the plurality of chips.
10. A three-dimensional stacked fan-out chip package structure, wherein the package method of any one of claims 1 to 9 is adopted for packaging.
CN202210321547.6A 2022-03-30 2022-03-30 Three-dimensional stacked fan-out type chip packaging method and packaging structure Pending CN115527868A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116230556A (en) * 2023-05-06 2023-06-06 芯盟科技有限公司 Chip carrier, forming method thereof, wafer bonding structure and forming method thereof
CN116230555A (en) * 2023-05-06 2023-06-06 芯盟科技有限公司 Chip carrier, forming method thereof and forming method of wafer bonding structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116230556A (en) * 2023-05-06 2023-06-06 芯盟科技有限公司 Chip carrier, forming method thereof, wafer bonding structure and forming method thereof
CN116230555A (en) * 2023-05-06 2023-06-06 芯盟科技有限公司 Chip carrier, forming method thereof and forming method of wafer bonding structure
CN116230555B (en) * 2023-05-06 2023-08-29 芯盟科技有限公司 Chip carrier, forming method thereof and forming method of wafer bonding structure
CN116230556B (en) * 2023-05-06 2023-08-29 芯盟科技有限公司 Chip carrier, forming method thereof, wafer bonding structure and forming method thereof

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