CN115527869A - Three-dimensional stacked fan-out type chip packaging method and packaging structure - Google Patents

Three-dimensional stacked fan-out type chip packaging method and packaging structure Download PDF

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Publication number
CN115527869A
CN115527869A CN202210321548.0A CN202210321548A CN115527869A CN 115527869 A CN115527869 A CN 115527869A CN 202210321548 A CN202210321548 A CN 202210321548A CN 115527869 A CN115527869 A CN 115527869A
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substrate
chips
metal pad
passivation layer
electrical
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马力
项敏
季蓉
郑子企
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The invention provides a three-dimensional stacked fan-out type chip packaging method and a packaging structure, wherein the method comprises the following steps: providing a first substrate, a second substrate and a plurality of chips, wherein the edge area of the first substrate is provided with a plurality of first electric interconnection structures, and the edge area of the second substrate is provided with a plurality of second electric interconnection structures corresponding to the first electric interconnection structures; forming a channel in a central region of a first surface of a first substrate and securing first surfaces of a plurality of chips within the channel, wherein the plurality of chips are electrically connected to a first electrical interconnect structure; thinning the second surface of the first substrate to expose the first electrical interconnection structure; and carrying out hybrid bonding on the second surface of the first substrate and the second substrate. The method adopts a hybrid bonding process to realize the interconnection of ultra-short distance, reduce the impedance of electric signals and the thermal resistance of packaging, and improve the performance during the period.

Description

Three-dimensional stacked fan-out type chip packaging method and packaging structure
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a three-dimensional stacked fan-out type chip packaging method and a three-dimensional stacked fan-out type chip packaging structure.
Background
In a fan-out package, as shown in fig. 1, the die 10 is placed in a silicon-based slot,
the photoresist is used to fix the two parts into a whole. On the front side of the wafer, solder balls 14 are fabricated,
and the bonding pad is connected with the outside, penetrates to the back of the wafer through the silicon through hole 11, and is manufactured into a bonding pad 12, so that more connections with the outside are realized, and the purpose of high-density integrated packaging of the chip is achieved. For the above structure, a flip-chip manner is generally adopted, and chips are stacked to improve the integration level of the package. The size and the distance of welding spots are large by adopting an inverted mode, the used packaging I/O density is low, glue layers are usually adopted between the laminated layers for filling, and the heat dissipation capacity is poor.
In view of the above problems, there is a need for a package structure and a package method for fan-out chips stacked in three dimensions, which are reasonable in design and effectively solve the above problems.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a method and a structure for packaging a three-dimensionally stacked fan-out chip.
One aspect of the present invention provides a three-dimensional stacked fan-out chip packaging method, including:
providing a first substrate, a second substrate and a plurality of chips, wherein the edge area of the first substrate is provided with a plurality of first electric interconnection structures, and the edge area of the second substrate is provided with a plurality of second electric interconnection structures corresponding to the first electric interconnection structures;
forming a slot in a central region of the first surface of the first substrate and securing the first surfaces of the plurality of dies within the slot, wherein the plurality of dies are electrically connected to the first electrical interconnect;
thinning the second surface of the first substrate to expose the first electrical interconnect structure;
and carrying out hybrid bonding on the second surface of the first substrate and the second substrate.
Optionally, a first passivation layer and a first metal pad are disposed on a side of the second substrate facing the first substrate;
the hybrid bonding of the second surface of the first substrate and the second substrate comprises:
forming a second passivation layer and a second metal pad on the second surface of the first substrate;
and bonding the first passivation layer and the second passivation layer, and bonding the first metal pad and the second metal pad.
Optionally, thinning the second surface of the first substrate to expose the first electrical interconnection structure includes:
fixing the first surface of the first substrate on a temporary carrying disc;
thinning the second surface of the first substrate to enable the surfaces of the first electrical interconnection structures far away from the plurality of chips to protrude out of the second surface of the first substrate;
it is right one side that first electricity interconnection structure kept away from a plurality of chips carries out the attenuate, makes first electricity interconnection structure keeps away from the surface of a plurality of chips with after the attenuate the second surface of first base plate flushes.
Optionally, after the thinning the second surface of the first substrate to expose the first electrical interconnection structure, the method further includes:
forming a second passivation layer on the thinned second surface of the first substrate;
patterning the second passivation layer, and forming the second metal pad on the patterned second passivation layer;
separating the first surface of the first substrate from the temporary boat.
Optionally, the second surfaces of the plurality of chips are provided with third metal pads, and after the first surfaces of the plurality of chips are fixed in the slot, the method further includes:
forming a dielectric layer on the first surface of the first substrate and the surface of the third metal pad;
and patterning the dielectric layer, and forming a plurality of solder balls on the patterned dielectric layer, wherein the solder balls are distributed corresponding to the third metal pad and the first electrical interconnection structure respectively.
Another aspect of the present invention provides a three-dimensional stacked fan-out chip package structure, including:
a first substrate having a first surface provided with a channel in a central region and a plurality of first electrical interconnections in an edge region;
a second substrate provided with a plurality of second electrical interconnection structures at an edge region thereof, the plurality of second electrical interconnection structures corresponding to the plurality of first electrical interconnection structures;
a plurality of chips, a first surface of the plurality of chips fixedly disposed in the slot and electrically connected to the first electrical interconnect structure;
and the mixed bonding structure is used for respectively connecting the second surface of the first substrate with the second substrate in a mixed bonding manner.
Optionally, the hybrid bonding structure includes:
the first passivation layer and the first metal pad are arranged on one side, facing the first substrate, of the second substrate;
a second passivation layer and a second metal pad disposed on the second surface of the first substrate;
the first passivation layer is in bonding connection with the second passivation layer, and the first metal pad is in bonding connection with the second metal pad.
Optionally, the package structure further includes:
a third metal pad disposed on the second surfaces of the plurality of chips;
a dielectric layer disposed on the first surface of the first substrate and the surface of the third metal pad;
and a plurality of solder balls arranged on the dielectric layer, wherein the solder balls are distributed corresponding to the third metal pad and the first electric interconnection structure respectively.
Optionally, the first surfaces of the plurality of chips are back surfaces of the plurality of chips.
Optionally, the first electrical interconnection structure and the second electrical interconnection structure are both through silicon vias.
According to the three-dimensional stacked fan-out chip packaging method and the packaging structure, the groove body is formed on the first surface of the first substrate, the first surfaces of the chips are fixed in the groove body, the total thickness formed by the chips and the first substrate is almost the same as the thickness of the first substrate, and therefore the thickness of the embedded packaging structure can be effectively reduced; the second surface of the first substrate and the second substrate are subjected to hybrid bonding, the ultrashort distance interconnection of the packaging structure is realized, the distance between the two substrates can be greatly reduced, the integral packaging thickness of the packaging structure is reduced, the I/O density of chip packaging is improved, the electric signal impedance and the packaging thermal resistance are reduced, and the performance of a device is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art embedded fan-out chip package;
FIG. 2 is a flow chart illustrating a three-dimensional stacked fan-out chip packaging method according to an embodiment of the invention;
fig. 3 to 14 are schematic views illustrating a packaging process of a three-dimensional stacked fan-out chip package structure according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2, an aspect of the present invention provides a three-dimensional stacked fan-out type chip packaging method S100, where the packaging method S100 includes:
s110, providing a first substrate, a second substrate and a plurality of chips, wherein a plurality of first electric interconnection structures are arranged on the edge area of the first substrate, and a plurality of second electric interconnection structures corresponding to the first electric interconnection structures are arranged on the edge area of the second substrate.
Specifically, as shown in fig. 14, a first substrate 110, a second substrate 120 and a plurality of chips 130 are provided, wherein an edge region of the first substrate 110 is provided with a plurality of first electrical interconnection structures 111, and an edge region of the second substrate 120 is provided with a plurality of second electrical interconnection structures 121 corresponding to the first electrical interconnection structures 111. In this embodiment, the first substrate 110 is a silicon substrate, and may also be glass, metal, organic substrate, etc., and those skilled in the art can select the substrate according to actual needs, and the embodiment is not limited in particular.
It should be noted that the plurality of chips 130 may be the same type of chip or different types of chips, and this embodiment is not limited in particular. The number of the chips 130 is not limited in this embodiment, and may be set according to actual needs, in this embodiment, the plurality of chips 130 are transversely fixed in the slot 112.
It should be further noted that in the present embodiment, the first electrical interconnection structure 111 and the second electrical interconnection structure 121 both use through silicon vias, and other electrical interconnection structures may also be used, and the present embodiment is not particularly limited. Specifically, as shown in fig. 3, blind vias may be formed on the first surface of the first substrate 110 by etching, and then the blind vias are formed into the first electrical interconnection structure 111, i.e., through-silicon-vias, by electroplating, chemical plating, and the like. The first electrical interconnection structure 111 may be formed by other processes, and of course, a plurality of second electrical interconnection structures 121 may be formed on the surface of the second substrate 120 facing the first substrate 110 by the same process. The present embodiment is not particularly limited. And the vertical electrical interconnection of the silicon through holes is realized by adopting a silicon through hole technology, so that the packaging height is reduced.
And S120, forming a groove body in the central area of the first surface of the first substrate, and fixing the first surfaces of the plurality of chips in the groove body, wherein the plurality of chips are electrically connected with the first electric interconnection structure.
In the present embodiment, the first surfaces of the chips 130 are the back surfaces of the chips 130, that is, the chips 130 are fixed in the slot body 112 with the front surfaces facing upward.
Specifically, as shown in fig. 4, a groove 112 may be formed in a central region of the first surface of the first substrate 110 by using photolithography and etching processes, and the first surfaces of the plurality of chips 130 may be fixed in the groove 112, that is, the back surfaces of the plurality of chips 130 may be fixed in the groove 112.
Illustratively, as shown in fig. 5, the second surface of the plurality of chips 130 is provided with a third metal pad 131, that is, the front surface of the plurality of chips 130 is provided with the third metal pad 131.
Securing first surfaces of the plurality of chips within the pocket, comprising:
as shown in fig. 5, a first adhesive 132 is formed on a first surface of the plurality of chips 130 to fix the plurality of chips 130 in the slot 112. That is, the first adhesive 132 is formed on the back surfaces of the plurality of chips 130, and the back surfaces of the plurality of chips 130 are fixed in the slot 112 by the first adhesive 132.
Second adhesive 133 is formed on the first surface of the first substrate 110 and the surface of the third metal pad 131, and a portion of the second adhesive 133 is filled into the gap between the sidewall of the slot 112 and the chip 130 and the gaps between the chips 130, so as to further fix the chips 130.
The second adhesive (not shown) on the first surface of the first substrate 110 and the second surfaces of the plurality of chips is removed to expose the third metal pads 131.
The plurality of chips 130 are electrically connected to the first electrical interconnection structure 111, that is, the plurality of chips 130 are electrically connected to the plurality of first electrical interconnection structures 111 through the third metal pads 131, so as to extract signals of the plurality of chips 130.
Illustratively, after the fixing the first surfaces of the plurality of chips in the slot, the method further comprises:
first, a dielectric layer is formed on the first surface of the first substrate and the surface of the third metal pad.
Specifically, as shown in fig. 6, a dielectric layer 134 is formed on the first surface of the first substrate 110 and the surface of the third metal pad 131. That is, the dielectric layer 134 is coated on the first surface of the first substrate 110 and the surface of the third metal pad 131, the material of the dielectric layer 134 is Polyimide (PI), polybenzoxazole (PBO), etc., the coating method is usually wafer spin coating, and the embodiment is not limited in particular.
Secondly, the dielectric layer is patterned, and a plurality of solder balls are formed on the patterned dielectric layer, wherein the solder balls are distributed corresponding to the third metal pad and the first electric interconnection structure respectively.
Specifically, as shown in fig. 6, a photoresist layer is coated on the surface of the dielectric layer 134, the photoresist layer is patterned by exposure and development to form a plurality of first openings (not shown), and as shown in fig. 7, ball-planting is performed at the plurality of first openings to form a plurality of solder balls 140. The solder balls 140 are distributed corresponding to the third metal pads 131 and the first electrical interconnection structure 111, respectively, so as to connect the chips 130 to the outside. In this embodiment, the solder ball 140 is made of cunisnga, sn, cuSn, cuNiSn, or the like, which is not limited in this embodiment.
S130, thinning the second surface of the first substrate to expose the first electric interconnection structure.
First, the first surface of the first substrate is fixed on a temporary boat.
Specifically, as shown in fig. 8, the first surface of the first substrate 110 is fixed on a temporary boat 126 by an adhesive layer 125. The adhesive layer 125 encapsulates the solder balls 140 and protects the solder balls 140.
And thinning the second surface of the first substrate to enable the surfaces, far away from the plurality of chips, of the first electrical interconnection structure to protrude out of the second surface of the first substrate.
Specifically, as shown in fig. 9, the second surface of the first substrate 110 is thinned by grinding and etching, so that the surface of the first electrical interconnection structure 111 protrudes from the second surface of the first substrate 110. That is, only the second surface of the first substrate 110 is thinned, and the first electrical interconnect structure 111 is not thinned.
Thirdly, thinning one side of the first electric interconnection structure, which is far away from the plurality of chips, so that the surface of the first electric interconnection structure, which is far away from the plurality of chips, is flush with the second surface of the first substrate after thinning.
Specifically, as shown in fig. 10, the protective layer 115 is formed on the second surface of the thinned first substrate and the surface of the first interconnect structure 111 away from the plurality of chips 130. In this embodiment, the material of the protection layer 115 may be silicon oxide or silicon nitride, or other materials that can perform a protection function may also be used, and this embodiment is not particularly limited.
As shown in fig. 11, a side of the first electrical interconnection structure 111 away from the plurality of chips 130 is thinned by a process such as mechanochemical polishing, so that a surface of the first electrical interconnection structure 111 away from the plurality of chips 130 is flush with the second surface of the thinned first substrate 110. That is, the protection layer 115 is removed by a process such as mechanochemical polishing, and the first electrical interconnection structure 111, i.e. the portion of the through-silicon via protruding from the second surface of the first substrate 110 is removed, so that the surface of the first electrical interconnection structure 111 away from the plurality of chips 130 is flush with the second surface of the thinned first substrate 110.
Compared with the common thinning process, the thinning process adopted by the second surface of the first substrate is simple and easy to implement, and the cost is low.
Step S130 can also be implemented by a next process step.
In another embodiment, the second surface of the first substrate 110 is thinned to a specified thickness by grinding and etching, and then back-polished by a polishing machine until the first electrical interconnection structure 111 is exposed. Forming a second passivation layer 113 on the second surface of the thinned first substrate 110, and patterning the second passivation layer 113 by using a photolithography process or the like, wherein the patterned second passivation layer 113 exposes the first electrical interconnection structure 111. A second metal pad 114 is formed on the patterned second passivation layer 113, wherein a portion of the second metal pad 114 corresponds to the first electrical interconnection structure 111.
After thinning the second surface of the first substrate to expose the first electrical interconnect structure, the method may further comprise:
firstly, forming a second passivation layer on the second surface of the thinned first substrate;
specifically, as shown in fig. 12, a second passivation layer 113 is deposited on the second surface of the thinned first substrate 110.
And secondly, patterning the second passivation layer, and forming the second metal pad on the patterned second passivation layer.
Specifically, as shown in fig. 12, the second passivation layer 113 is patterned by using a photolithography process to form a plurality of second openings (not shown), and a second metal pad 114 is formed at the plurality of second openings.
And thirdly, separating the first surface of the first substrate from the temporary carrying disc.
Specifically, as shown in fig. 13, the first surface of the first substrate 110 is separated from the temporary boat 126. Preparation is made for hybrid bonding of the first substrate 110 and the second substrate 120.
And S140, carrying out hybrid bonding on the second surface of the first substrate and the second substrate.
Specifically, as shown in fig. 14, a side of the second substrate 120 facing the first substrate is provided with a first passivation layer 122 and a first metal pad 123;
hybrid bonding the second surface of the first substrate 110 with the second substrate 120 includes:
as shown in fig. 12, a second passivation layer 113 and a second metal pad 114 are formed on the second surface of the first substrate 110 after thinning.
As shown in fig. 14, the first passivation layer 122 is bonded to the second passivation layer 113, and the first metal pad 123 is bonded to the second metal pad 114.
Specifically, the contact surfaces of the first passivation layer 122 and the second passivation layer 113 are flat, the first passivation layer 122 and the second passivation layer 113 are aligned, the first passivation layer 122 and the second passivation layer 113 are connected through high-temperature pressing, and then baking is performed at a temperature of 200 ℃ or higher, so that the first metal pad 123 and the second metal pad 114 are thermally expanded to form a bond.
It should be noted that in this embodiment, the materials of the first passivation layer 122 and the second passivation layer 113 may be silicon dioxide materials or silicon nitride materials, or may be other materials that perform a passivation function, and this embodiment is not limited thereto. The first metal pad 123 and the second metal pad 114 may be copper pads, or may be made of other metal materials, and this embodiment is not particularly limited. The first metal pad 123 is bonded to the second metal pad 114, that is, the pad is formed by thermal expansion of copper.
It should be noted that the second substrate 120 provided in this embodiment may be a silicon substrate, but is not limited to this, and may also be another type of substrate such as SOI. The second substrate 120 may be a wafer, but is not limited thereto, and the second substrate 120 may also be a wafer with embedded chips or other chip wafers. That is, in the present embodiment, the structure of the second substrate 120 is not particularly limited as long as the second surface of the first substrate 110 and the second substrate 120 can be hybrid bonded. The bonding scheme may be a bonding (face-back) of the first surface (front surface) of the first substrate 110 and the second surface (back surface) of the other substrate, and the positions may be reversed, that is, the first surface (front surface) of the first substrate 110 is bonded to the first surface (front surface) of the other substrate or the second surface (back surface) of the first substrate 110 is bonded to the second surface (back surface) of the other substrate.
As shown in fig. 14, in the present embodiment, the second substrate 120 has a structure similar to that of the first substrate 110, a first groove 124 is disposed on a side of the second substrate 120 away from the first substrate 110, a plurality of first chips 150 are fixed in the first groove 124, and a first passivation layer 122 and a first metal pad 123 are respectively formed on a side of the second substrate 120 facing the first substrate 110. The second surface of the first substrate 110 is bonded to a surface of the second substrate 120 facing the first substrate 110 (face-face). In this embodiment, a plurality of first solder balls 160 are disposed on a side of the second substrate 120 away from the first substrate 110. Of course, how to set the embodiment specifically on the side of the second substrate 120 away from the first substrate 110 is not limited, and solder balls may be set to lead out signals of the chips, or pads may be set to continue stacking the chips.
The second surface of the first substrate 110 and the second substrate 120 are mixed and bonded, and signal interconnection between chips can be achieved.
According to the three-dimensional stacked fan-out chip packaging method, the groove body is formed on the first surface of the first substrate, the first surfaces of the chips are fixed in the groove body, the total thickness formed by the chips and the first substrate is not much different from the thickness of the first substrate, and therefore the thickness of the embedded packaging structure can be effectively reduced; the second surface of the first substrate and the second substrate are subjected to hybrid bonding, the ultra-short distance interconnection of the packaging structure is realized, the distance between the two substrates can be greatly reduced, the overall packaging thickness of the packaging structure is reduced, the I/O density of chip packaging is improved, the electrical signal impedance and the packaging thermal resistance are reduced, and the performance of a device is improved.
As shown in fig. 14, another aspect of the present invention provides a three-dimensional stacked fan-out chip package structure 100, the package structure 100 including: a first substrate 110, a second substrate 120, a plurality of chips 130, and a hybrid bonding structure (not shown).
A central region of the first surface of the first substrate 110 is provided with a slot 112 and an edge region of the first substrate 110 is provided with a plurality of first electrical interconnection structures 111.
An edge region of the second substrate 120 is provided with a plurality of second electrical interconnection structures 121, and the plurality of second electrical interconnection structures 121 correspond to the plurality of first electrical interconnection structures 111.
A first surface of a plurality of chips 130 is fixedly disposed in the channel 112 and is electrically connected to the first electrical interconnect structure 111. In the present embodiment, the first surfaces of the chips 130 are the back surfaces of the chips 130, that is, the chips 130 are fixed in the slot 112 with the front surfaces facing upward.
The hybrid bonding structures hybrid-bond the second surfaces of the first substrate 110 and the second substrate 120, respectively.
In the present embodiment, the first substrate 110 is a silicon substrate, and may also be a glass, metal, organic substrate, etc., and those skilled in the art can select the substrate according to actual needs, and the present embodiment is not particularly limited.
It should be noted that the plurality of chips 130 may be the same type of chip or different types of chips, and the embodiment is not limited in particular. The number of the chips 130 is not limited in this embodiment, and may be set according to actual needs, and in this embodiment, the chips 130 are transversely fixed in the slot body 112.
It should be further noted that in the present embodiment, the first electrical interconnection structure 111 and the second electrical interconnection structure 121 both use through silicon vias, and other electrical interconnection structures may also be used, and the present embodiment is not particularly limited. Specifically, as shown in the figure, blind vias may be formed on the first surface of the first substrate 110 by etching or the like, and then the blind vias may be formed into the first electrical interconnection structure 111, i.e., through-silicon vias, by electroplating, chemical plating or the like. The first electrical interconnection structure 111 may be formed by other processes, and of course, a plurality of second electrical interconnection structures 121 may be formed on the surface of the second substrate 120 facing the first substrate 110 by the same process. The present embodiment is not particularly limited. And the vertical electrical interconnection of the silicon through holes is realized by adopting a silicon through hole technology, so that the packaging height is reduced.
As shown in fig. 14, the hybrid bonding structure includes a first passivation layer 122 and a first metal pad 123 disposed on a side of the second substrate 120 facing the first substrate 110, and a second passivation layer 113 and a second metal pad 114 disposed on a second surface of the first substrate 110. The first passivation layer 122 is bonded to the second passivation layer 113, and the first metal pad 123 is bonded to the second metal pad 114.
In this embodiment, the first passivation layer 122 and the second passivation layer 113 may be made of silicon oxide and silicon nitride, or may be made of other materials for passivation, and this embodiment is not particularly limited. The first metal pad 123 and the second metal pad 114 may be made of a metal copper material, and may also be made of other metal materials, which is not specifically limited in this embodiment.
As shown in fig. 14, the package structure 100 further includes a third metal pad 131, a dielectric layer 134, and a plurality of solder balls 140, where the third metal pad 131 is disposed on the second surface of the plurality of chips 130, that is, the third metal pad 131 is disposed on the front surface of the plurality of chips 130.
The dielectric layer 134 is disposed on the first surface of the first substrate 110 and the surface of the third metal pad 131. In this embodiment, the material of the dielectric layer 134 is Polyimide (PI), polybenzoxazole (PBO), etc., and this embodiment is not particularly limited.
A plurality of solder balls 140 are disposed on the dielectric layer 134, wherein the plurality of solder balls 140 are distributed corresponding to the third metal pads 131 and the first electrical interconnect structures 111, respectively. In this embodiment, the solder ball 140 is made of cunisnga, sn, cuSn, cuNiSn, or the like, which is not limited in this embodiment.
It should be noted that the second substrate 120 provided in this embodiment may be a silicon substrate, but is not limited thereto, and may also be another type of substrate such as SOI. The second substrate 120 may be a wafer, but is not limited thereto, and the second substrate 120 may also be a wafer with embedded chips or other chip wafers. That is, in the present embodiment, the structure of the second substrate 120 is not particularly limited as long as the second surface of the first substrate 110 and the second substrate 120 can be hybrid-bonded and connected by a hybrid-bonding structure.
As shown in fig. 14, in the present embodiment, the second substrate 120 has a similar structure to the first substrate 110, a first groove 124 is disposed on a side of the second substrate 120 away from the first substrate 110, a plurality of first chips 150 are fixed in the first groove 124, and a first passivation layer 122 and a first metal pad 123 are respectively formed on a side of the second substrate 120 facing the first substrate 110. The second surface of the first substrate 110 is bonded to a surface of the second substrate 120 facing the first substrate 110 (face-face). In this embodiment, a plurality of first solder balls 160 are disposed on a side of the second substrate 120 away from the first substrate 110. Of course, how to set the embodiment specifically on the side of the second substrate 120 away from the first substrate 110 is not limited, and solder balls may be set to lead out signals of the chips, or pads may be set to continue stacking the chips.
The three-dimensional stacked fan-out chip packaging structure can realize the ultra-short distance interconnection of embedded chips and improve the I/O density of chip packaging. Meanwhile, ultrashort distance interconnection is realized among the chips, the packaging thickness can be reduced, the electric signal impedance and the packaging thermal resistance are reduced, and the performance of the device is improved.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A method of three-dimensionally stacked fan-out die packaging, the method comprising:
providing a first substrate, a second substrate and a plurality of chips, wherein the edge area of the first substrate is provided with a plurality of first electric interconnection structures, and the edge area of the second substrate is provided with a plurality of second electric interconnection structures corresponding to the first electric interconnection structures;
forming a slot in a central region of the first surface of the first substrate and securing the first surfaces of the plurality of dies within the slot, wherein the plurality of dies are electrically connected to the first electrical interconnect;
thinning the second surface of the first substrate to expose the first electrical interconnect structure;
and carrying out hybrid bonding on the second surface of the first substrate and the second substrate.
2. The method according to claim 1, characterized in that a side of the second substrate facing the first substrate is provided with a first passivation layer and a first metal pad;
the hybrid bonding of the second surface of the first substrate and the second substrate comprises:
forming a second passivation layer and a second metal pad on the second surface of the first substrate;
and bonding the first passivation layer and the second passivation layer, and bonding the first metal pad and the second metal pad.
3. The method of claim 2, wherein thinning the second surface of the first substrate to expose the first electrical interconnect structure comprises:
fixing the first surface of the first substrate on a temporary carrier disc;
thinning the second surface of the first substrate so that the surfaces of the first electrical interconnection structures, which are far away from the plurality of chips, protrude from the second surface of the first substrate;
it is right one side that first electricity interconnection structure kept away from a plurality of chips carries out the attenuate, makes first electricity interconnection structure keeps away from the surface of a plurality of chips with after the attenuate the second surface of first base plate flushes.
4. The method of claim 3, wherein after thinning the second surface of the first substrate to expose the first electrical interconnect structure, the method further comprises:
forming a second passivation layer on the thinned second surface of the first substrate;
patterning the second passivation layer, and forming the second metal pad on the patterned second passivation layer;
separating the first surface of the first substrate from the temporary boat.
5. The method of claim 1, wherein the second surfaces of the plurality of chips are provided with third metal pads, and wherein after securing the first surfaces of the plurality of chips within the pocket, the method further comprises:
forming a dielectric layer on the first surface of the first substrate and the surface of the third metal pad;
and patterning the dielectric layer, and forming a plurality of solder balls on the patterned dielectric layer, wherein the solder balls are distributed corresponding to the third metal pad and the first electrical interconnection structure respectively.
6. A three-dimensional stacked fan-out chip package structure, the package structure comprising:
a first substrate having a first surface provided with a groove in a central region thereof and a plurality of first electrical interconnection structures in an edge region thereof;
a second substrate provided with a plurality of second electrical interconnection structures at an edge region thereof, the plurality of second electrical interconnection structures corresponding to the plurality of first electrical interconnection structures;
a plurality of chips, a first surface of the plurality of chips fixedly disposed in the tank and electrically connected to the first electrical interconnect structure;
and the hybrid bonding structures are used for hybrid bonding connection of the second surface of the first substrate and the second substrate respectively.
7. The package structure of claim 6, wherein the hybrid bond structure comprises:
the first passivation layer and the first metal pad are arranged on one side, facing the first substrate, of the second substrate;
the second passivation layer and the second metal pad are arranged on the second surface of the first substrate;
the first passivation layer is in bonding connection with the second passivation layer, and the first metal pad is in bonding connection with the second metal pad.
8. The package structure of claim 6, further comprising:
a third metal pad disposed on the second surfaces of the plurality of chips;
a dielectric layer disposed on the first surface of the first substrate and the surface of the third metal pad;
and a plurality of solder balls arranged on the dielectric layer, wherein the solder balls are distributed corresponding to the third metal pad and the first electric interconnection structure respectively.
9. The package structure according to any one of claims 6 to 8, wherein the first surfaces of the plurality of chips are back surfaces of the plurality of chips.
10. The package structure of any one of claims 6 to 8, wherein the first electrical interconnect structure and the second electrical interconnect structure are both through-silicon vias.
CN202210321548.0A 2022-03-30 2022-03-30 Three-dimensional stacked fan-out type chip packaging method and packaging structure Pending CN115527869A (en)

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