CN203833606U - Lamination combined type MEMS chip - Google Patents
Lamination combined type MEMS chip Download PDFInfo
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- CN203833606U CN203833606U CN201420216893.9U CN201420216893U CN203833606U CN 203833606 U CN203833606 U CN 203833606U CN 201420216893 U CN201420216893 U CN 201420216893U CN 203833606 U CN203833606 U CN 203833606U
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- mems
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- insulating barrier
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- silicon
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- 238000003475 lamination Methods 0.000 title claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims description 93
- 230000004888 barrier function Effects 0.000 claims description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 238000007789 sealing Methods 0.000 claims description 14
- 238000003466 welding Methods 0.000 claims description 14
- 238000000926 separation method Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 claims description 2
- 230000033001 locomotion Effects 0.000 abstract description 6
- 238000013461 design Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 52
- 238000005516 engineering process Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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Abstract
The utility model discloses a lamination combined type MEMS (Micro-electro-Mechanical Systems) chip, consisting of a bottom plate, a first MEMS layer, a through-silicon via integrated layer, a second MEMS layer and a cover plate; wherein a lower seal cavity is formed by a bottom plate cavity and the through-silicon via integrated layer, a first MEMS structure is arranged in the lower seal cavity, an upper seal cavity is formed by a cover plate cavity and the through-silicon via integrated layer, a second MEMS structure is arranged in the upper seal cavity, the air pressure in the upper seal cavity is different from the air pressure in the lower seal cavity, the second MEMS layer and the first MEMS layer are respectively bonded to upper and lower sides of the through-silicon via integrated layer, a bottom plate insulating layer is provided between the first MEMS layer and the bottom plate for isolation, and a cover plate insulating layer is provided between the second MEMS layer and the cover plate for isolation. The lamination combined type MEMS chip of the utility model can meet requirements of a combined type motion sensor chip to different pressures, and the lamination combined type MEMS chip has the advantages of small volume, high integrated level, flexible design and low cost.
Description
Technical field
The utility model belongs to MEMS chip technology field, specifically relates to a kind of lamination combined type MEMS chip.
Background technology
MEMS(Micro-Electro-Mechanical Systems) be the abbreviation of MEMS, MEMS manufacturing technology is utilized Micrometer-Nanometer Processing Technology, particularly semiconductor wafer manufacturing technology, produce various MIniature machinery structures, in conjunction with special control integration circuit (ASIC), form the MEMS components and parts such as intelligentized microsensor, microactrator, micro-optical device.It is little that MEMS components and parts have volume, cost is low, reliability is high, anti-adverse environment ability is strong, low in energy consumption, intelligent degree is high, easily calibration, advantage easy of integration, be widely used in consumer electronics product (as mobile phone, panel computer, toy, digital camera, game machine, air mouse, remote controller, GPS etc.), national defense industry is (as intelligent bomb, guided missile, Aero-Space, unmanned aerial vehicle etc.) and industrial series products (as automobile, robot, intelligent transportation, industrial automation, environmental monitoring, platform stable control, agricultural modernization, security monitoring etc.), MEMS components and parts become the foundation stone of technology of Internet of things gradually.
Along with portable type electronic product, as the rapid growth in the market such as mobile phone, panel computer, consumer electronics product has become the biggest market of MEMS components and parts, almost in each portable type electronic product, can use multiple MEMS components and parts, taking smart mobile phone as example, it has used gyroscope, accelerometer, altimeter, microphone, digital compass, tuned antenna, wave filter etc.Along with market is more and more stricter to the requirement of MEMS components and parts, should volume little, performance is high, low, the combined type MEMS components and parts of price again, particularly the market share of combined type MEMS motion sensor is increasing.Combined type MEMS components and parts are that the function of two or more MEMS components and parts is concentrated in components and parts, as combined type movement sensors such as gyroscope+accelerometer, accelerometer+digital compass, gyroscope+accelerometer+digital compass, they are that MEMS chip is independently combined by the way of encapsulation mostly, also have directly three axis accelerometer and three-axis gyroscope chip are made in same MEMS chip, Here it is combined type MEMS motion sensor chip.But in existing product, different MEMS structures is to be all produced on same MEMS layer, be accelerometer and gyroscope, or two different gyrohorizon directions of range are arranged, as Invensense, Bosch, the product of STMicroelectronics etc., because different MEMS structures is utilized same MEMS layer making, design flexibility is poor, and, the operation principle of MEMS gyroscope and accelerometer is different, gyroscope is service behaviour the best under lower pressure, generally below 0.001 atmospheric pressure, and accelerometer service behaviour the best under elevated pressures, generally more than 0.1 atmospheric pressure, this just requires MEMS chip to meet both demands simultaneously, be produced on compared with in low pressure by MEMS gyroscope arrangement, by mems accelerometer structure fabrication in higher air pressure.Existing pair of pressure MEMS wafer-level packaging of chip method is to be manufactured with getter in an annular seal space, in another annular seal space, there is no getter, when they enclose the mixture of active gases and inert gas during at wafer bonding in annular seal space, then heat post processing, there is the active gases in the annular seal space of getter to be absorbed, only remaining inert gas, internal pressure is lower, according to the ratio difference of mist, pressure can approach vacuum; And do not have active gases in the annular seal space of getter can not be absorbed, and gas pressure can not change, and pressure is higher, reaches so two pressure wafer level packaging objects, and the method need to be used getter, and getter also needs graphically, and cost is higher.
Utility model content
The technical problems to be solved in the utility model is to overcome the deficiencies in the prior art, a kind of lamination combined type MEMS chip is provided, this chip need to not put into getter in annular seal space, just can meet the requirement of combined type movement sensor chip to different pressures, and this chip size is little, integrated level is high, cost is low, the market competitiveness is strong.
For solving the problems of the technologies described above, the utility model provides a kind of lamination combined type MEMS chip, by base plate, the one MEMS layer, silicon perforation integrated layer, the 2nd MEMS layer and cover plate composition, on base plate, has a base plate cavity at least, on cover plate, has a cover plate cavity at least, base plate cavity and silicon perforation integrated layer form at least one lower seal chamber, cover plate cavity and silicon perforation integrated layer form annular seal space at least one, the air pressure inside difference of two annular seal spaces, the one MEMS structure is positioned at lower seal chamber, the 2nd MEMS structure is positioned at annular seal space, base plate and a MEMS interlayer have base plate insulator separation, cover plate and the 2nd MEMS interlayer have cover plate insulator separation, described silicon perforation integrated layer comprises silicon perforated layer, at least one layer insulating and one deck metal level at least, in described silicon perforated layer, there is isolating trenches, in isolating trenches, fill separation layer, silicon perforated layer is isolated ditch and is divided into sealing bonding region, the first vertical electrode and silicon conductive pole, sealing bonding region and silicon conductive pole all with a MEMS layer Direct Bonding, between the first vertical electrode and a MEMS structure, there is the first vertical electrode spacing, in described silicon perforated layer, accumulation has insulating barrier, has through hole in insulating barrier, and metal level is distributed on insulating barrier and is filled in through hole simultaneously.A described MEMS layer comprises a MEMS bonding region, a MEMS structure and a MEMS conduction region, a MEMS bonding region and sealing bonding region bonding, a MEMS conduction region and silicon conductive pole bonding.Described insulating barrier has three layers, be respectively the first insulating barrier, the second insulating barrier and the 3rd insulating barrier, described metal level has three layers, be respectively the first metal layer, the second metal level and the 3rd metal level, the first insulating barrier covers in silicon perforated layer, in the first insulating barrier, have the first through hole, the first metal layer is distributed on the first insulating barrier and is filled in the first through hole simultaneously, the first metal layer, for drawing the signal of telecommunication of a MEMS structure, is also drawn the signal of telecommunication of a MEMS structure and the 2nd MEMS structure simultaneously as press welding block; The second insulating barrier is deposited on the first metal layer, in the second insulating barrier, have the second through hole, the second metal level covers on the second insulating barrier and is filled in the second through hole simultaneously, the second metal level disturbs for the signal of telecommunication that shields the first metal layer and the 3rd metal interlevel, simultaneously for connecting the 3rd metal level and the first metal layer; Deposit the 3rd insulating barrier on the second metal level, in the 3rd insulating barrier, have third through-hole, the 3rd metal level covers on the 3rd insulating barrier and is filled in third through-hole simultaneously, the 3rd metal level is for drawing the signal of telecommunication of the 2nd MEMS structure, for surrounding upper annular seal space, between the second vertical electrode part of the 3rd metal level and the 2nd MEMS structure, there is the second vertical electrode spacing simultaneously.Described the first metal layer is divided into the first metal wire and press welding block by function, and the first metal wire electrically connects by the first through hole and the first vertical electrode and silicon conductive pole, and press welding block is exposed outside the second insulating barrier.Described the second metal level is divided into the second metal wire and blind zone by function, and the second metal wire electrically connects by the second through hole and the first metal wire, and first metal wire one end is connected with press welding block.Described the 3rd metal level is divided into the 3rd metal wire, metal sealing district and the second vertical electrode by function, the 3rd metal wire and the 2nd MEMS layer electrically connect, the second vertical electrode electrically connects by third through-hole and the second metal wire, metal sealing district and the 2nd MEMS floor Direct Bonding.
The combined type MEMS chip that builds up of the present utility model has annular seal space and at least one lower seal chamber at least one, separate and the stacked setting in upper-lower seal chamber, air pressure in upper-lower seal chamber can difference also can be identical, different MEMS structures lays respectively in upper-lower seal chamber, between with metal level come shielded signal disturb, different MEMS structure fabrications is in same MEMS chip, can meet the requirement of different integrated form MEMS components and parts simultaneously, and it is little to have volume, flexible design, cost is low.
Brief description of the drawings
Fig. 1 is the structural representation of the utility model detailed description of the invention.
Fig. 2 is that press welding block side metal line is overlooked enlarged drawing.
Detailed description of the invention
Below in conjunction with drawings and Examples, the utility model is described in further detail.
As shown in Figure 1, lamination combined type MEMS chip, by base plate 101, the one MEMS layer 104, silicon perforation integrated layer 410, the 2nd MEMS layer 504 and cover plate 501 form, on base plate 101, there is a base plate cavity 103a, on cover plate, there is a cover plate cavity 503a, base plate cavity 103a and silicon perforation integrated layer 410 form a lower seal chamber 103, cover plate cavity 503a and silicon perforation integrated layer 410 form a upper annular seal space 503, the air pressure inside difference of two annular seal spaces, a described MEMS layer 104 comprises a MEMS bonding region 104a, the one MEMS structure 104b and a MEMS conduction region 104c, the one MEMS structure 104b is positioned at lower seal chamber 103, described the 2nd MEMS layer 504 comprises a MEMS bonding region 504a, the one MEMS structure 504b and a MEMS conduction region 504c, the 2nd MEMS structure 504b is positioned at annular seal space 503, between base plate 101 and a MEMS layer 104, there is base plate insulating barrier 102 to isolate, between cover plate 501 and the 2nd MEMS layer 504, there is cover plate insulating barrier 502 to isolate, described silicon perforation integrated layer 410 comprises silicon perforated layer 200, the first insulating barrier 401, the first metal layer 403, the second insulating barrier 404, the second metal level 406, the 3rd insulating barrier 407 and the 3rd metal level 409, in described silicon perforated layer 200, there is isolating trenches 202, the interior filling silica of isolating trenches 202 separation layer, silicon perforated layer 200 is isolated ditch 202 and is divided into sealing bonding region 201c, the first vertical electrode 201d and silicon conductive pole 201e, sealing bonding region 201c and silicon conductive pole 201e all with MEMS layer 104 Direct Bonding, between the first vertical electrode 201d and a MEMS structure 104b, there is the first vertical electrode spacing 203, the first insulating barrier 401 covers in silicon perforated layer 200, in the first insulating barrier 401, have the first through hole 402, the first metal layer is distributed on the first insulating barrier 401 and is filled in the first through hole 402 simultaneously, the first metal layer is divided into the first metal wire 403a and press welding block 403b by function, the first metal wire 403a electrically connects by the first through hole 402 and the first vertical electrode 201d and silicon conductive pole 201e, press welding block 403b is exposed outside the second insulating barrier 404, the signal of telecommunication of the first metal layer for drawing a MEMS structure 104b, also draw the signal of telecommunication of a MEMS structure 104b and the 2nd MEMS structure 504b as press welding block 403b simultaneously, the second insulating barrier 404 is deposited on the first metal layer, in the second insulating barrier 404, have the second through hole 405, the second metal level covers on the second insulating barrier 404 and is filled in the second through hole 405 simultaneously, the second metal level is divided into the second metal wire 406a and blind zone 406b by function, the second metal wire 406a electrically connects by the second through hole 405 and the first metal wire 403a, the second metal level disturbs for the signal of telecommunication that shields the first metal layer and the 3rd metal interlevel, simultaneously for connecting the 3rd metal level and the first metal layer, deposit the 3rd insulating barrier 407 on the second metal level, in the 3rd insulating barrier 407, have third through-hole 408, the 3rd metal level covers on the 3rd insulating barrier 407 and is filled in third through-hole 408 simultaneously, the 3rd metal level is divided into the 3rd metal wire 409a by function, metal sealing district 409c and the second vertical electrode 409b, between the 3rd metal wire 409a and the 2nd MEMS layer 504, electrically connect, the second vertical electrode 409b electrically connects by third through-hole 408 and the second metal wire 406a, metal sealing district 409c and the 2nd MEMS floor 504 Direct Bonding, the signal of telecommunication of the 3rd metal level for drawing the 2nd MEMS structure 504b, simultaneously for surrounding upper annular seal space 503, between the second vertical electrode on the 2nd MEMS layer and metallization seal disc, form the second vertical electrode spacing 505, for responding to the 2nd MEMS structure motion in the vertical direction.
Wherein, the hardware cloth line chart of press welding block side as shown in Figure 7, the first metal wire 403a electrically connects with silicon conductive pole 201e by the first through hole 402, the second metal wire 406a electrically connects by the second through hole 405 and the first metal wire 403a, one end of the first metal wire 403a connects press welding block 403b, like this, the second metal wire 406a is just electrically connected with press welding block 403b.
Claims (6)
1. lamination combined type MEMS chip, is characterized in that: be made up of base plate, a MEMS layer, silicon perforation integrated layer, the 2nd MEMS layer and cover plate; On base plate, has a base plate cavity at least, on cover plate, has a cover plate cavity at least, base plate cavity and silicon perforation integrated layer form at least one lower seal chamber, the one MEMS structure is positioned at lower seal chamber, cover plate cavity and silicon perforation integrated layer form annular seal space at least one, the 2nd MEMS structure is positioned at annular seal space, and upper annular seal space is different with lower seal chamber internal gas pressure, and the 2nd MEMS layer and a MEMS layer are bonded in respectively the silicon perforation upper and lower both sides of integrated layer;
Described silicon perforation integrated layer comprises silicon perforated layer, at least one layer insulating and one deck metal level at least, in described silicon perforated layer, there is isolating trenches, in isolating trenches, fill separation layer, silicon perforated layer is isolated ditch and is divided into sealing bonding region, the first vertical electrode and silicon conductive pole, sealing bonding region and silicon conductive pole all with a MEMS layer Direct Bonding, between the first vertical electrode and a MEMS structure, there is the first vertical electrode spacing; In silicon perforated layer, accumulation has insulating barrier, has through hole in insulating barrier, and metal level is distributed on insulating barrier and is filled in through hole simultaneously;
Between the one MEMS layer and base plate, there is base plate insulator separation, between the 2nd MEMS layer and cover plate, have cover plate insulator separation.
2. lamination combined type MEMS chip according to claim 1, it is characterized in that: a described MEMS layer comprises a MEMS bonding region, a MEMS structure and a MEMS conduction region, the one MEMS bonding region and sealing bonding region bonding, a MEMS conduction region and silicon conductive pole bonding.
3. lamination combined type MEMS chip according to claim 1, it is characterized in that: described insulating barrier has three layers, be respectively the first insulating barrier, the second insulating barrier and the 3rd insulating barrier, described metal level has three layers, be respectively the first metal layer, the second metal level and the 3rd metal level, the first insulating barrier covers in silicon perforated layer, has the first through hole in the first insulating barrier, and the first metal layer is distributed on the first insulating barrier and is filled in the first through hole simultaneously; The second insulating barrier is deposited on the first metal layer, has the second through hole in the second insulating barrier, and the second metal level covers on the second insulating barrier and is filled in the second through hole simultaneously; On the second metal level, deposit the 3rd insulating barrier, has third through-hole in the 3rd insulating barrier, and the 3rd metal level covers on the 3rd insulating barrier and is filled in third through-hole simultaneously.
4. lamination combined type MEMS chip according to claim 3, it is characterized in that: described the first metal layer is divided into the first metal wire and press welding block by function, the first metal wire electrically connects by the first through hole and the first vertical electrode and silicon conductive pole, and press welding block is exposed outside the second insulating barrier.
5. lamination combined type MEMS chip according to claim 3, it is characterized in that: described the second metal level is divided into the second metal wire and blind zone by function, the second metal wire electrically connects by the second through hole and the first metal wire, and first metal wire one end is connected with press welding block.
6. lamination combined type MEMS chip according to claim 3, it is characterized in that: described the 3rd metal level is divided into the 3rd metal wire, metal sealing district and the second vertical electrode by function, the 3rd metal wire and the 2nd MEMS layer electrically connect, the second vertical electrode electrically connects by third through-hole and the second metal wire, metal sealing district and the 2nd MEMS floor Direct Bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420216893.9U CN203833606U (en) | 2014-04-30 | 2014-04-30 | Lamination combined type MEMS chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420216893.9U CN203833606U (en) | 2014-04-30 | 2014-04-30 | Lamination combined type MEMS chip |
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| Publication Number | Publication Date |
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| CN203833606U true CN203833606U (en) | 2014-09-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420216893.9U Expired - Lifetime CN203833606U (en) | 2014-04-30 | 2014-04-30 | Lamination combined type MEMS chip |
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| Country | Link |
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| CN (1) | CN203833606U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107010591A (en) * | 2015-09-29 | 2017-08-04 | 精材科技股份有限公司 | Electronic installation and its manufacture method |
| CN111952196A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
-
2014
- 2014-04-30 CN CN201420216893.9U patent/CN203833606U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107010591A (en) * | 2015-09-29 | 2017-08-04 | 精材科技股份有限公司 | Electronic installation and its manufacture method |
| CN111952196A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
| CN111952196B (en) * | 2020-08-24 | 2024-04-26 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140917 |