CN108766897B - Packaging method of three-dimensional heterostructure for realizing high-power GaN device layer heat dissipation - Google Patents
Packaging method of three-dimensional heterostructure for realizing high-power GaN device layer heat dissipation Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention provides a packaging method of a three-dimensional heterostructure for realizing the heat dissipation of a high-power GaN device layer aiming at the requirements of the three-dimensional heterostructure integration and the heat dissipation integration of the high-power GaN device layer, which utilizes a plurality of laminated substrates such as a GaN chip body, a TSV radio frequency adapter plate, a silicon supporting block and the like to realize the design of a three-dimensional folding micro-channel, micro-fluid flows into a back picking step from the bottom layer of a packaging shell to cool a hot spot of the GaN device layer upwards and then flows out from the picking step, thereby overcoming the problems of split flow design, integration and compatible manufacture of the traditional three-dimensional micro-channel and the packaging body-chip when the embedded micro-channel extends into the high-power GaN chip body from the TSV adapter plate in the traditional TSV three-dimensional integration technology, further realizing the three-dimensional heterostructure integration application with high.
Description
Technical Field
The invention relates to the field of microelectronic packaging, in particular to a three-dimensional heterogeneous integrated packaging method for realizing heat dissipation of a high-power GaN device layer based on a TSV (through silicon via) technology.
Background
The rapid development in the fields of 5G wireless communication, radar, unmanned aerial vehicle, satellite and the like brings wider requirements for radio frequency front-end electronic devices, and the important development trend of microwave and millimeter wave systems is more the main challenge in terms of complicated spectrum processing, high performance, small volume, high integration and light weight. Since 2006, with the breakthrough progress of advanced SiCMOS technology and InP and other heterogeneous integration technologies proposed by the DARPA microsystem in the united states, it is demonstrated and verified that heterogeneous integration is not two technology choices for breaking through the technical limitations. Compared with InP-based and GaAs-based devices, the GaN HEMT device has the highest Johnson factor, can be applied to higher frequency and higher power, and is an essential key device for supporting future high-power radio frequency and microwave communication, aerospace, military systems and the likeTherefore, GaN heterogeneous integration technology has become an important current development direction in the world. Meanwhile, with the development of three-dimensional integrated packaging application, the heat flux density of the three-dimensional integrated packaging high-power GaN chip reaches 100W/cm2Above, the heat flux density of the next generation of airborne platform high-power GaN chip is estimated to be 500W/cm2Above, the heat dissipation capability of the conventional heat dissipation technology is far exceeded, and the heat dissipation problem of the high-power device is more challenging due to the three-dimensional heterogeneous integration technology.
At present, the conventional heat dissipation technologies for GaN device packaging are still mainly air-cooled heat dissipation technologies and heat sink heat dissipation technologies. The air-cooled heat dissipation technology is a cooling method for dissipating heat by using air to take away heat, and the cooling method comprises natural cooling and forced cooling. The natural cooling technology is widely applied to low-power-consumption devices with low temperature control requirements and low heat flux density due to low cooling cost and no need of maintenance; the forced cooling technology is a way of dissipating heat by forcing ambient air to flow mainly with the aid of a heat dissipating device such as a fan, and has the main advantages of reducing the volume of an air cooling system and dissipating heat 10 times of that of natural cooling. However, for a high-power GaN device, an air-cooled radiator which only depends on conduction and convection in the air-cooled heat dissipation technology is close to the heat conduction limit of the high-power GaN device, the heat dissipation limit capacity of the high-power GaN device can only reduce the thermal resistance between a node and the environment to 0.5 ℃/W, and the cooling efficiency is low; and the heat dissipation devices such as fans and the like for enhancing convection heat transfer are obviously overlarge in diameter compared with microelectronic chips, and the heat dissipation space of the GaN device is limited, so that the heat dissipation performance is limited.
On the other hand, the heat sink heat dissipation technology can also realize the heat dissipation of the GaN chip. Generally speaking, the heat sink heat dissipation technology is to use a composite metal material with low thermal diffusivity to manufacture a micro heat sink so as to realize cooling of an electronic chip device, the temperature of a device does not change greatly with the size of heat energy transferred to the device, the miniaturization requirement of a heat dissipation device can be met, the heat sink heat dissipation technology is an effective way for reducing the temperature of a chip and ensuring the performance of the device, but an external heat sink heat dissipation structure is not beneficial to high-density and miniaturized three-dimensional integrated packaging, and the heat dissipation capability is not enough to meet the heat flux density of the high-power GaN chip three-dimensional integrated packaging.
The invention content is as follows:
the invention aims at high-power GaN devices (the heat flow density is not less than 500W/cm)2) The invention discloses a three-dimensional heterogeneous integration packaging method for realizing high-power GaN device layer heat dissipation based on a TSV (through silicon via) technology.
In order to solve the technical problem, the invention provides a packaging method of a three-dimensional heterostructure for realizing heat dissipation of a high-power GaN device layer, which comprises the following steps:
1) etching the back of the GaN chip to manufacture a first open micro-channel structure;
2) assembling a first substrate embedded with a first vertical micro-channel and a first metalized through-silicon-via on a metal packaging shell with a second open micro-channel; the first micro-channel and the first metalized through silicon hole are respectively arranged along the thickness direction of the first substrate; bonding the first GaN chip on one surface of the first substrate, which is far away from the metal packaging shell, so that the first open micro-channel of the first GaN chip is hermetically connected with the first vertical micro-channel of the first substrate;
3) integrating other microelectronic functional chips on one surface of the first substrate, which is far away from the metal packaging shell;
4) bonding a silicon supporting block which is embedded with a second vertical micro-channel and electrically interconnected with a second metalized silicon through hole on one surface of the first substrate far away from the metal packaging shell; the supporting blocks are positioned on two sides of the GaN chip; the second vertical micro-channel and the second metalized through silicon hole are respectively arranged along the thickness direction of the supporting block; the second vertical micro-channel is communicated with the first vertical micro-channel;
5) stacking and bonding a second substrate embedded with a third vertical micro-channel and electrically interconnected with a third metalized through silicon via on the supporting block; the third vertical micro-channel and the third metalized through silicon hole are respectively arranged along the thickness direction of the second substrate; the third vertical micro-channel is communicated with the second vertical micro-channel;
6) bonding a second GaN chip on one surface of the second substrate far away from the first substrate, so that the open micro-channel of the second GaN chip is hermetically connected with a third vertical micro-channel of the second substrate;
7) and integrating other microelectronic functional chips on the surface of the second substrate far away from the first substrate.
In a preferred embodiment: the first substrate is manufactured by the following method:
(1) providing a first substrate, and forming an open flow channel structure with a certain depth on the upper surface of the first substrate;
(2) providing a second substrate, and forming an open flow channel structure with a certain depth on the lower surface of the second substrate, wherein the structure of the open flow channel structure corresponds to that of the open flow channel structure of the first substrate;
(3) bonding and connecting the first substrate and the second substrate to enable the open micro-channel structures of the first substrate and the second substrate to be spliced to form the first vertical micro-channel;
(4) manufacturing a first metalized Through Silicon Via (TSV) for realizing electric vertical interconnection on the first substrate, wherein the first metalized through silicon via is arranged along the thickness direction of the first substrate;
(5) forming compact insulating layers on the upper surface and the lower surface of the first substrate, and forming a ring-shaped insulating layer on the side wall of the first metalized through silicon hole on the substrate;
(6) filling a conductive material in the first metalized through silicon via to form a conductive column, wherein a first metal interconnection layer and a second metal interconnection layer are respectively arranged on the upper end surface and the lower end surface of the conductive column;
(7) and the input/output ports of the first vertical micro-channels are respectively manufactured on the upper surface and the lower surface of the first substrate.
In a preferred embodiment: the method also comprises a substep between the step (3) and the step (4): and thinning processes are carried out on the upper surface and the lower surface of the first substrate through processes such as mechanical thinning, grinding, chemical polishing and the like, so that the overall thickness of the first substrate is reduced.
In a preferred embodiment: the open flow channel is one of a linear type, a turbulent flow column type and a snake shape.
In a preferred embodiment: the first substrate, the second substrate and the supporting block can be selected from double-polished high-resistance silicon materials.
In a preferred embodiment: and the first substrate and the second substrate are bonded through a wafer level bonding process.
In a preferred embodiment: the wafer level bonding process is one of wafer level silicon-silicon bonding and polymer bonding.
In a preferred embodiment: an insulating layer, a diffusion barrier layer and a conductive metal layer are sequentially arranged in the first metalized through silicon hole from outside to inside, and the diffusion barrier layer and the metal conductive layer form the vertical interconnection structure; the conductive metal layer includes a seed layer and a thickened metal layer.
In a preferred embodiment: the insulating layer is one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene and parylene; the diffusion barrier layer comprises at least one of Ta, TaN and TiW; the conductive metal layer comprises at least one of Cu, Al, Au and W;
in a preferred embodiment: the first metal interconnection layer and the second metal interconnection layer are respectively arranged in an insulated manner with the first substrate, and the insulating material is one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene or parylene;
the first metal interconnection layer and the second metal interconnection layer are sequentially arranged to be a diffusion barrier layer and a conductive metal layer, the conductive metal layer comprises a seed layer and a thickened metal layer, the diffusion barrier layer is at least one of Ta, TaN and TiW, and the conductive metal layer is at least one of Cu, Al, Au and W.
Compared with the prior art, the high-power GaN device is aimed at (the heat flow density is not less than 500W/cm)2) The invention provides a packaging method of a three-dimensional heterostructure for realizing the heat dissipation of a high-power GaN device layer, which utilizes a plurality of laminated substrates such as a GaN chip body, a TSV radio frequency adapter plate, a silicon supporting block and the like to realize the design of a three-dimensional folding micro-channel, micro-fluid flows into a bottom layer of a packaging shell and then is picked up to cool a hot spot of the GaN device layer, and then flows out from the bottom layer of the packaging shell, thereby overcoming the defects of the shunt design existing when the micro-channel embedded in the traditional TSV three-dimensional integration technology extends from the TSV adapter plate to the inside of the high-power GaN chip body, and the integration of the traditional three-dimensional micro-channel andand the method further realizes the three-dimensional radio frequency heterogeneous integration application with high manufacturability, high heat dissipation efficiency and high stability, and has important significance. The method has the following beneficial effects:
1) aiming at a high-power GaN device (the heat flux density is not less than 500W/cm)2) The cooperative solution of the three-dimensional heterogeneous integration and the device layer heat dissipation integration requirement makes up the blank of the application scheme of the three-dimensional heterogeneous integration;
2) the three-dimensional folding micro-channel design realizes the high-efficiency heat dissipation efficiency of the device level of the microelectronic chip;
3) the problems of shunt design, integration and compatible manufacturing of the traditional three-dimensional micro-channel and a packaging body-chip and the like when the embedded micro-channel of the traditional TSV three-dimensional integration technology extends from the TSV adapter plate to the inside of the high-power GaN chip body are solved;
4) expected to realize heat flow density as high as 1000W/cm2The heat dissipation capability of the hot spot.
Drawings
FIG. 1 is a process flow diagram of a first substrate;
FIG. 2 is a schematic view of a second substrate;
FIG. 3 is a schematic structural design of a silicon support block;
FIG. 4 is a schematic diagram of a package structure of a three-dimensional heterostructure for achieving high power GaN device layer heat dissipation;
FIG. 5 is a schematic diagram of a package structure of a three-dimensional heterostructure for achieving high power GaN device layer heat dissipation;
fig. 6 is a cross-sectional view of fig. 5 in the directions a-a, b-b, c-c, d-d.
Detailed Description
The following detailed description is made with reference to the accompanying drawings and examples.
Example 1
A package structure of a three-dimensional heterostructure for achieving heat dissipation of high power GaN device layers, as shown in fig. 4-6, comprising:
the first substrate 110, the first substrate 110 made of a high-resistivity silicon material (not less than 1000 Ω · cm) substrate, is composed of a first substrate 111 and a second substrate 112, the first substrate 110 has a front surface 000 and a back surface 001, and the first substrate 110 includes a first vertical micro channel 113 with a certain depth and a vertical interconnection structure. The front surface 000 of the first substrate 110 is provided with a micro-channel output port 114 corresponding to the size of the embedded micro-channel structure, and the back surface 001 is provided with a micro-channel input port 115 corresponding to the size of the embedded micro-channel structure 113; the vertical interconnection structure is formed by the following structure: the first substrate 110 has a plurality of independent first tsv 116 extending from the front surface 000 to the back surface 001, and the first tsv 116 is filled with a conductive material to form a conductive pillar 117. The front surface 000 and the back surface 001 of the first substrate 110 are respectively provided with a first metal interconnection layer 120 and a second metal interconnection layer 130 to serve as surface electrical transmission structures; an insulating layer 140 is disposed between each of the first metal interconnection layer 120 and the second metal interconnection layer 130 and the silicon substrate 110, and the upper and lower ends of the conductive post 117 are electrically connected to the first metal interconnection layer 120 and the second metal interconnection layer 130, respectively.
As shown in FIG. 2, the second substrate 210 made of a high-resistivity silicon material (≧ 1000 Ω · cm) substrate includes an embedded second vertical micro-channel structure 211 and a vertical interconnect structure. The second substrate 210 is provided with a second vertical micro channel structure 211 extending from the front surface 000 to the back surface 001; the vertical interconnection structure is formed by the following structure: the substrate 110 has a plurality of independent through silicon vias 116 extending from the front surface 000 to the back surface 001, and the through silicon vias 116 are filled with a conductive material to form conductive pillars 117. The front surface 000 and the back surface 001 of the substrate are respectively provided with a first metal interconnection layer 120 and a second metal interconnection layer 130 to serve as surface electrical transmission structures; an insulating layer 140 is disposed between each of the first metal interconnection layer 120 and the second metal interconnection layer 130 and the silicon substrate 110, and the upper and lower ends of the conductive post 117 are electrically connected to the first metal interconnection layer 120 and the second metal interconnection layer 130, respectively. In addition, the second substrate 210 may also be formed with a cavity 212 with a certain depth on the back side 001 of the substrate according to the requirement during the packaging application, so as to increase the packaging space under the condition of satisfying the mechanical strength of the package.
The supporting block 310, as shown in FIG. 3, is made of a high-resistivity silicon material (≧ 1000 Ω · cm) substrate, and the supporting block 310 includes a third vertical micro flow channel structure 211 and a vertical interconnect structure. The substrate 210 is provided with a third vertical micro flow channel structure 211 extending from the front surface 000 to the back surface 001; the vertical interconnection structure is formed by the following structure: the substrate 110 has a plurality of independent through silicon vias 116 extending from the front surface 000 to the back surface 001, and the through silicon vias 116 are filled with a conductive material to form conductive pillars 117. The front surface 000 and the back surface 001 of the substrate are respectively provided with a first metal interconnection layer 120 and a second metal interconnection layer 130 to serve as surface electrical transmission structures; an insulating layer 140 is disposed between each of the first metal interconnection layer 120 and the second metal interconnection layer 130 and the silicon substrate 110, and the upper and lower ends of the conductive post 117 are electrically connected to the first metal interconnection layer 120 and the second metal interconnection layer 130, respectively.
The first substrate 111 and the second substrate 112 are both double-polished high-resistance silicon substrates (not less than 1000 Ω · cm), a plurality of open flow channel structures 118 with certain depth are manufactured on the upper surface of the first substrate 111, a plurality of open flow channel structures 119 with certain depth are manufactured on the lower surface of the second substrate 112, the open flow channel structures 119 correspond to the open flow channel structures 118 of the first substrate 111, and the open flow channel structures 118 and 119 can be linear, burbling column type, snake-shaped and other micro-flow channel structures;
the first substrate 111 and the second substrate 112 are connected by a wafer-level bonding process to form the first substrate 110, and a first vertical micro channel 113 for heat dissipation in the first substrate 110 is formed. The bonding process is a silicon-silicon bonding process, a polymer bonding process and the like;
further, an insulating layer 140, a diffusion barrier layer and a conductive metal layer are sequentially arranged in the through silicon via 116 from outside to inside, wherein the conductive metal layer comprises a seed layer and a thickened metal layer, and the diffusion barrier layer and the metal conductive layer form the vertical interconnection structure; the first metal interconnection layer 120 and the second metal interconnection layer 130 are sequentially arranged as a diffusion barrier layer and a conductive metal layer, wherein the insulating layer 140 is made of one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene or parylene, the diffusion barrier layer is at least one of Ta, TaN and TiW, and the conductive metal layer is at least one of Cu, Al, Au and W.
Further, the pits 212 can be manufactured by wet etching, dry etching such as TMAH/KOH etching, DRIE and the like;
the manufacturing method of the first substrate 110 is as shown in fig. 1:
(1) providing a first substrate 111, double-polishing a high-resistance silicon material (more than or equal to 1000 omega cm) substrate, and forming an open flow channel structure 118 with a certain depth on the high-resistance silicon substrate by deep silicon etching (DRIE), laser and other processes;
(2) providing a second substrate 112, double-polishing a high-resistance silicon material (not less than 1000 Ω · cm) substrate, and forming an open flow channel structure 119 with a certain depth corresponding to that on the first substrate 111 on the high-resistance silicon substrate by deep silicon etching (DRIE), laser and other processes, as shown in fig. 1 (a);
(3) bonding and connecting the first substrate 111 and the second substrate 112 by using a bonding process such as silicon-silicon bonding or polymer bonding (e.g., BCB bonding) to form a sealed first vertical microchannel 113, thereby forming an embedded microchannel for heat dissipation in the first substrate 110;
(4) the back 001 of the first substrate 110 is thinned through processes of mechanical thinning, grinding, chemical polishing and the like, so that the overall thickness of the substrate is reduced, the thermal resistance is further reduced, the heat dissipation efficiency is improved, and the process difficulty is reduced for the subsequent metallization of the through silicon via 116;
(5) forming a through-silicon via 116 structure for electrical vertical interconnection on the substrate 110 by DRIE, laser, etc.;
(6) depositing a dense and continuous insulating layer 140 on the front surface 000 and the surface 001 of the substrate 110 by physical or chemical processes including PECVD, CVD, PVD, etc., and forming a ring-shaped insulating layer on the sidewall of the via 116 structure on the substrate 110, as shown in fig. 1 (b);
(7) a first metal interconnection layer 120 and a second metal interconnection layer 130 are formed by depositing metal on the front and back surfaces of the above structure, respectively, and a solid or hollow metal pillar is formed by depositing metal in the via 116 to form the conductive pillar 117. The specific method comprises the following steps: and manufacturing the barrier layer and the seed layer by an evaporation diffusion or sputtering process, and then depositing by a method process such as electroplating or chemical plating to form a metal conductive layer. Wherein the diffusion barrier layer is at least one of Ta, TaN, TiW, etc., and the metal conductive layer may be at least one of Cu, Al, Au, etc. The first metal interconnection layer 120 and the second metal interconnection layer 130 are electrically connected to the upper and lower end surfaces of the conductive pillar 117, respectively, so as to implement vertical interconnection.
(8) The micro-channel input port 115 and the micro-channel output port 114 are respectively manufactured on the upper and the lower sides of the cavity structure 113 for hermetically embedding the micro-channel in the substrate 110 by DRIE, laser and other processes, as shown in fig. 1 (c);
the method for packaging and applying the first substrate 110 is shown in fig. 1, and includes the following steps:
(1) preparing a first open micro-channel structure 2 on the back of a chip substrate by etching processes such as RIE, ICP, DRIE and the like on the back of a plurality of GaN power chips 1;
(2) assembling the first substrate 110 on the metal package housing 3 with the millimeter-scale second open microchannel by welding or bonding;
(3) the first GaN power chip 1 with the open flow channel structure 2 on the back substrate is bonded on the first base plate 110 of the structure formed in the step (2) in a sealing manner through graphical alignment bonding, is positioned on one side of the first base plate 110 far away from the metal packaging shell 3, and is electrically connected through wire bonding and other modes; such as at least one of gold-gold bonding, gold-tin bonding, and the like.
The second substrate 210 can refer to the content of the first substrate 110, and the two methods are similar to the first substrate 110 except that the second substrate does not need a silicon-silicon bonding process, i.e., the vertical embedded micro-channel structure 211 is directly fabricated on the high-resistance silicon substrate, and the fabrication process is the same as that of the first substrate 110, and thus the details are not repeated.
The options and the manufacturing method of the silicon supporting block 310 are substantially the same as those of the second substrate, and the contents of the first substrate 110 can be referred to, and the manufacturing process of the silicon supporting block is the same as that of the first substrate except that the silicon supporting block does not need to perform a silicon-silicon bonding process, and thus the details are not repeated.
The packaging structure of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer is shown in FIG. 4, and comprises the following steps:
1) etching the back of the GaN chip to manufacture a first open micro-channel structure;
2) assembling a first substrate embedded with a first vertical micro-channel and a first metalized through-silicon-via on a metal packaging shell with a second open micro-channel; the first micro-channel and the first metalized through silicon hole are respectively arranged along the thickness direction of the first substrate; bonding the first GaN chip on one surface of the first substrate, which is far away from the metal packaging shell, so that the first open micro-channel of the first GaN chip is hermetically connected with the first vertical micro-channel of the first substrate;
3) integrating other microelectronic functional chips on one surface of the first substrate, which is far away from the metal packaging shell;
4) bonding a silicon supporting block which is embedded with a second vertical micro-channel and electrically interconnected with a second metalized silicon through hole on one surface of the first substrate far away from the metal packaging shell; the silicon supporting blocks are positioned on two sides of the GaN chip; the second vertical micro-channel and the second metalized through silicon hole are respectively arranged along the thickness direction of the silicon supporting block; the second vertical micro-channel is communicated with the first vertical micro-channel;
5) stacking and bonding a second substrate which is embedded with a third vertical micro-channel and electrically interconnected with a third metalized through silicon via on a silicon supporting block; the third vertical micro-channel and the third metalized through silicon hole are respectively arranged along the thickness direction of the second substrate; the third vertical micro-channel is communicated with the second vertical micro-channel;
6) bonding a second GaN chip on one surface of the second substrate far away from the first substrate, so that the open micro-channel of the second GaN chip is hermetically connected with a third vertical micro-channel of the second substrate;
7) and integrating other microelectronic functional chips on the surface of the second substrate far away from the first substrate.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A packaging method for realizing a three-dimensional heterostructure for radiating a high-power GaN device layer is characterized by comprising the following steps:
1) etching the back of the GaN chip to manufacture a first open micro-channel structure;
2) assembling a first substrate embedded with a first vertical micro-channel and a first metalized through-silicon-via on a metal packaging shell with a second open micro-channel; the first vertical micro-channel and the first metalized through silicon hole are respectively arranged along the thickness direction of the first substrate; bonding the first GaN chip on one surface of the first substrate, which is far away from the metal packaging shell, so that the first open micro-channel of the first GaN chip is hermetically connected with the first vertical micro-channel of the first substrate;
3) integrating other microelectronic functional chips on one surface of the first substrate, which is far away from the metal packaging shell;
4) bonding a silicon supporting block which is embedded with a second vertical micro-channel and electrically interconnected with a second metalized silicon through hole on one surface of the first substrate far away from the metal packaging shell; the supporting blocks are positioned on two sides of the GaN chip; the second vertical micro-channel and the second metalized through silicon hole are respectively arranged along the thickness direction of the supporting block; the second vertical micro-channel is communicated with the first vertical micro-channel;
5) stacking and bonding a second substrate embedded with a third vertical micro-channel and electrically interconnected with a third metalized through silicon via on the supporting block; the third vertical micro-channel and the third metalized through silicon hole are respectively arranged along the thickness direction of the second substrate; the third vertical micro-channel is communicated with the second vertical micro-channel;
6) bonding a second GaN chip on one surface of the second substrate far away from the first substrate, so that the open micro-channel of the second GaN chip is hermetically connected with a third vertical micro-channel of the second substrate;
7) and integrating other microelectronic functional chips on the surface of the second substrate far away from the first substrate.
2. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 1, wherein: the first substrate is manufactured by the following method:
(1) providing a first substrate, and forming an open flow channel structure with a certain depth on the upper surface of the first substrate;
(2) providing a second substrate, and forming an open flow channel structure with a certain depth on the lower surface of the second substrate, wherein the structure of the open flow channel structure corresponds to that of the open flow channel structure of the first substrate;
(3) bonding and connecting the first substrate and the second substrate to enable the open micro-channel structures of the first substrate and the second substrate to be spliced to form the first vertical micro-channel;
(4) manufacturing a first metalized Through Silicon Via (TSV) for realizing electric vertical interconnection on the first substrate, wherein the first metalized through silicon via is arranged along the thickness direction of the first substrate;
(5) forming compact insulating layers on the upper surface and the lower surface of the first substrate, and forming a ring-shaped insulating layer on the side wall of the first metalized through silicon hole on the substrate;
(6) filling a conductive material in the first metalized through silicon via to form a conductive column, wherein a first metal interconnection layer and a second metal interconnection layer are respectively arranged on the upper end surface and the lower end surface of the conductive column;
(7) and the input/output ports of the first vertical micro-channels are respectively manufactured on the upper surface and the lower surface of the first substrate.
3. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 2, wherein: the method also comprises a substep between the step (3) and the step (4): and thinning processes are carried out on the upper surface and the lower surface of the first substrate through processes such as mechanical thinning, grinding, chemical polishing and the like, so that the overall thickness of the first substrate is reduced.
4. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 2, wherein: the open flow channel is one of a linear type, a turbulent flow column type and a snake shape.
5. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 2, wherein: the first substrate, the second substrate and the supporting block can be selected from double-polished high-resistance silicon materials.
6. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 2, wherein: and the first substrate and the second substrate are bonded through a wafer level bonding process.
7. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 6, wherein: the wafer level bonding process comprises wafer level silicon-silicon bonding and polymer bonding.
8. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 2, wherein: an insulating layer, a diffusion barrier layer and a conductive metal layer are sequentially arranged in the first metalized through silicon hole from outside to inside, and the diffusion barrier layer and the metal conductive layer form a vertical interconnection structure; the conductive metal layer includes a seed layer and a thickened metal layer.
9. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 8, wherein: the insulating layer is one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene and parylene; the diffusion barrier layer comprises at least one of Ta, TaN and TiW; the conductive metal layer comprises at least one of Cu, Al, Au and W.
10. The packaging method of the three-dimensional heterostructure for realizing the heat dissipation of the high-power GaN device layer as claimed in claim 2, wherein: the first metal interconnection layer and the second metal interconnection layer are respectively arranged in an insulated manner with the first substrate, and the insulating material is one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene or parylene;
the first metal interconnection layer and the second metal interconnection layer are sequentially arranged to be a diffusion barrier layer and a conductive metal layer, the conductive metal layer comprises a seed layer and a thickened metal layer, the diffusion barrier layer is at least one of Ta, TaN and TiW, and the conductive metal layer is at least one of Cu, Al, Au and W.
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