CN113241332B - Semiconductor structure with micro-channel, chip stacking structure and preparation method - Google Patents
Semiconductor structure with micro-channel, chip stacking structure and preparation method Download PDFInfo
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- CN113241332B CN113241332B CN202110469071.6A CN202110469071A CN113241332B CN 113241332 B CN113241332 B CN 113241332B CN 202110469071 A CN202110469071 A CN 202110469071A CN 113241332 B CN113241332 B CN 113241332B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
Abstract
The invention provides a semiconductor structure with a micro-channel, a chip stacking structure and a preparation method, wherein a barrier layer is formed on a semiconductor substrate and is etched to obtain a filling groove, an initial micro-channel body is obtained by etching the semiconductor substrate with partial thickness, then the semiconductor substrate on the side part of the initial micro-channel body is transversely etched to obtain the micro-channel body, and then an inlet and an outlet of the micro-channel are formed to communicate the inlet and the outlet of the micro-channel with the micro-channel body, so that the micro-channel is obtained. The micro-channel can be obtained by only one semiconductor substrate without using a silicon-silicon direct bonding technology, the requirements on the surface cleanliness and the flatness of the semiconductor substrate are reduced, the preparation difficulty and the complexity are further reduced, and the preparation method is simple.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor structure with a micro-channel, a chip stacking structure and a preparation method.
Background
Because the integration level and the packaging density of the chip are continuously improved, the volume is continuously reduced, the heat productivity of the unit area of the chip is continuously increased, and the temperature of a junction area of the chip is easily and rapidly increased, thereby having adverse effect on the performance of the chip. The heat dissipation problem of the chip has become a key element for the normal operation of the electronic equipment. The micro-channel structure has good heat dissipation effect. The micro-channel structure is suitable for passing cooling liquid, and the cooling liquid absorbs heat generated by the chip and transmits the heat to the outside, so that the purpose of heat dissipation of the device is achieved. At present, two silicon substrates are generally used to prepare a micro flow channel structure. Specifically, the micro flow channel units are formed on two silicon substrates, and then the two silicon substrates are combined into a whole by a silicon-silicon direct bonding technology, so that the two micro flow channel units form a closed micro flow channel.
However, the existing method for preparing the micro flow channel structure has extremely high requirements on surface cleanliness and flatness of the silicon substrate, thereby increasing the preparation difficulty and complexity.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defects of the existing preparation method of the micro flow channel structure that the preparation difficulty and complexity are high, thereby providing a semiconductor structure with a micro flow channel, a chip stacking structure and a preparation method.
The invention provides a preparation method of a semiconductor structure with a micro-channel, which comprises the following steps: providing a semiconductor substrate; forming a barrier layer on one side surface of the semiconductor substrate; etching the barrier layer and the semiconductor substrate with partial thickness to form a filling groove penetrating through the barrier layer and an initial micro-channel body positioned in the semiconductor substrate; transversely etching the semiconductor substrate on the side of the initial micro-channel body by taking the barrier layer as a mask, so that the initial micro-channel body forms a micro-channel body, and the width of the filling groove is smaller than that of the micro-channel body; forming a sealing layer in the filling groove after forming the micro flow channel body; and forming a micro-channel inlet and outlet on the front surfaces of the barrier layer, the sealing layer and the semiconductor substrate and/or the back surfaces of the barrier layer, the sealing layer and the semiconductor substrate, wherein the micro-channel inlet and outlet are communicated with the micro-channel body to form a micro-channel.
Optionally, the process for etching the barrier layer and the semiconductor substrate with a partial thickness includes a reactive ion etching process; and the process for transversely etching the semiconductor substrate on the side part of the initial micro-channel body by taking the barrier layer as a mask comprises an isotropic etching process.
Optionally, the material of the barrier layer comprises silicon dioxide, silicon nitride, gallium arsenide or aluminum nitride; the semiconductor substrate is a silicon substrate.
Optionally, the width of the filling groove is 1 μm to 10 μm; the width of the micro-channel body is 10-500 mu m.
Optionally, a sealing layer is formed in the filling groove by adopting a plasma enhanced chemical vapor deposition process; alternatively, the step of forming a sealing layer in the filling groove includes: forming a seed layer on the side wall of the filling groove; and forming a sealing body layer in the filling groove by using the seed layer as a growth matrix through an electroplating process, wherein the sealing body layer and the seed layer form a sealing layer.
Optionally, the method for preparing the semiconductor structure with the micro flow channel further comprises: forming a conductive connecting piece penetrating through the semiconductor substrate in the semiconductor substrate after forming the sealing layer in the filling groove and before forming the micro-channel inlet and outlet, wherein the conductive connecting piece is positioned on the side part of the micro-channel body; after the conductive connecting piece is formed, a first rewiring structure is formed on one side, opposite to the semiconductor substrate, of the barrier layer and the sealing layer, a second rewiring structure is formed on one side, opposite to the barrier layer and the sealing layer, of the semiconductor substrate, and the first rewiring structure and the second rewiring structure are electrically connected with the conductive connecting piece.
Optionally, the semiconductor structure is a first chip; the preparation method of the semiconductor structure with the micro flow channel further comprises the following steps: forming a device layer on the surface of one side, away from the semiconductor substrate, of the barrier layer and the sealing layer, wherein the device layer is electrically connected with the first rewiring structure and the conductive connecting piece; alternatively, the method for manufacturing a semiconductor structure having a micro flow channel further comprises: and forming a device layer on the surface of one side of the semiconductor substrate, which faces away from the barrier layer and the sealing layer, wherein the device layer is electrically connected with the second re-wiring structure and the conductive connecting piece.
Optionally, the semiconductor structure is a interposer or a first chip.
The invention also provides a preparation method of the chip stacking structure, which comprises the following steps: the semiconductor structure is formed, and the method for forming the semiconductor structure adopts the above method for preparing the semiconductor structure having the micro flow channel.
Optionally, the semiconductor structure is an interposer; the preparation method of the chip stacking structure further comprises the following steps: providing a substrate; arranging the adapter plate on the substrate, wherein the adapter plate is electrically connected with the substrate; and arranging a second chip on the adapter plate, wherein the second chip is electrically connected with the adapter plate.
Optionally, the substrate includes a through hole therein, the micro flow channel inlet and outlet of the adapter plate are arranged toward the substrate, and the through hole is communicated with the micro flow channel inlet and outlet; or the micro flow channel inlet and outlet are arranged away from the substrate.
Optionally, the semiconductor structures include a first semiconductor structure to an nth semiconductor structure, where N is an integer greater than or equal to 2; the preparation method of the chip stacking structure further comprises the following steps: providing a substrate; the substrate is sequentially provided with a first semiconductor structure to an Nth semiconductor structure from bottom to top, the first semiconductor structure is electrically connected with the substrate, a k +1 semiconductor structure is electrically connected with a k semiconductor structure, k is an integer larger than or equal to 1 and smaller than or equal to N-1, and an inlet and an outlet of a micro-channel of the first semiconductor structure are communicated with an inlet and an outlet of a micro-channel of the Nth semiconductor structure.
Optionally, the substrate includes a through hole therein, micro-channel inlets and outlets are formed on the front and back of the first semiconductor structure to the front and back of the N-1 th semiconductor structure, a micro-channel inlet and outlet is formed on one side of the N-1 th semiconductor structure facing the N-1 th semiconductor structure, and the through hole is communicated with the micro-channel inlet and outlet of the first semiconductor structure; or micro-channel inlets and outlets are formed from the front surface and the back surface of the second semiconductor structure to the front surface and the back surface of the Nth semiconductor structure, and the micro-channel inlets and outlets are formed in one side, facing the second semiconductor structure, of the first semiconductor structure.
Optionally, the first semiconductor structure is an interposer or a first chip; the second semiconductor structure to the Nth semiconductor structure are all first chips.
The present invention also provides a semiconductor structure having a micro flow channel, comprising: a semiconductor substrate; the barrier layer is positioned on one side surface of the semiconductor substrate and is provided with a filling groove; the semiconductor substrate with partial thickness at the bottom of the filling groove is provided with a micro-channel body, and the width of the filling groove is smaller than that of the micro-channel body; a sealing layer in the filling trench; and the inlet and the outlet of the micro-channel are positioned on the front sides of the barrier layer, the sealing layer and the semiconductor substrate and/or the back sides of the barrier layer, the sealing layer and the semiconductor substrate, and the inlet and the outlet of the micro-channel are communicated with the micro-channel body to form the micro-channel.
Optionally, the semiconductor structure with micro flow channels further comprises: the conductive connecting piece penetrates through the semiconductor substrate and is positioned on the side part of the micro-channel body; the first rewiring structure is positioned on the surface of one side, opposite to the semiconductor substrate, of the barrier layer and the sealing layer and is electrically connected with the conductive connecting piece; and the second rewiring structure is positioned on the surface of one side, back to the barrier layer and the sealing layer, of the semiconductor substrate, and is electrically connected with the conductive connecting piece.
Optionally, the semiconductor structure is a first chip; the semiconductor structure with micro flow channels further comprises: a device layer; the device layer is positioned on the surface of one side, away from the semiconductor substrate, of the barrier layer and the sealing layer, and is electrically connected with the first rewiring structure and the conductive connecting piece; or the device layer is positioned on the surface of one side, back to the barrier layer and the sealing layer, of the semiconductor substrate, and the device layer is electrically connected with the second re-wiring structure and the conductive connecting piece.
Optionally, the semiconductor structure is a interposer or a first chip.
The present invention also provides a chip stacking structure, comprising: the semiconductor structure with the micro-channel is provided.
Optionally, the semiconductor structure is an interposer; the chip stack structure further includes: a substrate; the semiconductor structure is arranged on the substrate and electrically connected with the substrate; a second chip disposed on the semiconductor structure, the second chip being electrically connected to the semiconductor structure.
Optionally, the chip stacking structure further includes: a substrate; the first semiconductor structure to the Nth semiconductor structure are sequentially arranged on the substrate from bottom to top, N is an integer greater than or equal to 2, and the first semiconductor structure is electrically connected with the substrate; the k +1 semiconductor structure is electrically connected with the k semiconductor structure, and k is an integer which is greater than or equal to 1 and less than or equal to N-1; and the micro-channel inlet and outlet of the first semiconductor structure are communicated with the micro-channel inlet and outlet of the Nth semiconductor structure.
Optionally, the first semiconductor structure is an interposer or a first chip; the second semiconductor structure to the Nth semiconductor structure are all first chips.
The technical scheme of the invention has the following advantages:
1. the preparation method of the semiconductor structure with the micro-channel provided by the invention comprises the steps of forming a barrier layer on a semiconductor substrate and etching the barrier layer to obtain a filling groove, etching the semiconductor substrate with partial thickness to obtain an initial micro-channel body, then transversely etching the semiconductor substrate at the side of the initial micro-channel body to obtain a micro-channel body, and a micro-channel inlet and outlet is formed on the front surfaces of the barrier layer, the sealing layer and the semiconductor substrate and/or the back surfaces of the barrier layer, the sealing layer and the semiconductor substrate, so that the micro-channel inlet and outlet is communicated with the micro-channel body to obtain a micro-channel, because the width of the filling groove is smaller than that of the micro flow channel body and the width of the filling groove is smaller, a sealing layer is easy to form in the filling groove, and the sealing layer can not fill the micro flow channel body. Therefore, the preparation method realizes the sealing of the micro-channel body by forming the sealing layer in the filling groove, namely, the micro-channel can be obtained by only one semiconductor substrate without bonding two semiconductor substrates by using a silicon-silicon direct bonding technology, so that the requirements on the surface cleanliness and the flatness of the semiconductor substrate are reduced, the preparation difficulty and the complexity are further reduced, and the preparation method is simple.
2. According to the preparation method of the semiconductor structure with the micro-channel, provided by the invention, the barrier layer is limited to be made of silicon dioxide, silicon nitride, gallium arsenide or aluminum nitride, and the semiconductor substrate is a silicon substrate, so that the etching degree of the barrier layer is smaller in the process of transversely etching the semiconductor substrate on the side part of the initial micro-channel body, and the width of the filling groove is ensured to be smaller than that of the micro-channel body, so that a sealing layer can be formed in the filling groove, and the forming time of the sealing layer is also shorter.
3. The preparation method of the chip stacking structure provided by the invention comprises the step of forming the semiconductor structure. The preparation method of the semiconductor structure realizes the sealing of the micro-channel body by forming the sealing layer in the filling groove, namely, the micro-channel can be obtained by only one semiconductor substrate without bonding two semiconductor substrates by using a silicon-silicon direct bonding technology, thereby reducing the requirements on the surface cleanliness and the flatness of the semiconductor substrate, further reducing the preparation difficulty and the complexity and having simple preparation method.
4. The semiconductor structure with the micro-channel only comprises one semiconductor substrate, the sealing of the micro-channel body is realized through the barrier layer and the sealing layer, the two semiconductor substrates are not required to be oppositely bonded, and the structure is simple.
5. The chip stacking structure provided by the invention comprises a semiconductor structure with a micro-channel, wherein the semiconductor structure only comprises one semiconductor substrate, the sealing of the micro-channel body is realized through a barrier layer and a sealing layer, two semiconductor substrates are not required to be oppositely bonded, and the structure is simple.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a process flow chart of a method for preparing a semiconductor structure having a micro flow channel provided in example 1;
FIGS. 2 to 8 are schematic structural views showing the fabrication process of the semiconductor structure having micro flow channels provided in example 1;
FIG. 9 is a top view of the first type of filled trench shown in FIG. 4;
FIG. 10 is a top view of the second type of filled trench shown in FIG. 4;
FIG. 11 is a top view of the third fill slot shown in FIG. 4;
fig. 12 is a first structural diagram of a chip stacking structure provided in embodiment 2;
fig. 13 is a second structural diagram of the chip stacking structure provided in embodiment 2;
fig. 14 is a schematic diagram of a third structure of a chip stacking structure provided in embodiment 2;
fig. 15 is a schematic diagram of a fourth structure of the chip stacking structure provided in embodiment 2.
Description of reference numerals:
1-a semiconductor substrate; 2-a barrier layer; 3-filling the groove; 4-initial micro-channel body; 5-micro flow channel body; 6-sealing layer; 71-inlet of micro-channel; 72-micro flow channel outlet; 8-a conductive connection; 9-a first rewiring structure; 10-a second redistribution structure; 11-a substrate; 111-a via; 12-a second chip; 13-a first semiconductor structure; 14-a second semiconductor structure; 15-a first glue filling layer; 16-a second adhesive glue layer; 17-bumps; 18-a sealing ring; 19-a second glue filling layer; 20-high bandwidth memory.
Detailed Description
As described in the background section, the existing methods for fabricating micro flow channel structures have extremely high requirements for surface cleanliness and flatness of silicon substrates, thereby increasing the difficulty and complexity of fabrication.
Making micro-channels in the interposer to cool the chip is an effective way to dissipate heat. At present, the method for manufacturing the micro-channel in the adapter plate mainly comprises the following two processes: one is that firstly, micro-channel units are respectively formed on two silicon substrates, and then the two silicon substrates are combined into a whole by a silicon-silicon direct bonding technology so that the two micro-channel units form a closed micro-channel, and then a TSV structure is prepared; the other method is to manufacture the TSV structure on two silicon substrates, and then bond the two silicon substrates through a solder layer to obtain a closed flow channel and realize the electrical communication of the TSV structure. However, the first method has extremely high requirements on surface cleanliness and flatness of the silicon substrate, thereby increasing the difficulty and complexity of preparation; the solder layer in the second method has a risk of being corroded by the cooling liquid introduced into the micro flow channel, and the stability of the structure is reduced.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
Referring to fig. 1, the present embodiment provides a method for preparing a semiconductor structure having a micro flow channel, comprising the steps of:
s1, providing a semiconductor substrate;
s2, forming a barrier layer on one side surface of the semiconductor substrate;
s3, etching the barrier layer and the semiconductor substrate with partial thickness to form a filling groove penetrating through the barrier layer and an initial micro-channel body located in the semiconductor substrate;
s4, transversely etching the semiconductor substrate on the side of the initial micro-channel body by taking the barrier layer as a mask, so that the initial micro-channel body forms the micro-channel body, and the width of the filling groove is smaller than that of the micro-channel body;
s5, forming a sealing layer in the filling groove after forming the micro flow channel body;
and S6, forming a micro-channel inlet and outlet on the front surfaces of the barrier layer, the sealing layer and the semiconductor substrate and/or the back surfaces of the barrier layer, the sealing layer and the semiconductor substrate, wherein the micro-channel inlet and outlet are communicated with the micro-channel body to form a micro-channel.
The preparation method of the semiconductor structure with the micro-flow channel comprises the steps of forming a barrier layer on a semiconductor substrate and etching the barrier layer to obtain a filling groove, etching the semiconductor substrate with partial thickness to obtain an initial micro-channel body, then transversely etching the semiconductor substrate at the side of the initial micro-channel body to obtain a micro-channel body, and a micro-channel inlet and outlet is formed on the front surfaces of the barrier layer, the sealing layer and the semiconductor substrate and/or the back surfaces of the barrier layer, the sealing layer and the semiconductor substrate, so that the micro-channel inlet and outlet is communicated with the micro-channel body to obtain a micro-channel, because the width of the filling groove is smaller than that of the micro flow channel body and the width of the filling groove is smaller, a sealing layer is easy to form in the filling groove, and the sealing layer can not fill the micro flow channel body. Therefore, the preparation method realizes the sealing of the micro-channel body by forming the sealing layer in the filling groove, namely, the micro-channel can be obtained by only one semiconductor substrate without bonding two semiconductor substrates by using a silicon-silicon direct bonding technology, so that the requirements on the surface cleanliness and the flatness of the semiconductor substrate are reduced, the preparation difficulty and the complexity are further reduced, and the preparation method is simple.
The method for fabricating the semiconductor structure having the micro flow channel will be described clearly and completely with reference to fig. 2 to 8.
Referring to fig. 2, in step S1, the semiconductor substrate 1 is provided.
Specifically, the semiconductor substrate 1 is a silicon substrate.
Referring to fig. 3, in step S2, a barrier layer 2 is formed on one side surface of the semiconductor substrate 1.
Specifically, the process of forming the barrier layer 2 on the surface of one side of the semiconductor substrate 1 is an oxidation process or a plasma enhanced chemical vapor deposition process; the material of the barrier layer 2 comprises silicon dioxide, silicon nitride, gallium arsenide or aluminum nitride, and the thickness of the barrier layer 2 is 1-20 μm; illustratively, the barrier layer 2 has a thickness of 1 μm, 3 μm, 5 μm, 10 μm, 15 μm, or 20 μm.
Referring to fig. 4, in step S3, the barrier layer 2 and a part of the thickness of the semiconductor substrate 1 are etched to form a filling trench 3 penetrating the barrier layer 2 and an initial micro flow channel body 4 in the semiconductor substrate 1.
Specifically, the process for etching the barrier layer 2 and the semiconductor substrate 1 with a part of thickness comprises a reactive ion etching process; the width of the filling groove 3 is 1 μm-10 μm, and exemplarily, the width of the filling groove 3 may be 1 μm, 2 μm, 3 μm, 5 μm, 7.5 μm, 9 μm or 10 μm; the depth of the initial micro-channel body 4 is 10-500 mu m; illustratively, the depth of the primary microchannel body 4 is 10 μm, 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm.
Referring to fig. 5, in step S4, the semiconductor substrate 1 on the side of the initial micro flow channel body 4 is laterally etched using the barrier layer 2 as a mask so that the initial micro flow channel body 4 forms a micro flow channel body 5, and the width of the filling channel 3 is smaller than the width of the micro flow channel body 5.
Specifically, the process for laterally etching the semiconductor substrate 1 on the side of the initial micro flow channel body 4 by using the barrier layer 2 as a mask includes an isotropic etching process, which may be a wet isotropic etching process or a dry isotropic etching process. The width of the micro flow channel body 5 is 10 μm to 500 μm, and illustratively, the width of the micro flow channel body 5 is 10 μm, 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm.
Referring to fig. 6, after the micro flow channel body 5 is formed, a sealing layer 6 is formed in the filling tank 3 in step S5.
Specifically, a sealing layer 6 is formed in the filling groove 3 by adopting a plasma enhanced chemical vapor deposition process; alternatively, the step of forming the sealing layer 6 in the filling groove 3 includes: forming a seed layer on the side wall of the filling groove 3; and forming a sealing body layer in the filling groove 3 by adopting an electroplating process and taking the seed layer as a growth matrix, wherein the sealing body layer and the seed layer form a sealing layer 6. The process of forming the seed layer may be a sputtering process. Further, the thickness of the sealing layer 6 is 1 μm to 20 μm, and illustratively, the thickness of the sealing layer 6 is 1 μm, 3 μm, 5 μm, 10 μm, 15 μm, or 20 μm.
It should be understood that when the sealing layer 6 is formed in the filling groove 3 by using a plasma enhanced chemical vapor deposition process, a sealing layer material is also deposited to a certain thickness on the surface of the side of the barrier layer 2 facing away from the semiconductor substrate 1; when a seed layer is formed on the side wall of the filling groove 3 by adopting a sputtering process, a seed layer material with a certain thickness is deposited on the bottom of the micro-channel body 5 and the surface of one side of the barrier layer 2, which is far away from the semiconductor substrate 1, and when a sealing body layer is formed in the filling groove 3 by adopting an electroplating process, a sealing body layer material with a partial thickness is deposited on one side of the barrier layer 2, which is far away from the semiconductor substrate 1. Since the width of the filling groove 3 is small, no sealing layer material or a small amount of sealing layer material is deposited at the bottom of the microchannel body 5 during the formation of the sealing layer 6, which does not affect the fluidity of the cooling fluid in the microchannel body.
Referring to fig. 8, in step S6, a microchannel inlet/outlet is formed in the front surfaces of the barrier layer 2, the sealing layer 6, and the semiconductor substrate 1 and/or the back surfaces of the barrier layer 2, the sealing layer 6, and the semiconductor substrate 1, and the microchannel inlet/outlet is communicated with the microchannel body 5 to form a microchannel.
Specifically, the process for forming the inlet and the outlet of the micro flow channel is an etching process; when a micro-channel inlet and outlet is formed on the front surfaces of the barrier layer 2, the sealing layer 6 and the semiconductor substrate 1, the barrier layer 2 and the sealing layer 6 are etched, the semiconductor substrate 1 with partial thickness can be continuously etched to obtain the micro-channel inlet and outlet, and the micro-channel inlet and outlet are communicated with the micro-channel body 5; when a micro-channel inlet and a micro-channel outlet are formed on the back surfaces of the barrier layer 2, the sealing layer 6 and the semiconductor substrate 1, etching is carried out on the semiconductor substrate 1 with partial thickness to obtain the micro-channel inlet and the micro-channel outlet, and the micro-channel inlet and the micro-channel outlet are communicated with the micro-channel body 5. The inlet and the outlet of the micro-channel comprise a micro-channel inlet 71 and a micro-channel outlet 72 which are separately arranged, and cooling liquid is suitable for entering the micro-channel body 5 from the micro-channel inlet 71 and flowing out from the micro-channel outlet 72.
In this embodiment, the semiconductor structure may be a micro flow channel structure, an interposer, or a first chip.
Specifically, referring to fig. 7, when the semiconductor structure is an interposer or a first chip, after the sealing layer 6 is formed in the filling groove 3 and before the micro flow channel inlet/outlet is formed, the conductive connecting part 8 penetrating through the semiconductor substrate 1 is formed in the semiconductor substrate 1, and the conductive connecting part 8 is located at the side of the micro flow channel body 5; after the conductive connection member 8 is formed, a first rewiring structure 9 is formed on a side of the barrier layer 2 and the sealing layer 6 facing away from the semiconductor substrate 1, a second rewiring structure 10 is formed on a side of the semiconductor substrate 1 facing away from the barrier layer 2 and the sealing layer 6, and the first rewiring structure 9 and the second rewiring structure 10 are electrically connected to the conductive connection member 8. According to the preparation method of the adapter plate or the first chip with the micro-channel, on one hand, the bonding of two semiconductor substrates is not required to be carried out by using a silicon-silicon direct bonding technology, so that the requirements on the surface cleanliness and the flatness of the semiconductor substrates are reduced, and the preparation difficulty and the complexity are further reduced; on the one hand, the welding flux layer is not needed to be used for bonding, and the risk that the welding flux layer is corroded by cooling liquid introduced into the micro-channel is avoided.
Wherein the first rewiring structure 9 includes a first insulating layer and a first rewiring layer located in the first insulating layer; the second rewiring structure 10 includes a second insulating layer and a second rewiring layer in the second insulating layer; the first insulating layer and the second insulating layer may be made of silicon dioxide, and the first redistribution layer and the second redistribution layer may be made of copper. When a micro-channel inlet and a micro-channel outlet are formed on the front surfaces of the barrier layer 2, the sealing layer 6 and the semiconductor substrate 1, the method further comprises the step of etching the first insulating layer; and when a micro-channel inlet and a micro-channel outlet are formed on the back surfaces of the barrier layer 2, the sealing layer 6 and the semiconductor substrate 1, the method also comprises the step of etching the second insulating layer.
Further, when the semiconductor structure is a first chip, the method for manufacturing a semiconductor structure having a micro flow channel further includes: forming a device layer (not shown in the figure) on the surface of the barrier layer 2 and the sealing layer 6 on the side away from the semiconductor substrate 1, wherein the device layer is electrically connected with the first rewiring structure 9 and the conductive connecting piece 8; alternatively, the method for manufacturing a semiconductor structure having a micro flow channel further comprises: and forming a device layer on the surface of the semiconductor substrate 1, which is opposite to the barrier layer 2 and the sealing layer 6, wherein the device layer is electrically connected with the second redistribution structure 10 and the conductive connecting piece 8.
When the device layer is located on the surface of the barrier layer 2 and the sealing layer 6 facing away from the semiconductor substrate 1, the device layer may be located below the first redistribution structure 9, or may be located separately from the first redistribution structure 9. Further, when the device layer may be located below the first rewiring structure 9, after the sealing layer 6 is formed in the filling groove 3, a device layer is formed on the surface of one side of the barrier layer 2 and the sealing layer 6 away from the semiconductor substrate 1, and then the first rewiring structure 9 covering the device layer is formed; when the device layer and the first redistribution structure 9 are arranged in a partitioned manner, after the sealing layer 6 is formed in the filling groove 3, the surfaces of the barrier layer 2 and the sealing layer 6, which are away from the semiconductor substrate 1, are divided into a device region and a redistribution region, and then the first redistribution structure 9 may be prepared in the redistribution region after the device layer is prepared in the device region, or the device layer may be prepared in the device region after the first redistribution structure 9 is prepared in the redistribution region.
When the device layer is located on the surface of the semiconductor substrate 1 on the side facing away from the barrier layer 2 and the sealing layer 6, the device layer may be located below the second redistribution structure 10 or may be provided separately from the second redistribution structure 10. Further, when the device layer is located below the second redistribution structure 10, the device layer may be formed on one side surface of the semiconductor substrate 1 before the barrier layer 2 is formed on the other side surface of the semiconductor substrate 1, followed by the preparation of the micro flow channel body 5, the conductive connection member 8, and the second redistribution structure 10; after the sealing layer 6 is formed in the filling groove 3 and before the micro flow channel inlet/outlet is formed, a device layer may be formed on the surface of the semiconductor substrate 1 on the side away from the barrier layer 2, and then the second redistribution structure 10 may be prepared. When the device layer and the second redistribution structure 10 are arranged in a partitioned manner, the surface of the semiconductor substrate 1 on the side away from the barrier layer 2 is partitioned into a device region and a redistribution region, the device layer may be prepared in the device region before the barrier layer 2 is formed on the surface of the semiconductor substrate 1 on the side, and the micro flow channel body 5, the conductive connecting member 8 and the second redistribution structure 10 may be prepared subsequently, or the second redistribution structure 10 may be prepared in the redistribution region after the device layer is prepared in the device region after the sealing layer 6 is formed in the filling groove 3, or the device layer may be prepared in the device region after the second redistribution structure 10 is prepared in the redistribution region.
It is to be understood that, in the present embodiment, the preparation sequence of the device layer, the micro flow channel body 5, the conductive connecting member 8, and the first re-wiring structure 9 or the second re-wiring structure 10 includes, but is not limited to, the above-mentioned sequence.
It is to be understood that the shapes of the microchannel body 5 and the filling channel 3 include, but are not limited to, straight line, zigzag, serpentine, spiral, or fin type; fig. 9 is a plan view of a straight-line-shaped filling groove 3, fig. 10 is a plan view of a serpentine-shaped filling groove 3, and fig. 11 is a plan view of a fin-type filling groove 3; the number of the micro-channel body 5 and the micro-channel inlets and outlets communicated with the micro-channel body 5 in the semiconductor structure can be 1 group or a plurality of discrete groups.
Referring to fig. 8, the present embodiment also provides a semiconductor structure having a micro flow channel, including: a semiconductor substrate 1; the barrier layer 2 is positioned on one side surface of the semiconductor substrate 1, and a filling groove 3 is formed in the barrier layer 2; the semiconductor substrate 1 with partial thickness at the bottom of the filling groove 3 is provided with a micro-channel body 5, and the width of the filling groove 3 is smaller than that of the micro-channel body 5; a sealing layer 6, the sealing layer 6 being located in the filling groove 3; and the inlet and the outlet of the micro-channel are positioned on the front sides of the barrier layer 2, the sealing layer 6 and the semiconductor substrate 1 and/or the back sides of the barrier layer 2, the sealing layer 6 and the semiconductor substrate 1, and the inlet and the outlet of the micro-channel are communicated with the micro-channel body 5 to form the micro-channel. The semiconductor structure with the micro-channel only comprises one semiconductor substrate 1, the barrier layer 2 and the sealing layer 6 realize the sealing of the micro-channel body 5, the two semiconductor substrates 1 are not required to be oppositely bonded, and the structure is simple.
In this embodiment, the semiconductor substrate 1 is a silicon substrate, and the material of the barrier layer 2 includes silicon dioxide, silicon nitride, gallium arsenide, or aluminum nitride; the width of the filling groove 3 is 1-10 μm, the width of the micro flow channel body 5 is 10-500 μm, and the thickness of the barrier layer 2 is 1-20 μm; the thickness of the sealing layer 6 is 1-20 μm; the depth of the initial micro-channel body 4 is 10-500 mu m; illustratively, the width of the filling trench 3 may be 1 μm, 2 μm, 3 μm, 5 μm, 7.5 μm, 9 μm, or 10 μm; the width of the micro flow channel body 5 is 10 μm, 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm or 500 μm; the thickness of the barrier layer 2 is 1 μm, 3 μm, 5 μm, 10 μm, 15 μm or 20 μm; the sealing layer 6 has a thickness of 1 μm, 3 μm, 5 μm, 10 μm, 15 μm, or 20 μm; the depth of the primary micro flow channel body 4 is 10 μm, 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm or 500 μm.
In this embodiment, the semiconductor structure may be a micro flow channel structure, an interposer, or a first chip.
Specifically, when the semiconductor structure is an interposer or a first chip, the semiconductor structure with a micro channel further includes: a conductive connection member 8 penetrating the semiconductor substrate 1, the conductive connection member 8 being located at a side portion of the micro flow channel body 5; a first rewiring structure 9 positioned on one side surface of the barrier layer 2 and the sealing layer 6 opposite to the semiconductor substrate 1, wherein the first rewiring structure 9 is electrically connected with the conductive connecting piece 8; and the second rewiring structure 10 is positioned on the surface of one side, facing away from the barrier layer 2 and the sealing layer 6, of the semiconductor substrate 1, and the second rewiring structure 10 is electrically connected with the conductive connecting piece 8.
Wherein the first rewiring structure 9 includes a first insulating layer and a first rewiring layer located in the first insulating layer; the second rewiring structure 10 includes a second insulating layer and a second rewiring layer in the second insulating layer; the first insulating layer and the second insulating layer may be made of silicon dioxide, and the first redistribution layer and the second redistribution layer may be made of copper.
Further, when the semiconductor structure is a first chip, the semiconductor structure having a micro flow channel further includes: a device layer (not shown); the device layer is positioned on the surface of one side, away from the semiconductor substrate 1, of the barrier layer 2 and the sealing layer 6, and the device layer is electrically connected with the first heavy wiring structure 9 and the conductive connecting piece 8; alternatively, the device layer is located on a surface of the semiconductor substrate 1 on a side facing away from the barrier layer 2 and the sealing layer 6, and the device layer is electrically connected to the second redistribution structure 10 and the conductive connection member 8.
When the device layer is located on the surface of the barrier layer 2 and the sealing layer 6 facing away from the semiconductor substrate 1, the device layer may be located below the first redistribution structure 9, or may be located separately from the first redistribution structure 9. When the device layer is located on the surface of the semiconductor substrate 1 on the side facing away from the barrier layer 2 and the sealing layer 6, the device layer may be located below the second redistribution structure 10 or may be provided separately from the second redistribution structure 10.
Example 2
The embodiment provides a method for preparing a chip stacking structure, which comprises the following steps: a semiconductor structure was formed, and the method for forming a semiconductor structure used the method for producing a semiconductor structure having a micro flow channel provided in example 1. The preparation method of the chip stack structure has all the advantages of the preparation method of the semiconductor structure, and details are not repeated herein.
As an alternative embodiment, the semiconductor structure is a interposer; referring to fig. 12 to 13, the method for manufacturing the chip stack structure further includes: providing a substrate 11; arranging the adapter plate on the substrate 11, wherein the adapter plate is electrically connected with the substrate 11; a second chip 12 is arranged on the interposer, the second chip 12 being electrically connected to the interposer. The substrate 11 may be an organic substrate or a ceramic substrate.
Specifically, referring to fig. 12, a through hole 111 is included in the substrate 11, an inlet and an outlet of the micro flow channel of the adapter plate are disposed toward the substrate 11, and the through hole 111 is communicated with the inlet and the outlet of the micro flow channel; alternatively, referring to fig. 13, the microchannel inlet/outlet is located away from the substrate 11.
Further, the method for manufacturing the chip stack structure further includes: forming a first filling adhesive layer 15, wherein the first filling adhesive layer 15 is located between the substrate 11 and the interposer to fix the interposer on the substrate 11, the first filling adhesive layer 15 includes a plurality of bumps 17, and the bumps 17 are electrically connected to the substrate 11 and the second redistribution structure 10; form first bonding glue film, first bonding glue film is located second chip 12 with be used for between the keysets with second chip 12 is fixed on the keysets, just include a plurality of bumps 17 in the first bonding glue film, bump 17 electricity is connected second chip 12 and first heavy wiring structure 9. The second chips 12 are normal chips or flip chips, and the number of the second chips 12 is greater than or equal to 1. Referring to fig. 12, when the substrate 11 includes a through hole 111 therein, a sealing ring 18 is disposed in the first adhesive filling layer 15, and the sealing ring 18 is located between the micro flow channel inlet/outlet and the through hole 111 to prevent the cooling liquid from entering the first adhesive filling layer 15.
As another alternative, referring to fig. 14 to 15, the semiconductor structures include first to nth semiconductor structures 13 to 15, N being an integer greater than or equal to 2; the preparation method of the chip stacking structure further comprises the following steps: providing a substrate 11; the substrate 11 is sequentially provided with a first semiconductor structure 13 to an Nth semiconductor structure from bottom to top, the first semiconductor structure 13 is electrically connected with the substrate 11, a k +1 th semiconductor structure is electrically connected with a kth semiconductor structure, k is an integer which is more than or equal to 1 and less than or equal to N-1, and a micro flow channel inlet and a micro flow channel outlet of the first semiconductor structure 13 are communicated with a micro flow channel inlet and a micro flow channel outlet of the Nth semiconductor structure. The first semiconductor structure 13 is an interposer or a first chip; the second semiconductor structure 14 to the nth semiconductor structure are all first chips. As shown in fig. 14-15, the semiconductor structure includes a first semiconductor structure 13 through a second semiconductor structure 14.
Specifically, referring to fig. 14, the substrate 11 includes a through hole 111 therein, micro flow channel inlets and outlets are formed on the front and back of the first semiconductor structure 13 to the front and back of the N-1 th semiconductor structure, a micro flow channel inlet and outlet is formed on one side of the N-1 th semiconductor structure facing the N-1 th semiconductor structure, and the through hole 111 is communicated with the micro flow channel inlet and outlet of the first semiconductor structure 13; alternatively, referring to fig. 15, the front surface and the back surface of the second semiconductor structure 14 to the front surface and the back surface of the nth semiconductor structure are formed with micro flow channel ports, and the first semiconductor structure 13 is provided with micro flow channel ports on the side facing the second semiconductor structure 14.
Further, the method for manufacturing the chip stack structure further includes: forming a second adhesive filling layer 19, wherein the second adhesive filling layer 19 is located between the substrate 11 and the first semiconductor structure 13 to fix the first semiconductor structure 13 on the substrate 11, and the second adhesive filling layer 19 includes a plurality of bumps 17, and the bumps 17 are electrically connected to the substrate 11 and the first semiconductor structure 13; form second bonding glue film 16, second bonding glue film 16 is located between kth semiconductor structure and the (k + 1) th semiconductor structure, just including a plurality of bumps and sealing ring 18 in the second bonding glue film 16, the kth semiconductor structure and the (k + 1) th semiconductor structure are connected to the bump electricity, sealing ring 18 is located between the miniflow channel of the (k) th semiconductor structure is imported and exported and the miniflow channel of the (k + 1) th semiconductor structure to avoid the coolant liquid to get into second bonding glue film 16. As shown in fig. 14, when the substrate 11 includes a through hole 111 therein, a sealing ring 18 is disposed in the second adhesive filling layer 19, and the sealing ring 18 is located between the micro flow channel inlet/outlet of the first semiconductor structure 13 and the through hole 111 to prevent the cooling liquid from entering the second adhesive filling layer 19.
As an alternative embodiment, referring to fig. 14 to 15, the method for manufacturing the chip stack structure further includes: a high bandwidth memory 20 is disposed on the nth semiconductor structure, the high bandwidth memory 20 being electrically connected to the nth semiconductor structure.
The present embodiment also provides a chip stacking structure including the semiconductor structure having a micro flow channel provided in embodiment 1. The chip stack structure has all the advantages of the semiconductor structure, and is not described in detail herein.
As an alternative embodiment, the semiconductor structure is a interposer; referring to fig. 12 to 13, the chip stacking structure further includes: a substrate 11; the semiconductor structure is arranged on the substrate 11, and the semiconductor structure is electrically connected with the substrate 11; a second chip 12 disposed on the semiconductor structure, the second chip 12 being electrically connected to the semiconductor structure. The substrate 11 may be an organic substrate or a ceramic substrate.
Specifically, referring to fig. 12, a through hole 111 is included in the substrate 11, an inlet and an outlet of the micro flow channel of the adapter plate are disposed toward the substrate 11, and the through hole 111 is communicated with the inlet and the outlet of the micro flow channel; alternatively, referring to fig. 13, the microchannel inlet/outlet is located away from the substrate 11.
Further, the chip stack structure further includes: the first adhesive filling layer 15 is positioned between the substrate 11 and the interposer, the first adhesive filling layer 15 is used for fixing the interposer on the substrate 11, the first adhesive filling layer 15 comprises a plurality of bumps 17, and the bumps 17 are electrically connected with the substrate 11 and the second redistribution structure 10; be located second chip 12 with first bonding glue film between the keysets, first bonding glue film be used for with second chip 12 is fixed on the keysets, just include a plurality of bumps 17 in the first bonding glue film, bump 17 electricity is connected second chip 12 and first heavy wiring structure 9. The second chips 12 are normal chips or flip chips, and the number of the second chips 12 is greater than or equal to 1. When the substrate 11 includes the through hole 111 therein, a sealing ring 18 is disposed in the first adhesive filling layer 15, and the sealing ring 18 is located between the micro flow channel inlet/outlet and the through hole 111 to prevent the cooling liquid from entering the first adhesive filling layer 15.
As another alternative, referring to fig. 14 to 15, the semiconductor structures include first to nth semiconductor structures 13 to 15, N is an integer of 2 or more; the preparation method of the chip stacking structure further comprises the following steps: providing a substrate 11; the substrate 11 is sequentially provided with a first semiconductor structure 13 to an Nth semiconductor structure from bottom to top, the first semiconductor structure 13 is electrically connected with the substrate 11, a k +1 th semiconductor structure is electrically connected with a kth semiconductor structure, k is an integer which is more than or equal to 1 and less than or equal to N-1, and a micro flow channel inlet and a micro flow channel outlet of the first semiconductor structure 13 are communicated with a micro flow channel inlet and a micro flow channel outlet of the Nth semiconductor structure. The first semiconductor structure 13 is an interposer or a first chip; the second semiconductor structure 14 to the nth semiconductor structure are all first chips. As shown in fig. 14-15, the semiconductor structure includes a first semiconductor structure 13 through a second semiconductor structure 14.
Specifically, referring to fig. 14, the substrate 11 includes a through hole 111 therein, micro flow channel inlets and outlets are formed on the front and back of the first semiconductor structure 13 to the front and back of the N-1 th semiconductor structure, a micro flow channel inlet and outlet is formed on one side of the N-1 th semiconductor structure facing the N-1 th semiconductor structure, and the through hole 111 is communicated with the micro flow channel inlet and outlet of the first semiconductor structure 13; alternatively, referring to fig. 15, the front surface and the back surface of the second semiconductor structure 14 to the front surface and the back surface of the nth semiconductor structure are formed with micro flow channel ports, and the first semiconductor structure 13 is provided with micro flow channel ports on the side facing the second semiconductor structure 14.
Further, the chip stack structure further includes: a second adhesive filling layer 19 located between the substrate 11 and the first semiconductor structure 13, wherein the second adhesive filling layer 19 is used to fix the first semiconductor structure 13 on the substrate 11, and the second adhesive filling layer 19 includes a plurality of bumps 17, and the bumps 17 are electrically connected to the substrate 11 and the first semiconductor structure 13; the second bonding glue layer 16 is located between the kth semiconductor structure and the (k + 1) th semiconductor structure, the second bonding glue layer 16 comprises a plurality of salient points and a sealing ring 18, the salient points are electrically connected with the kth semiconductor structure and the (k + 1) th semiconductor structure, and the sealing ring 18 is located between the micro flow channel inlet and outlet of the kth semiconductor structure and the micro flow channel inlet and outlet of the (k + 1) th semiconductor structure so as to prevent cooling liquid from entering the second bonding glue layer 16. As shown in fig. 14, when the substrate 11 includes a through hole 111 therein, a sealing ring 18 is disposed in the second adhesive filling layer 19, and the sealing ring 18 is located between the micro flow channel inlet/outlet of the first semiconductor structure 13 and the through hole 111 to prevent the cooling liquid from entering the second adhesive filling layer 19.
As an alternative embodiment, referring to fig. 14 to 15, the chip stacking structure further includes: a high bandwidth memory 20 located on the second semiconductor structure 14, the high bandwidth memory 20 being electrically connected to the second semiconductor structure 14.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications derived therefrom are intended to be within the scope of the invention.
Claims (22)
1. A method for preparing a semiconductor structure with a micro-channel is characterized by comprising the following steps:
providing a semiconductor substrate;
forming a barrier layer on one side surface of the semiconductor substrate;
etching the barrier layer and the semiconductor substrate with partial thickness to form a filling groove penetrating through the barrier layer and an initial micro-channel body positioned in the semiconductor substrate;
transversely etching the semiconductor substrate on the side of the initial micro-channel body by taking the barrier layer as a mask, so that the initial micro-channel body forms a micro-channel body, and the width of the filling groove is smaller than that of the micro-channel body;
forming a sealing layer in the filling groove after forming the micro flow channel body;
and forming a micro-channel inlet and outlet on the front surfaces of the barrier layer, the sealing layer and the semiconductor substrate and/or the back surfaces of the barrier layer, the sealing layer and the semiconductor substrate, wherein the micro-channel inlet and outlet are communicated with the micro-channel body to form a micro-channel.
2. The method of claim 1, wherein the etching process of the barrier layer and the semiconductor substrate of a partial thickness includes a reactive ion etching process; and the process for transversely etching the semiconductor substrate on the side part of the initial micro-channel body by taking the barrier layer as a mask comprises an isotropic etching process.
3. The method of claim 1, wherein the material of the barrier layer includes silicon dioxide, silicon nitride, gallium arsenide, or aluminum nitride; the semiconductor substrate is a silicon substrate.
4. The method for producing a semiconductor structure having a micro flow channel according to claim 1, wherein the width of the filling groove is 1 μm to 10 μm; the width of the micro-channel body is 10-500 mu m.
5. The method of claim 1, wherein a sealing layer is formed in the filling trench by a plasma enhanced chemical vapor deposition process;
alternatively, the step of forming a sealing layer in the filling groove includes: forming a seed layer on the side wall of the filling groove; and forming a sealing body layer in the filling groove by adopting an electroplating process and taking the seed layer as a growth matrix, wherein the sealing body layer and the seed layer form a sealing layer.
6. The method of claim 1, further comprising: forming a conductive connecting piece penetrating through the semiconductor substrate in the semiconductor substrate after forming the sealing layer in the filling groove and before forming the micro-channel inlet and outlet, wherein the conductive connecting piece is positioned on the side part of the micro-channel body;
after the conductive connecting piece is formed, a first rewiring structure is formed on one side, opposite to the semiconductor substrate, of the barrier layer and the sealing layer, a second rewiring structure is formed on one side, opposite to the barrier layer and the sealing layer, of the semiconductor substrate, and the first rewiring structure and the second rewiring structure are electrically connected with the conductive connecting piece.
7. The method of claim 6, wherein the semiconductor structure is a first chip;
the preparation method of the semiconductor structure with the micro flow channel further comprises the following steps: forming a device layer on the surface of one side, away from the semiconductor substrate, of the barrier layer and the sealing layer, wherein the device layer is electrically connected with the first rewiring structure and the conductive connecting piece; alternatively, the method for preparing a semiconductor structure having a micro flow channel further comprises: and forming a device layer on the surface of one side of the semiconductor substrate, which faces away from the barrier layer and the sealing layer, wherein the device layer is electrically connected with the second re-wiring structure and the conductive connecting piece.
8. The method of claim 1, wherein the semiconductor structure is an interposer or a first chip.
9. A method for preparing a chip stack structure, comprising: a method of forming a semiconductor structure using the method of manufacturing a semiconductor structure having a micro flow channel according to any one of claims 1 to 8.
10. The method of manufacturing a chip stack structure according to claim 9, wherein the semiconductor structure is an interposer;
the preparation method of the chip stacking structure further comprises the following steps: providing a substrate; arranging the adapter plate on the substrate, wherein the adapter plate is electrically connected with the substrate; and arranging a second chip on the adapter plate, wherein the second chip is electrically connected with the adapter plate.
11. The method for preparing a chip stacking structure according to claim 10, wherein the substrate includes a through hole therein, the micro flow channel inlet/outlet of the interposer is disposed toward the substrate, and the through hole is communicated with the micro flow channel inlet/outlet; or the micro flow channel inlet and outlet are arranged away from the substrate.
12. The method of manufacturing a chip stack structure according to claim 9, wherein the semiconductor structures include first to nth semiconductor structures, N being an integer greater than or equal to 2;
the preparation method of the chip stacking structure further comprises the following steps: providing a substrate; the substrate is provided with a first semiconductor structure to an Nth semiconductor structure from bottom to top in sequence, the first semiconductor structure is electrically connected with the substrate, the k +1 th semiconductor structure is electrically connected with the k-th semiconductor structure, k is an integer which is more than or equal to 1 and less than or equal to N-1, and the micro flow channel of the first semiconductor structure is imported and exported to the micro flow channel of the Nth semiconductor structure and is communicated with the micro flow channel of the Nth semiconductor structure.
13. The method for preparing a chip stack structure according to claim 12, wherein the substrate includes a through hole therein, the front and back surfaces of the first semiconductor structure to the front and back surfaces of the N-1 th semiconductor structure are each formed with a microchannel inlet/outlet, a microchannel inlet/outlet is provided in the N-1 th semiconductor structure on a side facing the N-1 th semiconductor structure, and the through hole is communicated with the microchannel inlet/outlet of the first semiconductor structure;
or micro-channel inlets and outlets are formed from the front surface and the back surface of the second semiconductor structure to the front surface and the back surface of the Nth semiconductor structure, and the micro-channel inlets and outlets are formed in one side, facing the second semiconductor structure, of the first semiconductor structure.
14. The method for manufacturing a chip stack structure according to claim 12 or 13, wherein the first semiconductor structure is an interposer or a first chip; the second semiconductor structure to the Nth semiconductor structure are all first chips.
15. A semiconductor structure having a micro flow channel, which is produced by the method for producing a semiconductor structure having a micro flow channel according to any one of claims 1 to 8, comprising:
a semiconductor substrate;
the barrier layer is positioned on one side surface of the semiconductor substrate and is provided with a filling groove;
the semiconductor substrate with partial thickness at the bottom of the filling groove is provided with a micro-channel body, and the width of the filling groove is smaller than that of the micro-channel body;
a sealing layer in the filling trench;
and the inlet and the outlet of the micro-channel are positioned on the front sides of the barrier layer, the sealing layer and the semiconductor substrate and/or the back sides of the barrier layer, the sealing layer and the semiconductor substrate, and the inlet and the outlet of the micro-channel are communicated with the micro-channel body to form the micro-channel.
16. The semiconductor structure having a micro flow channel of claim 15, further comprising:
a conductive connection member penetrating through the semiconductor substrate, the conductive connection member being located at a side portion of the micro flow channel body;
the first rewiring structure is positioned on the surface of one side, opposite to the semiconductor substrate, of the barrier layer and the sealing layer and is electrically connected with the conductive connecting piece;
and the second rewiring structure is positioned on the surface of one side, back to the barrier layer and the sealing layer, of the semiconductor substrate, and is electrically connected with the conductive connecting piece.
17. The semiconductor structure with a micro flow channel of claim 16, wherein the semiconductor structure is a first chip; the semiconductor structure with the micro flow channel further comprises: a device layer;
the device layer is positioned on the surface of one side, away from the semiconductor substrate, of the barrier layer and the sealing layer, and is electrically connected with the first rewiring structure and the conductive connecting piece; or the device layer is positioned on the surface of one side, back to the barrier layer and the sealing layer, of the semiconductor substrate, and the device layer is electrically connected with the second re-wiring structure and the conductive connecting piece.
18. The semiconductor structure with a micro flow channel of claim 15, wherein the semiconductor structure is an interposer or a first chip.
19. A chip stacking structure, comprising: the semiconductor structure having a micro flow channel according to any one of claims 15 to 18.
20. The chip stack structure according to claim 19, wherein the semiconductor structure is an interposer;
the chip stack structure further includes: a substrate; the semiconductor structure is arranged on the substrate and electrically connected with the substrate; a second chip disposed on the semiconductor structure, the second chip being electrically connected to the semiconductor structure.
21. The chip stack structure according to claim 19, further comprising: a substrate; the first semiconductor structure to the Nth semiconductor structure are arranged on the substrate in sequence from bottom to top, N is an integer larger than or equal to 2, and the first semiconductor structure is electrically connected with the substrate; the k +1 semiconductor structure is electrically connected with the k semiconductor structure, and k is an integer which is greater than or equal to 1 and less than or equal to N-1; and the micro-channel inlet and outlet of the first semiconductor structure are communicated with the micro-channel inlet and outlet of the Nth semiconductor structure.
22. The chip stack structure according to claim 21, wherein the first semiconductor structure is an interposer or a first chip; the second semiconductor structure to the Nth semiconductor structure are all first chips.
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