CN115050730A - Packaging structure with double-sided heat dissipation structure and manufacturing method thereof - Google Patents
Packaging structure with double-sided heat dissipation structure and manufacturing method thereof Download PDFInfo
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- CN115050730A CN115050730A CN202210740051.2A CN202210740051A CN115050730A CN 115050730 A CN115050730 A CN 115050730A CN 202210740051 A CN202210740051 A CN 202210740051A CN 115050730 A CN115050730 A CN 115050730A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a packaging structure with a double-sided heat dissipation structure, which comprises the double-sided heat dissipation structure and N chip sets. Wherein double-sided heat radiation structure includes N chip chamber, and the upper and lower both sides in every chip chamber all are provided with heat radiation module, and N chipsets set sets up respectively in N chip chamber, and the accessible double-sided heat radiation structure carries out the electricity and connects.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure with a double-sided heat dissipation structure and a manufacturing method thereof.
Background
The development of semiconductor packages is progressing toward precision and miniaturization, and from the early stage of plug-in packages to surface mount high density packages, the connection of packages and printed circuit boards is gradually progressing from a side form to a face array form, and the connection of chips and packages is progressing to flip chip packages in the face array form. However, as the number of transistors in a chip increases, the amount of heat generated by the chip also increases. Therefore, the device heat generation density is increasing without a large increase in chip area.
In the existing 2.5D or 3D stack package, a plurality of chips with high power density are usually stacked, and plastic package is mostly adopted for plastic package, so that the heat dissipation path from the chip to a package shell is long, the thermal resistance is large, heat is difficult to dissipate, and the temperature of the chip is easily limited to exceed the allowable temperature or power density.
Disclosure of Invention
In order to solve the heat dissipation problem of the high power density stacked package, an aspect of the present invention provides a package structure having a double-sided heat dissipation structure, including:
the double-sided heat dissipation structure comprises N chip cavities, and heat dissipation modules are arranged on the upper side and the lower side of each chip cavity; and
and the N chip groups are respectively arranged in the N chip cavities of the double-sided heat dissipation structure, wherein the N chip groups are electrically connected through the double-sided heat dissipation structure.
Further, the double-sided heat dissipation structure includes:
an L-layer micro-channel adapter plate;
the chip cavity adapter plate is arranged between the two adjacent layers of micro-channel adapter plates, and is provided with a through hole which forms a closed chip cavity together with the two adjacent layers of micro-channel adapter plates; and
and the liquid inlet channel and the liquid outlet channel penetrate through the L-layer micro-channel adapter plate and the chip cavity adapter plate and are communicated with micro-channels on the micro-channel adapter plate.
Furthermore, the micro-channel adapter plate and the chip cavity adapter plate are made of semiconductor materials or ceramics.
Further, a first sealing ring is arranged between the micro-channel adapter plate and the chip cavity adapter plate, and the first sealing ring is arranged at the liquid inlet channel and the liquid outlet channel.
Further, the first sealing ring is made of solder or sealant.
Furthermore, a silicon through hole and/or a first signal interconnection structure are/is arranged on the micro-channel adapter plate.
Further, the double-sided heat dissipation structure further includes:
the base plate, set up in double-sided heat radiation structure's bottom, and be provided with the second sealing ring between its and the miniflow way keysets of bottom, the base plate includes:
the liquid inlet and the liquid outlet respectively correspond to the liquid inlet channel and the liquid outlet channel, and the second sealing rings are arranged at the liquid inlet and the liquid outlet; and
the second signal interconnection structure is electrically connected with the micro-channel adapter plate; and
and the shell is arranged on the substrate and coats the N layers of micro-channel adapter plates and the chip cavity adapter plate.
Further, the housing is made of metal or a material having electromagnetic compatibility.
Further, the chipset comprises a single chip or a plurality of stacked chips, wherein:
the single chip is electrically connected to the lower micro-channel adapter plate by adopting a flip chip bonding technology, and a heat-conducting interface material is arranged between the back surface of the single chip and the upper micro-channel adapter plate; and
the stacked chips are formed in a flip-chip bonding or lead bonding mode, wherein the chip on the topmost layer is in flip-chip bonding, and a heat conduction interface material is arranged between the back surface of the chip on the topmost layer and the upper micro-channel adapter plate.
Another aspect of the present invention provides a method for manufacturing the package structure, comprising:
forming a micro-channel adapter plate and a chip cavity adapter plate;
forming a chipset;
stacking the micro-channel adapter plate, the chip cavity adapter plate and the chip set from top to bottom; and
the substrates are bonded and the housing is formed.
Further, the melting point of the solder used for each bonding is different.
The invention provides a packaging structure with a double-sided heat dissipation structure and a manufacturing method thereof. Simultaneously in order to satisfy the requirement of thermal management, all adopted two-sided radiating mode on every chip chamber, promptly the upper and lower both sides in chip chamber all are provided with the miniflow channel module, and then make high power density single-chip or 3D pile up the miniflow channel module effluvium of heat accessible upper and lower face that the chip produced. By the packaging structure, system-level high-density heterogeneous integration of a high-power-density chip, such as a radio frequency system, a high-performance computing system and the like, can be realized, and 3D integration with more layers can be realized under the condition of meeting the requirement of thermal management.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 is a schematic cross-sectional view illustrating a package structure having a double-sided heat dissipation structure according to an embodiment of the invention; and
fig. 2 illustrates a flow diagram for forming a package structure with a double-sided heat dissipation structure according to an embodiment of the invention.
Detailed Description
In the following description, the present invention is described with reference to examples. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention describes the process steps in a specific order, however, this is only for the purpose of illustrating the specific embodiment, and does not limit the sequence of the steps. Rather, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
In order to solve the heat dissipation problem of high power density and 3D stacked package, the thermal resistance from the chip junction to the environment is reduced. The invention provides a packaging structure with a double-sided heat dissipation structure and a manufacturing method thereof, wherein a plurality of layers of chip cavities are designed, and micro channels are arranged on the upper side and the lower side of each layer of chip cavity for heat dissipation, so that heat generated by a high-power-density single chip or a 3D stacked chip can be quickly dissipated to the air, and the number of layers of 3D integration can be increased on the premise of meeting the heat management requirement. The solution of the invention is further described below with reference to the accompanying drawings of embodiments.
Fig. 1 is a schematic cross-sectional view illustrating a package structure having a double-sided heat dissipation structure according to an embodiment of the invention. As shown in fig. 1, a package structure with a double-sided heat dissipation structure includes a double-sided heat dissipation structure 001 and a chipset 002, wherein the chipset 002 is disposed inside the double-sided heat dissipation structure 001, so that both sides of the chipset can dissipate heat through a heat dissipation module.
The double-sided heat dissipation structure 001 includes N chip cavities 012, and the upper and lower both sides of each chip cavity 012 all are provided with heat dissipation module. In the embodiment shown in fig. 1, a micro flow channel adapter plate is used as the heat dissipation module. It should be understood that in other embodiments of the present invention, an interposer having a micro-jetting structure may also be used as a heat dissipation module, for example.
As shown in fig. 1, the double-sided heat dissipation structure 001 includes L layers of micro flow channel adapter plates 101, and a chip cavity adapter plate 102 is disposed between each two layers of micro flow channel adapter plates. At least one through hole is formed in the chip cavity adapter plate 102, and meanwhile, the chip cavity adapter plate 102 is connected with the micro channel adapter plate 101 in a sealing mode, so that the through hole and the two adjacent layers of micro channel adapter plates 101 can form a closed chip cavity 012 together.
Two sides of the chip cavities 012 are provided with a liquid inlet channel 103 and a liquid outlet channel 104, the liquid inlet channel 103 and the liquid outlet channel 104 penetrate through the L-layer micro flow channel adapter plate 101 and the chip cavity adapter plate 102, and in an embodiment of the present invention, two chip cavities 012 adjacent to each other on the left and right can share one liquid inlet channel 103 or liquid outlet channel 104.
In order to ensure the sealing performance of the chip cavity and further avoid the failure caused by the direct contact between the cooling liquid and the chip, in an embodiment of the present invention, a first sealing ring 011 is further disposed between the L-layer micro flow channel adapter plate 101 and the chip cavity adapter plate 102, and the first sealing ring 011 is disposed at the liquid inlet channel 103 and the liquid outlet channel 104 to prevent the liquid inlet channel 103 and the liquid outlet channel 104 from communicating with the chip cavity 012. In an embodiment of the present invention, the material of the first sealing ring 011 is solder or sealant, i.e. a solder ring or a preformed sealant can be used as the first sealing ring 011.
In an embodiment of the present invention, the material of the micro flow channel interposer 101 and the chip cavity interposer 102 may be a semiconductor material or a ceramic, and in another embodiment of the present invention, a through silicon via TSV and/or a first signal interconnection structure (not shown) may be further formed on the micro flow channel interposer 101 to electrically connect to a chipset, so as to form electrical or signal interconnections between chips of the same type or different types located in different chip cavities, thereby enabling system-level high-density heterogeneous integration and forming a system-level package structure such as a radio frequency system, a high-performance computing system, and the like.
As shown in fig. 1, the N chip sets are respectively disposed in the N chip cavities of the double-sided heat dissipation structure. As shown above, the types of the chipsets in different chip cavities may be the same or different, and further, the number of the chipsets in different chip cavities may be the same or different. For example, only a single chip may be disposed in one chip cavity, and if only a single chip is disposed, the chip needs to be flip-chip bonded, that is, the front surface of the chip faces downward, so that the bonding pad of the chip is electrically connected to the through-silicon via of the lower micro flow channel interposer and/or the first signal interconnection structure, and meanwhile, the back surface of the chip may be further disposed with a thermal interface material TIM 021 for better heat dissipation. A plurality of 3D stacked chips can be arranged in one chip cavity, the 3D stacked chips can be manufactured in a flip chip bonding mode and an underfill mode, or in a mode that a non-conductive film NCF or a non-conductive paste NCP is matched with the flip chip bonding mode, or in a copper-dielectric layer mixed bonding mode. In addition, if 3D stacking is implemented by using wire bonding, the lower chips may be wire bonded, but the upper chip may be flip-chip bonded. Similarly, a TIM 021, a thermal interface material, may also be disposed between the top of the 3D stacked chip and the upper micro flow channel interposer. In one embodiment of the present invention, the thermal interface material TIM is a conventional TIM such as silicone grease. In another embodiment of the present invention, a metal solder is used as the thermal interface material TIM.
As shown in fig. 1, the package structure further includes a substrate 003 and a housing 004. The base plate 003 set up in the below of two-sided heat radiation structure 001, be provided with inlet 031 and liquid outlet 032 on the base plate, it corresponds to inlet channel 103 and liquid outlet 104, through further set up structures (not shown in the figure) such as outside micropump, heat exchanger and pipeline on inlet 031 and liquid outlet 032, can with the miniflow channel keysets constitutes a compact closed circulation system together, realizes packaging structure's liquid heat dissipation. In addition, a second signal interconnection structure (not shown in the figure) may be further disposed on the substrate 003, and meanwhile, an external solder ball BGA or a micro bump may be disposed on the micro channel interposer at the bottom layer, and the micro channel interposer at the bottom layer is electrically or signal connected to the second signal interconnection structure through the external solder ball BGA or the micro bump. Similarly, in order to avoid the cooling liquid from contacting the circuit structures of the micro flow channel adapter plate and the substrate, in an embodiment of the present invention, a second sealing ring 033 is disposed between the bottom micro flow channel adapter plate and the substrate 003, and the second sealing ring 033 is disposed at the liquid inlet 031 and the liquid outlet 032. The material of the second sealing ring 033 may be solder or sealant, i.e., a solder ring or a preformed sealant may be used as the second sealing ring 033.
In an embodiment of the invention, the bottommost chip cavity may also be composed of an upper micro channel adapter plate, a chip cavity adapter plate and a substrate, i.e. the bottommost micro channel adapter plate may be omitted. In this embodiment, the bottommost die cavity interposer and chipset are disposed directly on the substrate.
As shown in fig. 1, the housing 004 is disposed on the substrate 003 and covers the double-sided heat dissipation structure 001. In an embodiment of the present invention, the housing may be made of a material with electromagnetic compatibility EMC, or may be directly made of a metal housing, so as to ensure the electromagnetic compatibility of the whole package structure.
Fig. 2 illustrates a flow diagram for forming a package structure with a double-sided heat dissipation structure according to an embodiment of the invention. As shown in fig. 2, a method for manufacturing a package structure with a double-sided heat dissipation structure includes:
first, at step 201, an interposer is formed. Including forming a microchannel adapter plate and a chip cavity adapter plate. The micro-channel adapter plate can be realized in a copper-dielectric layer mixed bonding mode, and can also be realized in a solder hot-pressing bonding mode. In one embodiment of the present invention, the forming of the micro flow channel adaptor plate comprises:
covering a first surface of a first passive device and a second passive device, such as a semiconductor material or a ceramic adapter plate, with an insulating material, and preparing a TSV structure;
filling metal in the TSV structures of the first passive device and the second passive device for signal interconnection, and forming a plurality of communicated groove structures; and
and the first surface of the first passive device and the first surface of the second passive device are subjected to copper-dielectric layer hybrid bonding or solder hot-pressing bonding, so that the TSV structure of the first passive device is electrically connected with the TSV structure of the second passive device, and meanwhile, the groove structure of the first passive device and the groove structure of the second passive device surround to form a micro-channel.
In yet another embodiment of the present invention, a redistribution layer may be further formed on the second surface of the first and/or second passive structure, and electrically connected to the TSV structure as the first signal interconnection structure, and performing ball-planting or forming a micro bump as required.
It should be understood that in other embodiments of the present invention, other processes commonly used in the art may be used to form the micro flow channel adapter plate;
the chip cavity adapter plate is obtained by forming through holes with specified sizes at specified positions of passive devices, such as a semiconductor material or a ceramic adapter plate;
next, at step 202, a chipset is formed. The method mainly comprises the step of forming a 3D stacked chip, wherein the 3D stacked chip can be manufactured in a flip-chip bonding and bottom filling manner, or in a manner that a non-conductive film NCF or a non-conductive paste NCP is matched with the flip-chip bonding manner, or in a manner that a copper-dielectric layer is mixed and bonded. In addition, if the 3D stacking is implemented by using wire bonding, the chips on the lower layers may be wire bonded, but the chip on the upper layer needs to be flip-chip bonded;
next, in step 203, a double-sided heat dissipation structure is formed. Pile up from top to bottom microchannel keysets, chip chamber keysets and chipset. In the embodiment of the invention, the double-sided heat dissipation structure can be formed by adopting a single package body mode or a wafer-level bonding mode. In the process, because a multilayer structure may be provided, multiple times of bonding are usually required, and in order to avoid that the bonding surface of the previous time is not melted in the bonding process of the next time, solders with different melting points can be adopted for respectively bonding. However, if in-situ reflow bonding is used, solders with different melting points may not be used. If wafer-level bonding is adopted, the integration of a micro-channel adapter plate wafer and a chip cavity adapter plate wafer is realized by using a wafer-level bonding mode, then the integration of a chip set, the micro-channel adapter plate wafer and the chip cavity adapter plate wafer is realized by using a chip-to-wafer mode, then the integrated chip set, the micro-channel adapter plate and the chip cavity adapter plate wafer are stacked, the integration of a plurality of layers of wafers is realized, and finally scribing is carried out, wherein in the wafer-level bonding process, solders with different melting points can not be used; and
finally, at step 204, the substrates are bonded and the housing is formed.
The invention provides a packaging structure with a double-sided heat dissipation structure and a manufacturing method thereof. Simultaneously in order to satisfy the requirement of thermal management, all adopted two-sided radiating mode on every chip chamber, promptly the upper and lower both sides in chip chamber all are provided with the miniflow channel module, and then make high power density single-chip or 3D pile up the miniflow channel module effluvium of heat accessible upper and lower face that the chip produced. By the packaging structure, system-level high-density heterogeneous integration of a high-power-density chip, such as a radio frequency system, a high-performance computing system and the like, can be realized, and 3D integration with more layers can be realized under the condition of meeting the requirement of thermal management.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (11)
1. A package structure with a double-sided heat dissipation structure, comprising:
the double-sided heat dissipation structure comprises N chip cavities, and heat dissipation modules are arranged on the upper side and the lower side of each chip cavity; and
n chipsets are respectively arranged in the N chip cavities, wherein the N chipsets can be electrically connected through the double-sided heat dissipation structure.
2. The package structure of claim 1, wherein the double-sided heat dissipation structure comprises:
an L-layer micro-channel adapter plate;
the chip cavity adapter plate is arranged between the two adjacent layers of micro-channel adapter plates, at least one through hole is arranged on the chip cavity adapter plate, and the through hole and the two adjacent layers of micro-channel adapter plates form a closed chip cavity together; and
and the liquid inlet channel and the liquid outlet channel penetrate through the L-layer micro-channel adapter plate and the chip cavity adapter plate and are communicated with micro-channels on the micro-channel adapter plate.
3. The package structure of claim 2, wherein a first sealing ring is disposed between the micro flow channel adapter plate and the chip cavity adapter plate, and the first sealing ring is disposed at the liquid inlet channel and the liquid outlet channel.
4. The package structure of claim 3, wherein the first seal ring is a solder or a sealant.
5. The package structure of claim 2, wherein the micro flow channel interposer has through-silicon vias and/or first signal interconnect structures disposed thereon for electrical connection with the chipset.
6. The package structure of claim 2, wherein the micro flow channel interposer and the chip cavity interposer are made of semiconductor material or ceramic.
7. The package structure of claim 2, further comprising:
the base plate, set up in double-sided heat radiation structure's bottom, and with be provided with the second sealing ring between the miniflow way keysets of bottom, the base plate includes:
the liquid inlet and the liquid outlet respectively correspond to the liquid inlet channel and the liquid outlet channel, and the second sealing rings are arranged at the liquid inlet and the liquid outlet; and
the second signal interconnection structure is electrically connected with the micro-channel adapter plate; and
and the shell coats the double-sided heat dissipation structure.
8. The package structure of claim 7, wherein the housing is made of metal or a material with electromagnetic compatibility.
9. The package structure of claim 1, wherein the chipset comprises a single chip or a plurality of stacked chips, wherein:
the single chip is bonded in the chip cavity by adopting a flip chip bonding technology, and a heat conduction interface material is arranged between the back surface of the single chip and the double-sided heat dissipation structure; and
the stacked chips are formed in a flip-chip bonding or wire bonding mode, wherein the chip at the topmost layer is in flip-chip bonding, and a heat conduction interface material is arranged between the back surface of the chip at the topmost layer and the double-sided heat dissipation structure.
10. A manufacturing method of a packaging structure with a double-sided heat dissipation structure is characterized by comprising the following steps:
forming a micro-channel adapter plate and a chip cavity adapter plate;
forming a chipset;
bonding the micro-channel adapter plate, the chip cavity adapter plate and the chip set from top to bottom; and
the substrates are bonded and the housing is formed.
11. The method of manufacturing of claim 10 wherein the solder used for each bond has a different melting point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210740051.2A CN115050730A (en) | 2022-06-28 | 2022-06-28 | Packaging structure with double-sided heat dissipation structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210740051.2A CN115050730A (en) | 2022-06-28 | 2022-06-28 | Packaging structure with double-sided heat dissipation structure and manufacturing method thereof |
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| CN115050730A true CN115050730A (en) | 2022-09-13 |
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| CN202210740051.2A Pending CN115050730A (en) | 2022-06-28 | 2022-06-28 | Packaging structure with double-sided heat dissipation structure and manufacturing method thereof |
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