CN213546307U - Partitioned heat dissipation chip packaging structure - Google Patents
Partitioned heat dissipation chip packaging structure Download PDFInfo
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- CN213546307U CN213546307U CN202022310383.6U CN202022310383U CN213546307U CN 213546307 U CN213546307 U CN 213546307U CN 202022310383 U CN202022310383 U CN 202022310383U CN 213546307 U CN213546307 U CN 213546307U
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Abstract
The application provides radiating chip package structure of subregion formula includes: a rewiring layer; the functional chip is arranged on the rewiring layer and is electrically connected with the rewiring layer; at least one power device disposed on the redistribution layer and electrically connected to the redistribution layer; a thermal isolation element on the redistribution layer and disposed between the power device and the functional chip to thermally isolate the power device from the at least one functional chip; and the packaging layer is arranged on the rewiring layer and used for packaging and plastically packaging the functional chip, the heat insulation element and the power device. This application carries out thermal insulation to power device and function chip through setting up the heat insulating block around power device for power device top forms isolated heat source island, conveniently independently dispels the heat to power device, does not influence the working property of functional chip, can improve packaging structure's reliability.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a partitioned heat dissipation chip packaging structure.
Background
With the rapid development of modern electronic information technology, electronic products are gradually developed in the direction of miniaturization, portability and multi-functionalization, so that the existing electronic products are packaged in multiple ways to form a modular structure with high integration level. The modular structure is packaged with circuit elements such as chips with different functions, power devices and the like, wherein the power devices are mainly used for electric energy conversion and control circuits of electric products. In practical application, the heat generated by the power device is far greater than that generated by the chip, and in a modular packaging structure, the heat generated by the power device can be transferred to the chip to influence the working performance of the chip, so that the reliability of the whole packaging structure is poor, and the heat dissipation burden of the packaging structure is increased.
Therefore, the prior art has defects and needs to be improved urgently.
Disclosure of Invention
An object of the embodiment of the present application is to provide a partitioned heat dissipation chip package structure, which solves the problem that a large amount of heat generated by a power device in an existing electronic product can be transferred to a functional chip to affect the working performance of the functional chip, and can improve the reliability of the package structure.
The embodiment of the application provides a partitioned heat dissipation chip packaging structure, which includes:
a rewiring layer;
at least one functional chip disposed on the redistribution layer and electrically connected to the redistribution layer;
at least one power device disposed on the redistribution layer and electrically connected to the redistribution layer;
a thermal isolation element on the redistribution layer and disposed between the power device and the functional chip such that the power device is thermally isolated from at least one of the functional chips;
and the packaging layer is arranged on the rewiring layer and used for packaging and plastically packaging the functional chip, the heat insulation element and the power device.
Preferably, in the chip package structure with partitioned heat dissipation according to the embodiment of the present application, the heat insulation element is disposed on each side of the power device adjacent to the functional chip.
Preferably, in the chip package structure with partitioned heat dissipation according to the embodiment of the present application, the heat insulation element is disposed between the power device and the functional chip in a continuous and uninterrupted manner.
Preferably, in the chip packaging structure with partitioned heat dissipation according to the embodiment of the present application, the thermal conductivity of the thermal insulation element is less than 0.1W/(m × K).
Preferably, in the chip packaging structure with partitioned heat dissipation according to the embodiment of the present application, the width of the heat insulating element is 20 to 1000 μm.
Preferably, in the chip package structure with partitioned heat dissipation according to the embodiment of the present application, the heat insulation element may be silicon-based, carbon-based, or titanium-based aerogel, foamed alumina, a metal tube covered with an oxide dielectric layer, or a micro channel in which a liquid flow loop is formed.
Preferably, in the chip packaging structure with partitioned heat dissipation of the embodiment of the present application, the chip packaging structure further includes a heat dissipation element, where the heat dissipation element is disposed on the package layer and correspondingly disposed above the power device.
Preferably, in the chip package structure with partitioned heat dissipation according to the embodiment of the present application, the heat dissipation element is composed of a heat conduction interface material layer and a heat sink which are stacked in sequence from bottom to top.
Preferably, in the chip packaging structure with partitioned heat dissipation of the embodiment of the present application, the heat conducting interface material layer may be one of heat conducting silicone grease, a heat conducting silicone sheet, a heat conducting phase change material, or a heat conducting double-sided adhesive tape, and the heat sink is one or a combination of two or more of a metal plate, a graphite film, a graphene film, a heat pipe, or a vapor chamber plate containing heat dissipation fins.
Preferably, in the chip package structure with partitioned heat dissipation according to the embodiment of the present application, an underfill layer is disposed between the upper surface of the redistribution layer and the functional chip, the power device, and the heat insulation element.
The partitioned heat dissipation chip packaging structure provided by the embodiment of the application carries out heat isolation on the power device and the functional chip by arranging the heat insulation blocks around the power device, so that an isolated heat source island is formed above the power device, the power device is conveniently and independently cooled, the working performance of the functional chip is not influenced, and the reliability of the packaging structure can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a chip package structure with partitioned heat dissipation in embodiment 1 of the present application.
Fig. 2 is a schematic structural diagram of a chip package structure with partitioned heat dissipation in embodiment 2 of the present application.
Fig. 3-7 are schematic cross-sectional views of various arrangements of thermal isolation elements of the partitioned heat dissipation chip fan-out package in the embodiments of the present application.
Fig. 8-14 are detailed diagrams of steps of a packaging method for manufacturing the partitioned heat dissipation chip package structure in embodiment 1 of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that the terms "upper surface", "lower surface", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip package structure with partitioned heat dissipation according to embodiment 1 of the present application. Among this subregion formula radiating chip package structure, include:
a rewiring layer 10;
at least one functional chip 20, the functional chip 20 is disposed on the redistribution layer 10 and electrically connected to the redistribution layer 10;
at least one power device 30, the power device 30 being disposed on the rewiring layer 10 and electrically connected to the rewiring layer 10;
a heat insulating element 40, the heat insulating element 40 being located on the redistribution layer 10 and disposed between the power device 30 and the functional chip 20, so that the power device 30 is thermally isolated from the at least one functional chip 20;
and the packaging layer 50 is arranged on the redistribution layer 10, and encapsulates the functional chip 20, the heat insulation element 40 and the power device 30.
Please refer to fig. 3-7, and fig. 3-7 are schematic cross-sectional views of various arrangements of the heat insulating element of the chip fan-out package with partitioned heat dissipation in the embodiment of the present application. In practical applications, the heat insulation element 40 may be disposed between the power device 30 and the functional chip 20 in a continuous uninterrupted manner or in an equally spaced manner. Preferably, as shown in fig. 3 to 6, the heat insulation element 40 is continuously and uninterruptedly disposed between the power device 30 and the functional chip 20, so as to completely separate the power device 30 from the functional chip 20, thereby achieving better heat insulation effect.
Furthermore, as shown in fig. 6, the thermal insulation element 40 may be used to isolate the power device 30 from only a portion of the adjacent functional chips 20; the heat insulation element 40 may be disposed between the power device 30 and each functional chip 20 adjacent to the power device 30, as shown in fig. 3, that is, disposed at each side of the power device 30 adjacent to the functional chip 20, or even may surround the power device 30 in a continuous and uninterrupted manner except for the contact surface connected to the redistribution layer 10, as shown in fig. 4 and 5, so as to form an isolated heat source island for the power device 30, and further, only by performing heat dissipation on the power device 30, most of heat of the whole package structure may be dissipated, and the heat dissipation burden of the package structure is reduced.
In practical applications, as shown in fig. 3 to 7, the heat insulation element 40 may be disposed around the power device 30 in a shape of a circular ring, a square ring, or a U shape, and the like, depending on the position of the power device 30 on the package structure, which is not limited herein.
It should be further noted that in the chip package structure with partitioned heat dissipation of embodiment 1 of the present application, the thermal conductivity of the thermal insulating element 40 is less than 0.1W/(m × K), which has a good thermal insulating effect and can insulate heat generated by the power device 30. And the width of the heat insulation element 40 is 20-1000 μm.
In practical applications, the insulating element 40 may be silicon-based, carbon-based or titanium-based aerogel, foamed alumina, metal tubing covered with an oxide dielectric layer, or a microchannel in which a liquid flow circuit is formed. As shown in fig. 7, the heat insulation element 40 is a micro channel forming a liquid flow loop, and therefore, the side surface of the package structure is provided with a liquid inlet and a liquid outlet, which are connected with an external circulation liquid cooling device, so that not only is the heat insulation effect achieved, but also the heat of the power device 30 can be directly taken away, and the heat insulation and heat dissipation effects are excellent.
Further, the chip package structure with partitioned heat dissipation of embodiment 1 of the present application further includes a heat dissipation element 60, where the heat dissipation element 60 is disposed on the package layer 50 and correspondingly disposed above the power device 30.
In practical applications, the heat dissipation element 60 may be composed of only one heat conduction interface material layer 61, and preferably, the heat dissipation element 60 may be composed of the heat conduction interface material layer 61 and the heat sink 62 which are stacked in sequence from bottom to top. The thermal interface material layer 61 is used to conduct heat generated by the power device 30 to the heat sink 62, and then rapidly dissipate heat generated by the power device 12 through the heat sink 62. The heat insulation element 40 is arranged around the power device 30 in embodiment 1 of the present application, and the heat insulation element 40 isolates the power device from other devices, and then, in combination with the heat dissipation element above the power device 30, an independent heat source island is formed, which can perform active heat dissipation, so that the heat of the power device 30 is not conducted to other devices (such as a functional chip or other power devices), so as to improve the working efficiency of the package structure, and meanwhile, only the power device 30 with large heat generation amount is subjected to partitioned isolated heat dissipation, which can also reduce the heat dissipation cost.
Specifically, in practical application, the heat conducting interface material layer 61 may be one of heat conducting silicone grease, a heat conducting silicone sheet, a heat conducting phase change material, or a heat conducting double-sided adhesive tape, and the heat sink 62 is one or a combination of two or more of a metal plate containing heat dissipating fins, a graphite film, a graphene film, a heat pipe, or a vapor chamber. For example, a heat pipe or a vapor chamber may be disposed on the heat conducting interface material layer 61, and a graphite film or a graphene film may be disposed on the heat pipe or the vapor chamber, so that heat generated by the power device 30 is first transferred to the heat pipe or the vapor chamber through the heat conducting interface material layer 61, then transferred to the graphite film or the graphene film, and then transferred into the air directly or through a metal plate having heat dissipation fins, thereby forming an efficient heat dissipation system.
Further, in the chip package structure with partitioned heat dissipation according to embodiment 1 of the present application, the redistribution layer 10 includes:
the dielectric material layer 11, the functional chip 20, the power device 30 and the heat insulation element 40 are arranged on the upper surface of the dielectric material layer 11, the dielectric material layer 11 is provided with a plurality of first through holes, and one first through hole is opposite to one input/output port of the functional chip 20 or one input/output port of the power device 30;
the metal circuit layer 12 is disposed on the lower surface of the dielectric material layer 11, and the metal circuit layer 12 is filled in the first through hole.
The dielectric material layer 11 is made of materials such as ABF (Ajinomoto Build-up Film) or PP (Polypropylene), and is attached to the functional chip 20 and the power device 30 on the side having the input/output port, so as to play an insulating role, and form an integrated circuit together with the metal circuit layer 12.
Wherein, the first through hole on the dielectric material layer 11 can be obtained by laser drilling, and forms a window for exposing the bumps (i.e. input/output ports) of the functional chip 20 and the power device 30; specifically, the dielectric material layer is drilled by UV laser, so that the bumps of the functional chip 20 and the power device 30 are exposed, and the subsequent electrical extraction of the functional chip 20 and the power device 30 is facilitated.
It should be noted that, in order to form the Chip package structure with partitioned heat dissipation in embodiment 1 of the present application, in practical applications, the package manners of the functional Chip 20 and the power device 30 may be implemented by Ball Grid Array (Flip Chip Ball Grid Array, abbreviated as FC-BGA), quad flat non-leaded package (QFN), fan-out wafer level Chip package (FOWLP), or board level fan-out Chip package (FOPLP).
Further, in the chip package structure with partitioned heat dissipation according to embodiment 1 of the present application, the method further includes:
solder resist ink 71, wherein the solder resist ink 71 is arranged on the metal circuit layer 12, and the solder resist ink 71 is provided with a plurality of second through holes;
and the solder balls 72, wherein the solder balls 72 are arranged at the second through holes and are electrically connected with the metal circuit layer 12.
The solder resist ink 71 is formed by coating a photosensitive ink, and performing exposure, development, curing treatment, and surface treatment. The pad area of the redistribution layer 10 is exposed out of the solder resist ink 71, and then the solder balls 72 are implanted into the pad area, so that the functional chip 20 and the power device 30 can be electrically led out.
It should be further noted that the functional chip 20 in embodiment 1 of the present application may be a digital chip, a passive component, a power management chip, or the like, the power device 30 may be a power driving chip, a switch control chip, or the like, and the number and the type of the functional chip 20 and the power device 30 may be set according to a pre-designed circuit with a modular structure, and the number and the type of the functional chip 20 and the power device 30 are not limited herein.
Further, referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package structure with a partitioned heat dissipation structure in embodiment 2 of the present application. The partitioned heat dissipation chip package structure is formed by FC-BGA packaging process, in which an underfill layer 80 is disposed between the upper surface of the dielectric material layer 11 and the functional chip 20, the power device 30 and the heat insulation element 40. The underfill layer 80 is used to encapsulate the gaps between the bumps (i.e., input/output ports) of the functional chip 20 and the power device 30 and the dielectric material layer 11, so as to ensure the sealing performance of the package structure and improve the reliability of the package structure. In practical applications, the underfill layer 80 can be formed by performing underfill in the package structure of embodiment 2 of the present application through a non-contact dispensing technique. In addition, in embodiment 2 of the present application, the package is manufactured by using the FC-BGA process, which not only provides excellent electrical performance, but also reduces the loss and inductance between chip interconnections, reduces the problem of electromagnetic interference, and bears higher frequency, thereby making it possible to break through the over-frequency limit, and improving the density of the input/output ports.
Referring to fig. 8 to 14, the chip package structure with partitioned heat dissipation in embodiment 1 of the present application can be manufactured by a fan-out chip package process, which specifically includes the following steps:
A. respectively arranging at least one functional chip 20 and at least one power device 30 at preset positions of the carrier plate 1, and arranging heat insulation elements 40 around the power devices 30;
B. arranging an encapsulation layer 50 on the carrier 1, wherein the encapsulation layer 50 wraps the functional chip 20, the power device 30 and the heat insulation element 40 to form a preliminary encapsulation structure;
C. removing the carrier plate 1 from the primary packaging structure, and arranging a rewiring layer 10 on the front surface of the primary packaging structure, wherein the rewiring layer 10 is electrically connected with the functional chip 20 and the output/input port of the power device 30;
D. a heat dissipation element 60 is disposed on the reverse side of the preliminary package structure, and the heat dissipation element 60 is disposed at a position of the preliminary package structure corresponding to the power device 30.
Referring to fig. 8, the step a specifically includes: a bonding glue layer 2 is arranged on the carrier plate 1; bonding the functional chip 20 and the power device 30 to a preset position of the carrier plate 1 through the bonding glue layer 2; and the heat insulating element 40 is disposed around the power device 30 by the bond paste layer 2.
The functional chip 20 and the power device 30 may be fixed on the bonding adhesive layer 2 in a face up or face down mounting manner, that is, the input/output ports of the functional chip 20 and the power device 30 may be contact surfaces of the bonding adhesive layer 2, or may be opposite surfaces of the contact surfaces of the bonding adhesive layer 2, but the input/output ports of the functional chip 20 and the input/output ports of the power device 30 need to be on the same side. In practical applications, if the thicknesses of the functional chip 20 and the power device 30 are not the same, the functional chip can be mounted only by face down mounting. In practical applications, the bonding glue layer 2 may be a common bonding glue, such as a blue film or other adhesive glue. The carrier board 1 may be a glass carrier board, an organic carrier board, a stainless steel carrier board, an alloy carrier board, an FR2 carrier board, an FR4 carrier board, an FR5 carrier board or a BT resin carrier board.
Further, the distribution of the functional chips 20 and the power devices 30 on the bonding paste layer 2 may be set according to a pre-designed circuit.
Referring to fig. 9, the encapsulating layer 50 may be an encapsulating epoxy resin, such as a bisphenol a type epoxy resin, a brominated epoxy resin, a novolac type epoxy resin, a bisphenol F type epoxy resin, a hydrogenated bisphenol a type epoxy resin, a glycidyl amine type epoxy resin, a hydantoin type epoxy resin, an alicyclic epoxy resin, a trishydroxyphenylmethane type epoxy resin, a bis-or bisphenol type epoxy resin, or a mixture thereof, a bisphenol S type epoxy resin, a bisphenol a novolac type epoxy resin, a tetraphenylphenol alcohol (phenylylol) ethane type epoxy resin, a heterocyclic epoxy resin, a diglycidyl benzoate resin, a tetraglycidyl dimethylol ethane resin, an epoxy resin containing a naphthyl group, an epoxy resin containing a nitrogen group, an epoxy resin having a dicyclopentadiene skeleton, a glycidyl methacrylate copolymerized epoxy resin, Epoxy resins obtained by copolymerizing cyclohexylmaleimide with glycidyl methacrylate, CTBN-modified epoxy resins, and the like. Of course, these epoxy resins may be used alone or in combination of 2 or more.
It should be noted that, in step a, if the functional chip 20 and the power device 30 are both adhered to the bonding adhesive layer 2 in a face down mounting manner, the package layer 50 corresponding to the back surfaces (i.e., the surfaces opposite to the surfaces where the input/output ports are exposed) of the functional chip 20 and the power device 30 may not be thinned, but preferably, the package layer 50 corresponding to the back surfaces of the functional chip 20 and the power device 30 may also be thinned, that is, as shown in fig. 9, so that the back surfaces of the functional chip 20 and the power device 30 are exposed, and the heat dissipation effect of the heat dissipation element may be improved. However, in the step a, if the functional chip 20 and the power device 30 are both adhered to the bonding adhesive layer 2 in a face up mounting manner, the package layer 50 corresponding to the front surfaces (i.e. the surfaces exposing the input/output ports) of the functional chip 20 and the power device 30 needs to be thinned to expose the input/output ports of the functional chip 20 and the power device 30, so as to facilitate subsequent processing.
Referring to fig. 10 to 12, specifically, step C includes: removing the bonding glue layer 2 from the preliminary packaging structure to unload the carrier plate 1; forming a dielectric material layer 12 on the front surface of the preliminary packaging structure, wherein the front surface of the preliminary packaging structure is a surface exposing the functional chip 20 and the output/input port of the power device 30; punching the positions of the dielectric material layer 12 corresponding to the output/input ports of the functional chip 20 and the power device 30; a metal circuit layer 11 is disposed on the dielectric material layer 12, and the metal circuit layer 11 is electrically connected to the output/input port of the functional chip 20 and the power device 30 through the via hole.
It should be noted that the bonding glue layer 2 can be removed by thermal disassembly, mechanical disassembly or laser disassembly to disassemble the carrier plate 1.
Further, referring to fig. 13 and fig. 14, after step C, the method further includes the following steps:
coating solder resist ink 71 on the metal circuit layer 11, and punching the solder resist ink 71;
Referring to fig. 1, in step D, the thermal interface material layer 61 and the heat spreader 62 are sequentially stacked on the package layer 50, so as to obtain the chip package structure with partitioned heat dissipation of embodiment 1 of the present application.
According to the partitioned heat dissipation chip packaging structure provided by the embodiment of the application, the power device and the functional chip are thermally isolated, so that an isolated heat source island is formed above the power device, the power device is conveniently and independently cooled, the working performance of the functional chip is not influenced, the reliability of the packaging structure can be improved, and the heat dissipation cost is also reduced; and meanwhile, the heat dissipation element is arranged on the packaging layer above the power device, so that heat generated by the power device can be quickly dissipated, and efficient heat dissipation is realized.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A partitioned heat dissipation chip packaging structure is characterized by comprising:
a rewiring layer;
at least one functional chip disposed on the redistribution layer and electrically connected to the redistribution layer;
at least one power device disposed on the redistribution layer and electrically connected to the redistribution layer;
a thermal isolation element on the redistribution layer and disposed between the power device and the functional chip such that the power device is thermally isolated from at least one of the functional chips;
and the packaging layer is arranged on the rewiring layer and used for packaging and plastically packaging the functional chip, the heat insulation element and the power device.
2. The package structure of claim 1, wherein the thermal isolation element is disposed on each side of the power device adjacent to the functional chip.
3. The partitioned heat dissipation chip package structure according to claim 1 or 2, wherein the thermal insulation element is disposed between the power device and the functional chip in a continuous and uninterrupted manner.
4. The partitioned heat dissipating chip package structure of claim 1, wherein the thermal conductivity of the thermal insulating element is less than 0.1W/(m × K).
5. The chip package structure with partitioned heat dissipation according to claim 1, wherein the width of the heat insulating element is 20-1000 μm.
6. The chip package structure with partitioned heat dissipation according to claim 1, wherein the heat insulation element is silicon-based, carbon-based or titanium-based aerogel, foamed alumina, metal tube covered with oxide dielectric layer, or micro channel forming liquid flow loop.
7. The package structure of claim 1, further comprising a heat dissipation element disposed on the package layer and above the power device.
8. The package structure of claim 7, wherein the heat dissipation element comprises a heat conducting interface material layer and a heat sink stacked in sequence from bottom to top.
9. The chip package structure with partitioned heat dissipation according to claim 8, wherein the thermal interface material layer is one of thermal silicone grease, thermal silicone sheet, thermal phase change material, or double-sided thermal adhesive tape, and the heat spreader is one or a combination of two or more of a metal plate with heat dissipation fins, a graphite film, a graphene film, a heat pipe, or a heat spreader.
10. The chip package structure with partitioned heat dissipation according to claim 1, wherein an underfill layer is disposed between the redistribution layer upper surface and the functional chip, the power device and the thermal isolation element.
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| CN202022310383.6U CN213546307U (en) | 2020-10-16 | 2020-10-16 | Partitioned heat dissipation chip packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115084063A (en) * | 2022-07-22 | 2022-09-20 | 深圳市诚芯微科技股份有限公司 | Heat radiation fan-out type power chip packaging device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115084063A (en) * | 2022-07-22 | 2022-09-20 | 深圳市诚芯微科技股份有限公司 | Heat radiation fan-out type power chip packaging device |
| CN115084063B (en) * | 2022-07-22 | 2023-02-14 | 深圳市诚芯微科技股份有限公司 | Heat radiation fan-out type power chip packaging device |
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