TWI391084B - Pcb structure having heat-dissipating member - Google Patents

Description

Circuit board structure with heat sink

The present invention relates to a circuit board structure, and more particularly to a circuit board structure having a heat sink.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, in which Ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized by a package. The substrate is used to mount the semiconductor wafer, and a plurality of grid arrays of solder balls are formed on the back surface of the package substrate to have more input/output connections (I/O connections) in the same unit area to meet A highly integrated semiconductor wafer is required and electrically connected to the external electronic device by the solder balls.

In the conventional semiconductor package structure, the semiconductor wafer is adhered to the top surface of the substrate, and the semiconductor wafer is electrically connected to the substrate by wire bonding or flip chip bonding, and the solder ball is implanted on the back surface of the substrate. For the purpose of electrical connection; although the purpose of high number of feet can be achieved, in the case of higher frequency use or high speed operation, the performance of the electrical characteristics due to the long connection path of the wire cannot be improved, and there is a limit, and Because the traditional packaging requires multiple connection interfaces, the manufacturing cost is relatively increased.

In addition, with the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the heat generated by the semiconductor wafer during operation will increase significantly. If the heat generated by the semiconductor wafer is not effectively dissipated, it will be severe. Shorten the performance and longevity of semiconductor wafers.

In order to effectively improve the electrical quality to meet the application of the next generation of products, the industry has studied the use of the embedded in the carrier board for direct electrical connection to shorten the electrical conduction path, and reduce signal loss, signal distortion and upgrade The ability to operate at high speeds.

As shown in Fig. 1, a schematic cross-sectional view of a package structure in which a semiconductor element is buried in a substrate is shown in U.S. Patent No. 5,432,677. As shown in the figure, the package structure includes: a laminate layer 10 having a first surface 10a and a second surface 10b corresponding to the first surface, and the pressure is The opening 10 is formed with at least one opening 100 extending through the first and second surfaces 10a, 10b; the second surface 10b of the bonding layer 10 is bonded to a conductive layer 13 by an adhesive layer 12; A semiconductor wafer 11 is received in the opening 100, and the semiconductor wafer 11 is fixed in the opening 100 by an adhesive layer 12. The semiconductor wafer 11 has an active surface 11a and an inactive surface 11b opposite to the active surface 11a. A plurality of electrode pads 111 are formed on the active surface 11a; a line build-up structure 14 is formed on the first surface 10a of the press layer 10 and the active surface 11a of the semiconductor wafer 11, and the line build-up structure 14 includes An electrical layer 140, a wiring layer 141 stacked on the dielectric layer 140, and a conductive structure 142 formed in the dielectric layer 140, and the conductive structures 142 are electrically connected to the electrode pads of the semiconductor wafer 11. 111; the second surface 10b of the bonding layer 10 and the non-semiconductor wafer 11 Stopper surface 11b of the heat sink 13 bonded to heat the semiconductor wafer 13 by the operation of the heat sink 11 is transferred to the outside.

The wafer embedded package structure can solve various defects of the prior art, but the heat sink 13 must be additionally prepared, which complicates the manufacturing process and increases the manufacturing cost.

In addition, although the inactive surface of the semiconductor wafer embedded in the substrate is completely exposed to facilitate heat dissipation of the semiconductor wafer, a circuit structure is formed only on one surface of the substrate; the US patent shown in FIG. No. 6,586,822, comprising a core 20 having a first surface 20a and an opposite second surface 20b and having an opening extending through the first surface 20a and the second surface 20b. 200; a semiconductor chip (microelectronic die) 21 is received in the opening 200, and the semiconductor wafer 21 has an active surface 21a and an opposite inactive surface 21b; an encapsulation material 22 is filled in the semiconductor a gap between the wafer 21 and the opening 200 to fix the semiconductor wafer 21 in the opening 200; a line build-up structure 23 is formed on the first surface 20a of the core board 20 and the active surface 21a of the semiconductor wafer 21, The circuit build-up structure 23 includes a dielectric layer 230, a circuit layer 231 stacked on the dielectric layer 230, and a conductive structure 232 formed in the dielectric layer 230, and the conductive structures 232 are electrically connected. Connected to the semiconductor 21 of the pad electrode sheet 211.

Although the second surface 20b of the core board 20 and the inactive surface 21b of the semiconductor wafer 21 have no other components, the heat sink can be eliminated to reduce the cost, and the inactive surface 21b of the semiconductor wafer 21 can be exposed. The heat generated during operation directly dissipates heat; however, the second surface 20b of the core board 20 does not form a line structure or is connected to other electronic components, so that the electrical function cannot be improved, and the use of the multi-function circuit design cannot be met.

Therefore, how to provide a circuit board structure in which a semiconductor wafer and a heat sink are embedded at the same time to facilitate heat dissipation of the semiconductor wafer and avoid the above-mentioned various defects of the prior art has become a difficult problem to be overcome in the industry.

In view of the above disadvantages of the prior art, the main object of the present invention is to provide a circuit board structure having a heat dissipating member, which is formed on the surface of the dielectric layer of the inactive surface of the semiconductor wafer and formed with a corresponding semiconductor wafer. The heat absorbing pad of the active surface is used for heat dissipation of the semiconductor wafer.

A further object of the present invention is to provide a circuit board structure having a heat dissipating member, and a circuit structure is formed on both sides of the circuit board to enhance the electrical function of the circuit board structure.

It is still another object of the present invention to provide a circuit board structure having a heat dissipating member, which simplifies the process to reduce cost.

To achieve the above and other objects, the present invention provides a circuit board structure having a heat dissipating member, comprising: a carrier plate having opposite first and second surfaces, and at least one opening extending through the first and second surfaces a first dielectric layer formed on the first surface of the carrier to seal one end of the opening; a semiconductor wafer is disposed in the opening of the carrier, the semiconductor wafer having a relative active surface and a non- An active surface, the active surface having a plurality of electrode pads, and the non-active surface is disposed on the surface of the first dielectric layer; the second dielectric layer is formed on the second surface of the carrier and the active surface of the semiconductor wafer, And filling a gap between the opening of the carrier and the semiconductor wafer; and a first circuit layer formed on the surface of the first dielectric layer, and the first circuit layer has at least one heat absorbing pad, the heat absorbing pad position It is the inactive surface of the semiconductor wafer.

The circuit board structure further comprises a line build-up structure formed on the first dielectric layer, the first circuit layer and the surface of the heat absorbing pad, wherein the line build-up structure has a heat conducting structure connected to the heat absorbing pad, and the line buildup structure The surface includes an electrical connection pad, and the thermally conductive structure is connectable to the electrical connection pad.

Furthermore, the circuit board structure further includes a second circuit layer formed on the surface of the second dielectric layer, the second circuit layer being electrically connected to the semiconductor via a conductive structure formed in the second dielectric layer An electrode pad of the chip, wherein the second circuit layer is electrically connected to the first circuit layer via a plating via formed in the carrier; and the surface of the second dielectric layer and the second circuit layer is formed Another line build-up structure.

The line build-up structure includes a dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, the outer surface of the line build-up structure being covered with a solder resist layer, and A plurality of openings are formed in the solder resist layer to expose an electrical connection pad on the outer surface of the line build-up structure, and a surface of the electrical connection pad in the open-hole of the solder resist layer is formed as a solder ball. A conductive element of a pin (Pin) or LGA (land grid array).

The circuit board structure with a heat dissipating member of the present invention is formed on a second dielectric layer corresponding to the inactive surface of the semiconductor wafer to form a heat absorbing pad for dissipating heat of the semiconductor wafer, so that the heat absorbing pad is spaced apart from the dielectric layer to absorb the The heat generated by the semiconductor wafer is transferred to the external electrical connection pads and the conductive elements via the heat conducting structure in the line build-up structure to dissipate heat; therefore, the present invention performs the line process only on the carrier board and the surface of the semiconductor wafer. The heat absorbing pad and the heat conducting structure are formed together in the process, and the heat dissipation component is not separately prepared, thereby simplifying the process to reduce the cost, and forming a circuit structure on the first and second surfaces of the carrier plate to improve the structure of the circuit board structure. Sexual function.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

As shown in Figs. 3A to 3G, a schematic cross-sectional view showing a method of manufacturing a circuit board structure having a heat dissipating member of the present invention will be described.

As shown in FIG. 3A, first, a carrier board 30 is provided, which is selected from a circuit board, an insulating board or a metal board. The carrier board 30 has a first surface 30a and is opposite to the first surface 30a. The second surface 30b defines at least one opening 300 in the carrier plate 30.

As shown in FIG. 3B, a first dielectric layer 31 is formed on the first surface 30a of the carrier 30 to seal one end of the carrier opening 300.

As shown in FIG. 3C, a semiconductor wafer 32, which is an active wafer or a passive wafer, is disposed in the opening 300. The semiconductor wafer 32 has an active surface 32a and an inactive surface 32b opposite to the active surface 32a. The active surface 32a has a plurality of electrode pads 321 and is attached to the surface of the first dielectric layer 31 by the inactive surface 32b.

As shown in FIG. 3D, a second dielectric layer 33 is formed on the second surface 30b of the carrier 30 and the active surface 32a of the semiconductor wafer 32, and the first and second dielectric layers 31, 33 are filled in In the gap between the opening 300 and the semiconductor wafer 32, the semiconductor wafer 32 is fixed in the opening 300; the first and second dielectric layers 31, 33 are made of FR-4 resin, FR-5 resin. Epoxy, Polyesters, Cyanate ester, Polyimide, Bismuthimide/BT (Bismaleimide triazine) or It is made of insulating material such as epoxy resin glass or glass fiber.

As shown in FIG. 3E, a first circuit layer 34 and a heat absorbing pad 341 are formed on the surface of the first dielectric layer 31. The position of the heat absorbing pad 341 corresponds to the inactive surface 32b of the semiconductor wafer 32. The second circuit layer 35 is formed on the surface of the electrical layer 33, and the second circuit layer 35 is electrically connected to the electrode pad 321 of the semiconductor wafer 32 via the conductive structure 351 formed in the second dielectric layer 33; At least one plated via (PTH) 36 is formed in the board 30 to electrically connect the first and second circuit layers 34, 35 of the first surface 30a and the second surface 30b of the carrier board 30.

The present invention mainly forms a heat absorbing pad 341 for dissipating heat of the semiconductor wafer 32 while forming the first circuit layer 34 on the surface of the first dielectric layer 31. The heat absorbing pad 341 is a copper pad, and the heat absorbing pad 341 is used. The first dielectric layer 31 is spaced apart from the heat generated by the operation of the semiconductor wafer 32, so that the heat dissipating member and the heat dissipating member are not required to be prepared in advance, so as to simplify the process steps without additional thickness of the package structure, and on the carrier board 30 The first and second surfaces 30a, 30b are formed with a line structure of the first and second circuit layers 34, 35 to enhance the electrical function of the circuit board structure.

As shown in FIG. 3F, a line build-up process is performed on the surfaces of the first dielectric layer 31 and the first circuit layer 34 to form a line build-up structure 37. The circuit build-up structure 37 includes a dielectric layer 370, a circuit layer 371 stacked on the dielectric layer 370, and a conductive structure 372 formed in the dielectric layer, and electrically connected through the conductive structure 372. To the first circuit layer 34, a plurality of electrical connection pads 373 are formed on the outer surface of the circuit build-up structure 37.

In addition, a heat conducting structure 374 is formed in the dielectric layer 370, and the heat conducting structure 374 is connected to the heat absorbing pad 341 of the first circuit layer 34 and the electrical connection pad 373 of the circuit layering structure 37. The heat absorbing pad 341, the heat conducting structure 374, and the electrical connection pad 373 form a heat dissipation path.

In addition, a line build-up process is performed on the second dielectric layer 33 and the second circuit layer 35 to form another line build-up structure 37'. The line build-up structure 37' includes a dielectric layer 370', stacked. a circuit layer 371' on the dielectric layer 370' and a conductive structure 372' formed in the dielectric layer, and electrically connected to the second circuit layer 35 via the conductive structure 372', and added to the line The outer surface of the layer structure 37' is formed with a plurality of electrical connection pads 373'.

As shown in FIG. 3G, the outer surfaces of the line build-up structures 37, 37' are respectively covered with a solder resist layer 38, 38', and openings 380, 380' are formed in the solder resist layers 38, 38' to expose the same The connection pads 373, 373' are formed on the electrical connection pads 373, 373' to form a conductive element 39 such as a solder ball, a pin or a land grid array, for storage on the carrier plate 30. The semiconductor wafer 32 is electrically connected to the external electronic components by electrode pads 321 on its surface, the wiring layer 35, the wiring build-up structures 37, 37', and the conductive members 39.

According to the above method, the present invention further provides a circuit board structure having a heat dissipating member, comprising: a carrier plate 30 having a first surface 30a and an opposite second surface 30b, and having at least one through the first and second surfaces The first dielectric layer 31 is formed on the first surface 30a of the carrier 30 to seal one end of the opening 300; at least one semiconductor chip 32 is disposed in the opening 300, the semiconductor wafer The 32 series has an active surface 32a and an opposite non-active surface 32b, and has a plurality of electrode pads 321 on the active surface 32a, and is disposed on the surface of the first dielectric layer 31 by the inactive surface 32b; the second dielectric layer 33, formed on the second surface 30b of the carrier plate 30 and the active surface 32a of the semiconductor wafer 32, and filled in the gap between the opening 300 of the carrier plate 30 and the semiconductor wafer 32; and the first circuit layer 34, The first circuit layer 34 is formed on the first dielectric layer 31, and the first circuit layer 34 has at least one heat absorbing pad 341 corresponding to the inactive surface 32b of the semiconductor wafer 32.

The circuit board structure includes a second dielectric layer 33 and a second circuit layer 35 formed on the second surface 30b of the carrier board 30 and the active surface 32a of the semiconductor wafer 32, and the second circuit layer 35 is formed. The conductive structure 351 in the second dielectric layer 33 is electrically connected to the electrode pad 321 of the semiconductor wafer 32; and the carrier board 30 has at least one plating via (PTH) 36 electrically connected to the first and the third Two circuit layers 34, 35.

The circuit board structure may include a line build-up structure 37 formed on the surface of the first dielectric layer 31 and the first circuit layer 34, and another line build-up structure 37' formed on the second dielectric a layer 33 and a second wiring layer 35; the line build-up structure 37, 37' includes a dielectric layer 370, 370', a wiring layer 371, 371' stacked on the surface of the dielectric layer, and a conductive layer formed in the dielectric layer The structure 372, 372', and the conductive structure 372, 372' is provided for the line build-up structure 37, 37' to electrically connect the first circuit layer 34 and the second circuit layer 35 respectively; and the line build-up structure 37, 37 The outer surface is formed with a plurality of electrical connection pads 373, 373'.

The line build-up structure 37 further includes a heat-conducting structure 374 for connecting the heat-absorbing pad 341 and the electrical connection pad 373, thereby forming a heat dissipation path formed by the heat-absorbing pad 341, the heat-conducting structure 374 and the electrical connection pad 373. .

The outer surface of the line build-up structure 37, 37' is covered with a solder resist layer 38, 38', respectively, and the solder resist layer 38, 38' has a plurality of openings 380, 380' to expose the line build-up structure 37, 37 'Electrical connection pads 373, 373' on the outer surface, forming conductive elements such as solder balls, pins or LGAs on the surface of the electrical connection pads 373, 373' The semiconductor wafer 32 accommodated in the carrier 30 is electrically connected to the external electronic component by the electrode pads 321 , the circuit layer 35 , the line build-up structures 37 , 37 ′ and the conductive elements 39 on the surface thereof.

In summary, the circuit board structure having the heat dissipating component of the present invention is mainly configured to form a heat absorbing pad for dissipating heat on the first dielectric layer of the inactive surface of the semiconductor chip, so that the heat absorbing pad is spaced apart from the first dielectric layer. The electric layer absorbs the heat generated by the semiconductor wafer, and transfers the heat to the heat conduction structure formed on the outer layer of the line build-up structure and the conductive connection layer and the conductive element on the outer surface of the line build-up structure as a heat dissipation path. Cooling. Therefore, the present invention only needs to form the heat absorbing pad and the heat conducting structure together in the line processing process on the surface of the carrier board and the semiconductor wafer, without additionally preparing a heat sink, thereby simplifying the process to reduce the cost; and first in the carrier board And the second surface is formed with a line structure to enhance the electrical function of the circuit board structure.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

10. . . Press layer

10a, 20a, 30a. . . First surface

10b, 20b, 30b. . . Second surface

100, 200, 300. . . Opening

11, 21, 32. . . Semiconductor wafer

111, 211, 321. . . Electrode pad

11a, 21a, 32a. . . Active surface

11b, 21b, 32b. . . Inactive surface

12. . . Adhesive layer

13. . . Heat sink

14, 23, 37, 37’. . . Line buildup structure

140, 230, 370, 370’. . . Dielectric layer

141, 231, 371, 371’. . . Circuit layer

142, 232, 351, 372, 372', 374. . . Conductive structure

20. . . Core board

twenty two. . . Packaging material

30. . . Carrier board

31. . . First dielectric layer

33. . . Second dielectric layer

34. . . First circuit layer

341. . . Heat absorption pad

35. . . Second circuit layer

36. . . Plating via

373, 373’. . . Electrical connection pad

38, 38’. . . Solder mask

380, 380’. . . Opening

39. . . Conductive component

1 is a cross-sectional view of U.S. Patent No. 5,432,677; FIG. 2 is a cross-sectional view of a structure of U.S. Patent No. 6,586,822; and Figs. 3A to 3G are schematic cross-sectional views showing a structure of a circuit board having a heat dissipating member.

30. . . Carrier board

30a. . . First surface

30b. . . Second surface

300. . . Opening

31. . . First dielectric layer

32. . . Semiconductor wafer

321. . . Electrode pad

32a. . . Active surface

32b. . . Inactive surface

33. . . Second dielectric layer

34. . . First circuit layer

341. . . Heat absorption pad

35. . . Second circuit layer

351. . . Conductive structure

36. . . Plating via

Claims (11)

A circuit board structure having a heat dissipating member, comprising: a carrier plate having opposite first and second surfaces, and at least one opening extending through the first and second surfaces; the first dielectric layer is formed on a first surface of the carrier to seal one end of the opening; a semiconductor wafer is disposed in the opening of the carrier, the semiconductor wafer has opposite active and inactive surfaces, and the active surface has a plurality of electrodes a pad is disposed on the surface of the first dielectric layer by the inactive surface; a second dielectric layer is formed on the second surface of the carrier and the active surface of the semiconductor wafer, and fills the opening of the carrier and the semiconductor a gap between the wafers; and a first circuit layer formed on the surface of the first dielectric layer, and the first circuit layer has at least one heat absorbing pad, the heat absorbing pad being equal to or larger than the inactive surface of the semiconductor wafer, The heat absorbing pad is spaced apart from the first dielectric layer and located below the inactive surface of the semiconductor wafer. The circuit board structure having a heat dissipating component according to claim 1, further comprising a line build-up structure formed on the first dielectric layer, the first circuit layer and the surface of the heat absorbing pad, wherein the circuit has a layered structure A heat conducting structure connects the heat absorbing mat. The circuit board structure having a heat dissipating component according to claim 2, wherein the surface of the circuit build-up structure further comprises an electrical connection pad. And the heat conducting structure is connected to the electrical connection pad. The circuit board structure having a heat dissipating member according to claim 1, further comprising a second circuit layer formed on the surface of the second dielectric layer, wherein the second circuit layer is transparently formed on the second dielectric layer The conductive structure in the layer is electrically connected to the electrode pad of the semiconductor chip, and the second circuit layer is electrically connected to the first circuit layer via a plating via formed in the carrier. A circuit board structure having a heat dissipating member according to claim 4, further comprising another line build-up structure formed on the surface of the second dielectric layer and the second circuit layer. The circuit board structure having a heat sink according to claim 2 or 5, wherein the line build-up structure comprises a dielectric layer, a circuit layer stacked on the dielectric layer, and a dielectric layer formed on the dielectric layer Conductive structure in the layer. The circuit board structure of claim 6, wherein the outer surface of the circuit build-up structure is formed with an electrical connection pad, and a solder resist layer is formed, and the plurality of openings are formed in the solder resist layer. An electrical connection pad exposing the outer surface of the line build-up structure. The circuit board structure having the heat dissipating component according to claim 7 of the patent application, further comprising a conductive component formed on the surface of the electrical connection pad in the opening of the solder resist layer. A circuit board structure having a heat sink according to claim 8 , wherein the conductive element is one of a solder ball, a pin, and an LGA. The circuit board structure having a heat sink according to claim 1, wherein the carrier board is one of an insulating board, a metal board, and a circuit board having a line. A circuit board structure having a heat sink according to claim 1, wherein the semiconductor chip is one of an active chip and a passive chip.