200830975 . « 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路板結構，尤指一種具有散熱 件之電路板結構。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其中球 柵陣列式（Ball grid array, BGA)係為一種先進的半導體封 _裝技術，其特點在於採用一封裝基板來安置半導體晶片， 並於該封裝基板背面形成複數柵狀陣列排列之錫球 (Solder ball)，以於相同單位面積中可具有更多輸入/輸出 連接端（I/O connection)，以符合高度集積化（Integration)之 半導體晶片所需，並藉由該些錫球以電性連接至外部之電 子裝置。 惟傳統半導體封裝結構是將半導體晶片黏貼於基板 頂面，且該半導體晶片係以打線接合（wire bonding)或覆晶 接合（Flip chip)電性連接該基板，再於基板之背面植以錫球 以進行電性連接；雖可達到高腳數的目的，但是在更高頻 使用時或高速操作時，其將因導線連接路徑過長而產生電 氣特性之效能無法提昇，而有所限制，另外，因傳統封裝 需要多次的連接介面，相對地增加生產製造成本。 此外，隨著電子產業的蓬勃發展，電子產品亦逐漸邁 入多功能、高性能的研發方向。為滿足半導體封裝件高積 集度（Integration)以及微型化（Miniaturization)的封裝 5 19829 200830975 - . 需求’半導體晶片於運作時所產生之熱量將明顯增加，如 不及時將半導體晶片產生之熱量有效逸散，將嚴重縮短半 導體晶片之性能及壽命。 為能有效地提昇電性品質以符合下世代產品之應 用，業界紛紛研究採用將晶片埋入承載板内，作直接的電 性連，以縮短電性傳導路徑，並減少訊號損失、訊號失真 及提昇在高速操作之能力。 如第1圖所示，係為美國專利第5,432,677號所示之 •將半$組it件埋人基板之封裝結構之剖面示意圖。如圖所 不，該封裝結構係包括：一壓合層（laminatelayer)1〇，該 壓合層10係具有一第一表面10a及與該第一表面對應之第 一表面10b’且於該壓合層1〇中形成有至少一貫穿該第一 及第二表面10a，10b之開口 100;於該壓合層1〇之第二表 面10b以一黏著層12結合一散熱件（c〇nductivelayer)13; 於該開口 100中容置有一半導體晶片n，且該半導體晶片 _ 11係以黏著層12固定於該開口1〇〇中，又該半導體晶片 Π具有一主動面11a及與該主動面Ua相對之非主動面 11b，且於該主動面lla形成有複數電極墊m •，於該壓合 層10之第一表面10a及半導體晶片1丨之主動面lla形成 有一線路增層結構14，該線路增層結構14係包括介電層 140、疊置於該介電層140上之線路層141，以及形成於該 介電層140中之導電結構142，且該些導電結構丨42係電 性連接至該半導體晶片11之電極塾111 ;該壓合層之 第二表面10b及半導體晶片11之非主動面ub結合有該散 19829 6 200830975 » 搴 熱件y以藉由該散熱件13將半導體晶片n運作時產生 的熱量傳遞至外界。 ^片甘入埋式封裝結構雖可解決習知技術之種種缺 失，惟必而領外製備該散熱件13，致使製程步驟繁雜，而 增加製造成本。 ， 5 f界雖有&用於嵌埋於基板中之半導體晶片之非 主動面完全露出，以利於該半導體晶片散熱，而僅於基板 表7成有線路結構；如第2圖所示之美國專利第 ⑩’ ’ 7虎係包括一核芯板（core>20，該核芯板20且有 :第一表面20a及相對之第二表面2〇b，且具有一貫穿該 第表面20a及第二表面20b之開口 200 ; —半導體晶片 (miCr〇eleCtr〇nicdie)21係容置於該開口 200中，而該半導 體晶片21具有一主動面2U及相對之非主動面封裝 材料（encapWation material)22係填入於該半導體晶片2] 與開口 200之間隙中，以將該半導體晶片21固定於該開口 參200中；線路增層結構23係形成於該核芯板2〇之第一表 面20a及该+導體晶片21之主動面2U，該線路增層結構 23係包括介電層230、疊置於該介電層23〇上之線路層 231，以及形成於該介電層23〇中之導電結構232，且該些 導電結構232係電性連接至該半導體晶片以之電極墊 211 〇 雖該核芯板20之第二表面2〇b及半導體晶片21之非 主動面21b並無其它構件，可免除結合散熱件以降低成 本，並可使邊半導體晶片21之非主動面21b外露，以於運 19829 7 200830975 • 参 作時產生的熱量直接進行散熱；但該核芯板20之第二声 面20b亚無形成線路結構或接置其它 ^ 功能無法提昇’而無法滿足多功能電路設計:使= 因此，如何提出一種同時嵌埋右 熱件之電路板結構，以利於半導體晶^=片及具有散 上述*知技術之種種缺失，實 免 難題。 “成爲目則業界亟待克服之 【發明内容】 _ 鑒於上述習知技術之缺點 供一種且右每以 點本發明之主要目的在於提 (、種具有散熱件之電路板結構，得於半導體 面的介電層表面形成線路之同時古 M a u . ^ J ^亚形成有相對應該半導 曰本發:=的吸熱墊’俾供該半導體晶片散熱用。 板結槿X、'，目的在於提供一種具有散熱件之電路 “口 ’亚於電路板之兩側均形成有線路 板結構之電性功能。 傅啲叔升電路 本發明之再-目的在於提供—種具有散熱件之 板結構，得簡化製程以降低成本。 ％ 為達上述及其他目的，本發明提供—種 ί路S':包括:承载板’係具有相對:第IS面及 ::;面，與至少一貫穿該第-及第二表面之開口；第一 :電：：：形成於該承載板之第-表面以封住該開口：一 曰，+¥體晶片，係容置於該承載板之開口中， 曰曰片係具有相對之主動面及非主動面，且該主動面且有― 數電極墊，並以該非主動面接置於該第—介電層表面^ 19829 200830975 瘳 二介電層，係形成於該承载板 主動面，並填入該承載板之開口 之 中’以及第—線路層’係形成於該 ：的間隙 弟一線路層具有至少一明刼豳 ,电層表面，且該 導體晶片之非主動面。一’該吸熱墊饭置係對應該年 =板料復包括有'線路增層結構 層及吸熱塾表面，該線路增層‘ 包括有電性連接墊，且該導;^^線^增層結構之表面復 *土 ¥熱結構可連接至該電性連接執。 再者，該電路板結構復包括有一 該第二介電層表面，該第路層係形成於 電声中之塞〜“層可經由形成於該第二介 心ί 電性連接該半導體晶片之電極塾，且 4一線W係可經由-形成於該 表面形成有另一線路增層結構。 _線路〜層結構係包括介電層，疊置於該介電層上 二=以=成於該介電層中之導電結構，該線二曾 Z — '面覆盖有一防焊層’且該防焊層中形成有複數 :以路出該線路增層結構外表面之電性連接塾，於該防 、早i開孔中之电性連接墊表面形成有係為錫球 Ball)、接腳（pln)或LGA(land grid抓叮)之導電元件。 麟本务月之具有散熱件之電路板結構，係於對應該半導 =曰曰片之非主動面表面的第二介電層上形成供半導體晶片 政熱用之吸熱墊，使該吸熱墊間隔該介電層吸收該半導體 19829 9 200830975 曰曰片所產生的熱量，並經由線路增屑处 遞至位於外部的電性連接塾及導電：;;，俾以=傳 因此，本發明僅於$n ^ ▲ 卞1早以進仃散熱； 俚於承载板及半導體晶Μ矣而、仓> 過程中一併报 骽日日片表面進仃線路製程 乂成該吸熱墊及導熱結構，而無 ，件’因而可簡化製程以降低成本，並於承载板之；一： =了表面均形成有線路結構而提昇電路板結構之電性功 【實施方式】 • 以下係藉由特定的具體實例說明本發明之實施方 ^:熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 如第3A至3G圖所示者用以說明本發明之具有散熱件 之電路板結構之製法之剖面示意圖。 μ /如第3Α圖所示，首先，提供一承載板3〇，該承載板 3〇係選自電路板、絕緣板或金屬板，該承載板3〇係具有 一第一表面30a及與該第一表面3〇a相對之第二表面 30b，且於該承載板30中形成至少一貫穿之開口 $⑽。 如第3B圖所示，於該承載板3〇之第一表面3〇a形成 有一第一介電層31以封住該承载板開口 300之一端。 如第3C圖所示，於該開口 300中容置一係為主動式 晶片或被動式晶片之半導體晶片32，該半導體晶片32係 具有一主動面32a及與該主動面32a相對之非主動面 32b ’且該主動面32a具有複數電極墊321，並以該非主動 面3 2b接置於该弟一介電層31表面。 10 19829 200830975200830975 . « IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit board structure, and more particularly to a circuit board structure having a heat dissipating member. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, in which Ball grid array (BGA) is an advanced semiconductor package technology. The utility model is characterized in that a semiconductor substrate is arranged by using a package substrate, and a plurality of grid arrays of solder balls are formed on the back surface of the package substrate to have more input/output connection ends in the same unit area (I/ O connection), in order to meet the requirements of a highly integrated semiconductor wafer, and electrically connected to the external electronic device by the solder balls. In the conventional semiconductor package structure, the semiconductor wafer is adhered to the top surface of the substrate, and the semiconductor wafer is electrically connected to the substrate by wire bonding or flip chip bonding, and the solder ball is implanted on the back surface of the substrate. For the purpose of electrical connection; although the purpose of high number of feet can be achieved, in the case of higher frequency use or high speed operation, the performance of the electrical characteristics due to the long connection path of the wire cannot be improved, and there is a limit, and Because the traditional packaging requires multiple connection interfaces, the manufacturing cost is relatively increased. In addition, with the rapid development of the electronics industry, electronic products are gradually entering the direction of multi-functional, high-performance research and development. In order to meet the high integration and miniaturization of semiconductor packages 5 19829 200830975 - . The demand for semiconductor wafers will increase the amount of heat generated during operation, such as not effectively generating heat from semiconductor wafers in time. Dissipation will severely shorten the performance and lifetime of semiconductor wafers. In order to effectively improve the electrical quality to meet the application of the next generation of products, the industry has studied the use of the embedded in the carrier board for direct electrical connection, to shorten the electrical conduction path, and reduce signal loss, signal distortion and Improve the ability to operate at high speeds. As shown in Fig. 1, it is a schematic cross-sectional view of a package structure in which a half of a group of parts is buried in a substrate as shown in U.S. Patent No. 5,432,677. As shown in the figure, the package structure includes: a laminate layer 10 having a first surface 10a and a first surface 10b' corresponding to the first surface and at the pressure The opening 1 is formed with at least one opening 100 extending through the first and second surfaces 10a, 10b; and the second surface 10b of the pressing layer 1 is bonded to a heat dissipating member by an adhesive layer 12. A semiconductor wafer n is received in the opening 100, and the semiconductor wafer 11 is fixed in the opening 1 by an adhesive layer 12, and the semiconductor wafer has an active surface 11a and the active surface Ua. A plurality of electrode pads m are formed on the active surface 11a, and a line build-up structure 14 is formed on the first surface 10a of the bonding layer 10 and the active surface 11a of the semiconductor wafer 1 The line build-up structure 14 includes a dielectric layer 140, a circuit layer 141 stacked on the dielectric layer 140, and a conductive structure 142 formed in the dielectric layer 140, and the conductive structures 42 are electrically An electrode 塾111 connected to the semiconductor wafer 11; a second table of the embossed layer 10b and the non-active surface of the semiconductor wafer incorporating ub 11 of the bulk 198,296,200,830,975 »img y to the heat generating element when the heat radiating member 13 by the operation of the n semiconductor wafer is transferred to the outside. The chip-embedded package structure can solve the various defects of the prior art, but the heat sink 13 must be prepared externally, which complicates the manufacturing process and increases the manufacturing cost. Although the 5 f boundary has & the inactive surface of the semiconductor wafer embedded in the substrate is completely exposed to facilitate heat dissipation of the semiconductor wafer, and only the substrate table 7 has a line structure; as shown in FIG. U.S. Patent No. 10''7 includes a core board (core>20, the core board 20 having a first surface 20a and an opposite second surface 2〇b, and having a first surface 20a and An opening 200 of the second surface 20b; a semiconductor wafer (miCr〇eleCtr〇nicdie) 21 is housed in the opening 200, and the semiconductor wafer 21 has an active surface 2U and an opposite encapsulation material (encapWation material) 22 is filled in the gap between the semiconductor wafer 2] and the opening 200 to fix the semiconductor wafer 21 in the opening 200; the line build-up structure 23 is formed on the first surface 20a of the core board 2 And an active surface 2U of the +conductor wafer 21, the line build-up structure 23 includes a dielectric layer 230, a wiring layer 231 stacked on the dielectric layer 23, and formed in the dielectric layer 23? a conductive structure 232, and the conductive structures 232 are electrically connected to the The conductor pad is the electrode pad 211. Although the second surface 2b of the core board 20 and the inactive surface 21b of the semiconductor wafer 21 have no other components, the heat sink can be eliminated to reduce the cost, and the edge semiconductor wafer can be obtained. The non-active surface 21b of the 21 is exposed, so that the heat generated during the participation is directly radiated; however, the second acoustic surface 20b of the core board 20 does not form a line structure or is connected to other functions. 'And can not meet the multi-function circuit design: so = Therefore, how to propose a circuit board structure embedded with the right hot part at the same time, in order to facilitate the semiconductor crystal ^ ^ sheet and have the above-mentioned various missing technologies, to avoid problems. [Inventive content] _ In view of the above-mentioned shortcomings of the prior art, one of the main purposes of the present invention is to provide a circuit board structure having a heat sink, which is derived from a semiconductor surface. At the same time as the formation of the circuit on the surface of the electric layer, the ancient M au . ^ J ^ sub-form has a relatively semi-conducting 曰 发: = the heat absorbing pad '俾 for the semiconductor wafer to dissipate heat. 板 槿 X, ', purpose The invention provides a circuit having a heat dissipating member, and the electric function of the circuit board structure is formed on both sides of the circuit board. Fu Fu Shusheng Circuit The second object of the present invention is to provide a board structure having a heat dissipating member. Simplifying the process to reduce the cost. For the above and other purposes, the present invention provides a ί路 S': comprising: a carrier plate having a relative: an IS surface and a:: face, and at least one through the first - and An opening of the second surface; first: electricity::: formed on the first surface of the carrier plate to seal the opening: a 曰, +¥ body wafer, the system is placed in the opening of the carrier plate, the cymbal The active surface and the non-active surface are opposite to each other, and the active surface has a number of electrode pads, and the non-active surface is connected to the surface of the first dielectric layer, which is formed on the surface of the first dielectric layer. The active surface of the board is filled into the opening of the carrier board and the 'first circuit layer' is formed on the gap layer of the circuit layer having at least one alum, the surface of the electric layer, and the non-active of the conductor chip surface. A 'heat-absorbing mat is set to correspond to the year = sheet material includes 'line build-up layer and heat-absorbing surface, the line build-up' includes an electrical connection pad, and the guide; ^ ^ line ^ buildup The surface of the structure can be connected to the electrical connection. Furthermore, the circuit board structure further includes a surface of the second dielectric layer, the second layer is formed in the electro-acoustic plug - "the layer can be electrically connected to the semiconductor wafer via the second dielectric layer An electrode 塾, and a 4-wire W system may be formed on the surface by forming another line build-up structure. The _ line-layer structure includes a dielectric layer stacked on the dielectric layer. a conductive structure in the dielectric layer, the line 2 is Z-'face covered with a solder resist layer' and the solder resist layer is formed with a plurality of: an electrical connection between the outer surface of the line build-up structure The surface of the electrical connection pad in the early opening is formed with a conductive element which is a solder ball, a pin or a LGA. The structure is formed on the second dielectric layer corresponding to the surface of the inactive surface of the semiconductor film to form a heat absorption pad for the semiconductor wafer, so that the heat absorption pad is spaced apart from the dielectric layer to absorb the semiconductor. 19829 9 200830975 The heat generated by the cymbal is transferred to the external electrical connection via the line chip塾 导电 导电 导电 导电 导电 导电 导电 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此The surface of the day-to-day film is formed into the heat-absorbing pad and the heat-conducting structure, and the piece is not, and thus the process can be simplified to reduce the cost and the load-bearing plate; a: = the surface is formed with a line structure and the circuit board is raised EMBODIMENT OF THE INVENTION [Embodiment] The following describes the embodiments of the present invention by way of specific specific examples: Those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure of the present disclosure. 3A to 3G are diagrams for explaining the manufacturing method of the circuit board structure having the heat sink of the present invention. μ / As shown in Fig. 3, first, a carrier board 3 is provided, and the carrier board 3〇 The carrier board 3 has a first surface 30a and a second surface 30b opposite to the first surface 3〇a, and at least one of the carrier board 30 is formed in the carrier board 30. Through the opening $(10). As shown in Figure 3B A first dielectric layer 31 is formed on the first surface 3〇a of the carrier plate 3 to seal one end of the carrier plate opening 300. As shown in FIG. 3C, a line is accommodated in the opening 300. An active wafer or a passive wafer semiconductor wafer 32 having an active surface 32a and an inactive surface 32b' opposite the active surface 32a, and the active surface 32a has a plurality of electrode pads 321 and the active surface 3 2b is placed on the surface of the dielectric layer 31 of the younger brother. 10 19829 200830975
如第3D圖所示，於該承載板30之第二表面30b及半 導體晶片32之主動面32a形成一第二介電層33，並使該 第一及第二介電層31，33填充於該開口 300與半導體晶片 32之間的間隙中，俾以將該半導體晶片32固定於該開口 300中；該第一及第二介電層31，33係由FR-4樹脂、FR-5 樹脂、環氧樹脂（Epoxy )、聚酯樹脂（Polyesters )、氰 脂（Cyanate ester)、聚乙驢胺（？〇1>^111丨(^)、雙順丁烯二酸酉藍 亞胺/三氮I9KBT，Bismaleimide triazine)或混合環氧樹脂 玻、璃纖維（Glass fiber)等絕緣性材料製成。 如第3E圖所示，於該第一介電層31表面形成第一線 路層34及吸熱墊341，該吸熱墊341位置係對應該半導體 晶片32之非主動面32b;又於該第二介電層33表面形成 第二線路層35，並使該第二線路層35經由形成於該第二 介電層33中之導電結構351電性連接該半導體晶片32之 電極墊321;且於該承載板30中形成有至少一電鍍導通孔 (PTH)36電性連接該承載板30之第一表面30a及第二表面 30b之第一及第二線路層34,35。 本發明主要係於該第一介電層31表面形成第一線路 層34的同時一併形成該半導體晶片32散熱用之吸熱墊 341，該吸熱墊341係如銅墊，藉由該吸熱墊341間隔該第 一介電層31吸收半導體晶片32運作所產生的熱，因而無 須預先製備散熱件及組裝該散熱件，以簡化製程步驟，且 無須額外增加封裝結構之厚度，並於承載板3〇之第一及第 二表面30a、3Ob形成有第一及第二線路層34，35之線路結 11 19829As shown in FIG. 3D, a second dielectric layer 33 is formed on the second surface 30b of the carrier 30 and the active surface 32a of the semiconductor wafer 32, and the first and second dielectric layers 31, 33 are filled in In the gap between the opening 300 and the semiconductor wafer 32, the semiconductor wafer 32 is fixed in the opening 300; the first and second dielectric layers 31, 33 are made of FR-4 resin, FR-5 resin. Epoxy, Polyesters, Cyanate ester, Polyethylamine (?〇1>^111丨(^), bis-maleic acid indigo-imine/three Nitrogen I9KBT, Bismaleimide triazine) or mixed epoxy resin, glass fiber (Glass fiber) and other insulating materials. As shown in FIG. 3E, a first circuit layer 34 and a heat absorbing pad 341 are formed on the surface of the first dielectric layer 31. The position of the heat absorbing pad 341 corresponds to the inactive surface 32b of the semiconductor wafer 32. The second circuit layer 35 is formed on the surface of the electrical layer 33, and the second circuit layer 35 is electrically connected to the electrode pad 321 of the semiconductor wafer 32 via the conductive structure 351 formed in the second dielectric layer 33; At least one plated via (PTH) 36 is formed in the board 30 to electrically connect the first and second circuit layers 34, 35 of the first surface 30a and the second surface 30b of the carrier board 30. The present invention mainly forms a heat absorbing pad 341 for dissipating heat of the semiconductor wafer 32 while forming the first circuit layer 34 on the surface of the first dielectric layer 31. The heat absorbing pad 341 is a copper pad, and the heat absorbing pad 341 is used. The first dielectric layer 31 is spaced apart from the heat generated by the operation of the semiconductor wafer 32, so that the heat dissipating member is not prepared in advance and the heat dissipating member is assembled to simplify the process steps, and the thickness of the package structure is not required to be increased, and the carrier plate 3 The first and second surfaces 30a, 3Ob are formed with first and second circuit layers 34, 35 circuit junctions 11 19829
厶WO / J 構，以提昇電路板結構 如第3F圖所_ 私性功能。 _所不，於該第一八命 表面進行線路增層勢W電層31及第一線路層34 增磨結構〜括介二成-，層結構37。該線路 線路層371以及形成於嗦9入豎置於該介電層37〇上的 過该導電結構372係可恭。、“中之導電結構372，且透 該線路增層結構37 电性連接至該第一線路層34，又於 另外於讀介電芦面$成複數電性連接墊373。 ⑩導熱結構374係連接該第:仅t成有導熱結構374，而該 路增層結構37夕昂線路層34之吸熱墊341及該線 之電性連接轨 、 導熱結構374、帝w、主 土 以藉由該吸熱墊341、 私性連接墊373形成 另，於讀第二介電層33及第I欠熱路径。 增層製程以形杰口一^ 及乐—線路層h上進行線路 37,係包括介+ 、路增層結構37，，該線路增層結構 1尔匕符；ι電層37〇,、聂 人 07Γα U ^ , 且置於忒；丨龟層370,上的線路層 371 U及形成於該介電犀 ^ λχ ^ 曰中之涂電結構372，，且經由該導 電I口構372電性連接 ， 受主邊弟一線路層35，又於該線路增層 、。構3外表面形成有複數電性連接塾373，。 如第3G圖所示，於該線路增層結構37、37,外表面分 別覆盖一防焊層38,38,，且該防焊層38,38,中形成開孔 380,380’以露出該等電性連接塾373,373,，並於該電性連 接墊373,373’上形成例如錫球（solder Bali)、接腳（？叫或 LGA(land grid array)之導電元件39，俾供收納於該承載板 30中之該半導體晶片32以其表面之電極墊321、線路層 35、線路增層結構37,37,以及導電元件39電性導接至外部 12 19829 200830975 * 鼻 電子元件。 依上述製法，本發明復提出一種具有散熱件之電路板 結構，係包括：承載板30，係具有第一表面3〇a及相對之 第二表面30b，且具有至少一貫穿該第一及第二表面之開 口 300 ’第一介電層31 ’係形成於該承載板3〇之第—表面 3〇a以封住該開口 300之一端；至少一半導體晶片％，係 容置於該開口 300中，該半導體晶片32係具有一主動面 32a及相對之非主動面32b，且於該主動面3。具有複數 極墊切’並以該非主動面饥接置於該第一介電層幻表 面；第二介電層33’係形成於該承載板3()之第 鳩 與半導體晶片32之主動面32a，並填入該承載板3〇之開b 口 300與半導體晶片32之間的間隙中；以及第一線路声 34 ’係形成於該第—介電層31，且該第—線路層％具^ 至少一吸熱墊341，該吸埶巷〆 1位置係對應該半導體晶 片32之非主動面32b。 該電路板結構復包括有第二介電層33及第二 35 ’係形成於該承载板3〇之第—+ ' ^ ”之主動面32a，且該第半導體，晶片 “ 弟—線路層35經由形成於該第二介 电層33中之導電結構351 ；， 扛轨包『生連接遠+導體晶片32之雷 極墊321，又該承載板3〇中 ()6以电性連接該第—及第二線路層34 35。 該電路板結構復可包括有線’ 該第一介電芦31乃笼一 ^ °構37係形成於 芦砝構37，曰仫农4 、、路層34表面，以及另一線路擗 4 7 ’係形成於該第二介電層Μ及第二線路層3/ 19829 13 200830975 - » 表面，該線路增層結構37,37,係包括介電層370,370,、疊 置於該介電層表面的線路層371，371，以及形成於該介電層 中之導電結構372,372,，且經由該導電結構372,372，係可 供該線路增層結構37,37,分別電性連接該第一線路層34 及=一線路層35;又於該線路增層結構37,37，外表面形成 有複數電性連接墊373,373,。 忒線路增層結構37中復包括有導熱結構374，係用以 連接該吸熱墊341及電性連接墊373,藉以形成一由吸熱 墊341、導熱結構374及電性連接墊373構成的散熱路徑。 、曰復於該線路增層結構37、37，外表面分別覆蓋有一防 丈干層38,38 ’且該防焊層38,38’中具有複數開孔職綱， 以露出該祕增層結構37、37,外表面之電性連接塾奶、 =3’ ’於該些電性連接墊373、奶，表面形成例如錫球 (Sender Ball)、接腳（pin)或心(1咖 _ = 39’俾供收納於該承載板3Q中之該半導體晶片m 2之電極墊321、線路層35、線路增層結構37,37,以及 蜍毛疋件39電性導接至外部電子元件。 在认综上所述’本發明之具有散熱件之電路板結構，主要 係於該半導體晶片非 m 之弟一介電層上對應形成嵛 …用之吸熱墊，使該吸熱墊間隔該第一入恭 體曰Μ姦砝沾為- 弟，丨廷層吸收該半導 禮，並將該熱量經由形成於該線路增層社 ，中之¥熱結構及線路增層結構外表面之電性連接^ 電兀件以作為散熱路徑傳遞，俾以進行 。 、 明僅需於承载板及半導體晶片月… 泣，本發 表面進行線路製程過程中一 19829 14 200830975 併形成該吸熱墊及導熱結構， ^ 7 „ 稱而無須頟外製備散熱件，因 而可間化製程以降低成本；i於承載板之第—及第 均形成有線路結構*提昇電路板結構之n力能。、 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 =本發明之精神及範疇下，對上述實施例進行修飾與改延 變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 _【圖式簡單說明】 第1圖係為美國專利第5,432,677號之剖面示意圖； 第2圖係為美國專利第6,586,822號之結構剖視圖； 以及 第3 A至3G圖係為本發明具有散熱件之電路板結構的 製法剖面示意圖。 【主要元件符號說明】 10 壓合層 l〇a、20a、30a 第一表面 l〇b、20b、30b 第二表面 100 、 200 、 300 開口 11 、 21 、 32 半導體晶片 111 、 211 、 321 電極塾 11a、21a、32a 主動面 11b、21b、32b 非主動面 12 黏著層 15 19829 200830975 - » 13 散熱件 14、23、37、37’ 線路增層結構 140、 230、370、37CT 介電層 141、 231、371、371’ 線路層 372’、374 導電結構 核芯板 封裝材料 承載板 第一介電層 第二介電層 第一線路層 吸熱墊 第二線路層 電鍛導通孔 電性連接墊 防焊層 開孔 導電元件 142 、 232 、 351 、 372 、 20 22 30 • 31 33 34 341 35 36 373 、 3735 38 ^ 38? • 380 、 380’ 39 16 19829厶WO / J structure to enhance the board structure as shown in Figure 3F _ private function. _No, on the first octal surface, the line-increasing potential W-electric layer 31 and the first wiring layer 34 are ground-grinding structure---------------------------- The wiring layer 371 and the conductive structure 372 formed on the dielectric layer 37A are formed on the dielectric layer 37. The conductive structure 372 is electrically connected to the first circuit layer 34 through the line build-up structure 37, and is further connected to the dielectric reed surface into a plurality of electrical connection pads 373. 10 Thermally conductive structure 374 Connecting the first: only t is formed with a heat conducting structure 374, and the heat absorbing pad 341 of the road layering structure 37 and the electrical connecting rail of the line, the heat conducting structure 374, the emperor w, the main soil are The heat absorbing pad 341 and the private connection pad 373 are formed to read the second dielectric layer 33 and the first underheating path. The layering process is performed on the line jiekou and the circuit layer h, and the line 37 is included. +, road build-up structure 37, the line build-up structure 1 er character; 1 electric layer 37 〇, Nie people 07 Γ α U ^, and placed in the 忒; 丨 turtle layer 370, the circuit layer 371 U and formed The dielectric structure 372 in the dielectric rhinoceros λ χ ^ ,, and electrically connected via the conductive I-port 372, the acceptor-side circuit layer 35, and the additional layer on the line Forming a plurality of electrical connections 塾 373, as shown in FIG. 3G, the outer surface of the line build-up structures 37, 37 is covered with a solder resist layer 38, 38, respectively, and Openings 380, 380' are formed in the solder resist layers 38, 38 to expose the electrical connections 373, 373, and solder balls, pins (? or LGA) are formed on the electrical connection pads 373, 373'. The conductive element 39 of the (land grid array), the electrode pad 321 of the semiconductor wafer 32 housed in the carrier plate 30, the circuit layer 35, the line build-up structure 37, 37, and the conductive element 39 are electrically connected. Guided to the outside 12 19829 200830975 * Nasal electronic component. According to the above method, the present invention further provides a circuit board structure having a heat dissipating member, comprising: a carrier plate 30 having a first surface 3A and an opposite second surface 30b, and having at least one opening 300' through the first and second surfaces, a first dielectric layer 31' is formed on the first surface 3a of the carrier plate 3 to seal one end of the opening 300; A semiconductor wafer % is disposed in the opening 300. The semiconductor wafer 32 has an active surface 32a and an opposite inactive surface 32b, and the active surface 3 has a complex pole cut and a non-active surface Hunger placed in the first dielectric layer The second dielectric layer 33' is formed on the second surface of the carrier 3 () and the active surface 32a of the semiconductor wafer 32, and is filled in the gap between the opening 300 of the carrier 3 and the semiconductor wafer 32. And a first line sound 34' is formed on the first dielectric layer 31, and the first circuit layer % has at least one heat absorption pad 341, and the position of the suction channel 1 corresponds to the semiconductor wafer 32. Active face 32b. The circuit board structure further includes a second dielectric layer 33 and a second 35' formed on the active surface 32a of the carrier layer 3 -, and the semiconductor, the wafer "the circuit layer 35" Via the conductive structure 351 formed in the second dielectric layer 33, the rail package "connects the lightning pad 321 of the far + conductor wafer 32, and the carrier plate 3 (6) is electrically connected to the first - and second circuit layer 34 35. The circuit board structure may include a wire. The first dielectric reed 31 is a cage structure formed on the reed structure 37, the surface of the road layer 34, and the other line 擗 4 7 ' Formed on the second dielectric layer and the second circuit layer 3/ 19829 13 200830975 - » surface, the line build-up structure 37, 37, comprising a dielectric layer 370, 370, stacked on the surface of the dielectric layer The circuit layers 371, 371, and the conductive structures 372, 372 formed in the dielectric layer, and through the conductive structures 372, 372, the line build-up structures 37, 37 are electrically connected to the first circuit layer 34 and = a circuit layer 35; and in the circuit build-up structure 37, 37, a plurality of electrical connection pads 373, 373 are formed on the outer surface. The 忒 line build-up structure 37 further includes a heat-conducting structure 374 for connecting the heat-absorbing pad 341 and the electrical connection pad 373 to form a heat dissipation path formed by the heat-absorbing pad 341, the heat-conducting structure 374 and the electrical connection pad 373. . And the additional layer structures 37, 37 are covered, and the outer surface is respectively covered with an anti-drying layer 38, 38' and the solder resist layer 38, 38' has a plurality of open-hole posts to expose the secret layer structure 37, 37, the external surface of the electrical connection with milk, = 3 ' ' on the electrical connection pads 373, milk, the surface forms, for example, a solder ball (Sender Ball), pin (pin) or heart (1 coffee _ = The electrode pad 321 of the semiconductor wafer m 2, the circuit layer 35, the line build-up structures 37, 37, and the bristles 39 are electrically connected to the external electronic components. In summary, the circuit board structure of the present invention having a heat dissipating member is mainly formed on a dielectric layer of the semiconductor chip, which is formed by a heat absorbing pad, so that the heat absorbing pad is spaced apart from the first hole. Congratulations, sorrows and sorrows are smothered - the younger brother, the sputum layer absorbs the semi-guided ritual, and electrically connects the heat to the outer surface of the heat-generating structure and the line-enhanced structure formed in the line. The electric pick-up piece is transmitted as a heat-dissipating path, and is carried out. It is only necessary to carry the carrier board and the semiconductor wafer... The surface is processed in the process of a line process of 19829 14 200830975 and the heat absorbing pad and the heat conducting structure are formed, ^ 7 „ said that the heat sink is not required to be prepared, so that the process can be reduced to reduce the cost; i is the first and the first of the carrier plate The present invention is merely illustrative of the principles of the present invention and its effects, and is not intended to limit the present invention. Anyone skilled in the art can In the spirit and scope of the present invention, the above embodiments are modified and modified. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described later. _ [Simple description of the drawing] A cross-sectional view of U.S. Patent No. 5,432,677; Fig. 2 is a cross-sectional view of the structure of U.S. Patent No. 6,586,822; and Figs. 3A to 3G are schematic cross-sectional views of a circuit board structure having a heat dissipating member of the present invention. DESCRIPTION OF SYMBOLS 10 Pressing layer l〇a, 20a, 30a First surface l〇b, 20b, 30b Second surface 100, 200, 300 Opening 11, 21, 32 Semiconductor crystal 111, 211, 321 electrode 塾 11a, 21a, 32a active surface 11b, 21b, 32b inactive surface 12 adhesive layer 15 19829 200830975 - » 13 heat sink 14, 23, 37, 37' line build-up structure 140, 230, 370 37CT dielectric layer 141, 231, 371, 371' circuit layer 372', 374 conductive structure core board packaging material carrier board first dielectric layer second dielectric layer first circuit layer heat absorbing pad second circuit layer electric forging Via Electrical Connection Pad Solder Mask Opening Conductive Element 142, 232, 351, 372, 20 22 30 • 31 33 34 341 35 36 373 , 3735 38 ^ 38? • 380 , 380' 39 16 19829