TW526600B - Semiconductor device including a heat spreader - Google Patents

Abstract

A semiconductor package including a heat spreader is provided. In the package, the heat spreader is mounted on a surface of a substrate used to fix solder balls; the substrate is provided with at least one through hole for accommodating a semiconductor die in a manner that the semiconductor die is in no contact with the substrate. A thermally conductive paste containing metal particles is used to attach the heat spreader to the semiconductor die and substrate, allowing an end of the through hole of the substrate to be sealed by the heat spreader. As the heat spreader is performed as a die carrier, the semiconductor die is provided with a direct heat-dissipated route by the thermally conductive paste and the heat spreader, making the semiconductor package improved in thermally conductive efficiency. Also, the heat spreader between the semiconductor die and an external device to which the semiconductor package is attached, is capable of shielding electromagnetic interference, allowing the electrical performance of the semiconductor package to be enhanced.

Description

526600 V. Description of the Invention (i) [Field of the Invention] ... The present invention relates to a semiconductor package, which is a semiconductor package for improving heat dissipation efficiency. //, heat dissipation [Previous technical description]: How to effectively dissipate the semi-conductive sea bass in use to ensure that the heat generated by the semi-coated half of the semiconductor chip is used in the use of Zhegu & *% < 'Life and quality' has always been a major issue in the semiconductor packaging industry) 2 = The packaging colloid (―t) covering the semiconductor wafer is uniform ... Poorly conductive packaging resin such as epoxy resin (Modding)

Compound), so that the heat generated by the chip cannot often be packaged, and the grease can effectively escape. Therefore, a heat dissipation structure is added to the semiconductor package to make heat sinks or heat sinks made of metal materials with good heat dissipation. It is a feasible way to improve heat dissipation efficiency with Heat Block. However, if the heat sink is also completely covered by the encapsulating gel, the heat generated by the chip must be dissipated through the heat dissipating path of the encapsulating gel. The improvement of heat dissipation efficiency is limited by j ', and it is even difficult to meet the heat dissipation requirement of the chip. Therefore, it is more ideal to make the surface of the heat sink 2 exposed to the sealing gel so that the heat generated by the chip can be dissipated ... and directly dissipated outside the surface of the chip in the atmosphere. If it is not directly connected to the heat sink and the chip and the heat sink are filled with packaging resin, the heat generated by the chip cannot be directly transferred to the two engraved sheets and still needs to pass through the packaging gel with poor thermal conductivity. Thermal efficiency is still limited. Zhifeng proposed the conductor package as shown in Figure 3 in U.S. Patent No. 5,726,079. This kind of conventional semiconductor package 2 is based on semiconductor 贌 16578.ptd

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526600 V. Outline of the Invention-A male fin 24 is directly attached with a heat sink 22, so that the top surface 22 of the heat sink 22 is exposed to the outside of the encapsulant 26 for covering the wafer 24. Since the chip 24 is directly adhered to the heat sink 22 and the top surface 220 of the heat sink 22 is exposed to the f-filled gel 26 and directly contacts the atmosphere, the heat generated by the operation of the chip 24 can be directly transferred to the heat sink 22 and then dissipated to In the atmosphere, its heat transfer path has no better heat dissipation efficiency by encapsulating the gel 26. However, this type of semiconductor package 2 has several defects in manufacturing. First of all, when the heat sink 22 and the chip 24 are adhered and placed in a cavity (mold and cavity) (not shown) of the packaging mold to perform the molding operation for forming the packaging colloid 26, the heat sink 22 must fit the mold exactly. The top wall of the cavity (not shown) can maintain good packaging quality. However, in fact, it is very difficult to properly arrange the heat sink 2 2 and the top wall of the cavity (not shown): when the top wall of the cavity (not shown) fails to effectively resist the top surface 220 of the heat sink 22 When voids are generated, the encapsulating resin (same as the encapsulating gel 26) forming the encapsulant 26 will overflow onto the top surface 220 of the heat sink 22, which not only makes the appearance of the packaged product poor, but also hinders the heat dissipation efficiency of the heat sink 22; If the pressure channel under the heat sink 22 is too strong on the top wall of the mold cavity, the brittle wafer 24 is often difficult to bear and cracks occur. Furthermore, as shown in FIG. 4, since the heat generated by the operation of the chip is radiated to the surroundings, some of the heat can be released through the heat sink 22 placed above the chip 24, but there is still a lot of heat. Conductive traces 214 passing through the bottom of the semiconductor wafer 24 and the adhesive layer 23 fixed on the wafer 24 to the surface of the substrate 21 are transmitted through most of the conductive vias 212 (Vias) inside the substrate 21 and under the substrate 21 Surface 211 solder ball 27 re-pass

526600 V. Description of the invention (3) It reaches the printed circuit board 28. This heat dissipation path must pass through an adhesive layer 23, but the adhesive layer 23 is made of a resin material and is hygroscopic in nature. Therefore, if moisture is intruded into the conductive through holes 212 communicating with the upper and lower surfaces of the substrate 21 It is often absorbed by the adhesive layer 23, and the hygroscopic adhesive layer 23 is likely to cause the interlayer Swelling or popcorn phenomenon in the subsequent high temperature process, especially the substrate 21 is used to conduct electricity. The above-mentioned problems are more likely to occur in a packaging method in which a wafer 24 is directly adhered above a hole or a semiconductor package made of a high electron density type such as a stacked wafer or an enlarged wafer. [Summary of the invention]: The main purpose of the present invention is to provide a semiconductor package with a heat sink, which allows the heat sink to be completely exposed directly outside the package without increasing the overall height of the packaged product, thereby maintaining the maximum heat dissipation area. And there is no suspicion of overflowing glue, which can maximize the heat dissipation efficiency. Another object of the present invention is to provide a semiconductor package with a heat sink, so that the heat sink and the wafer can be directly adhered to improve the heat dissipation efficiency, and not to cause chip cracks during the molding process, and ensure that the yield to the finished product is improved. . Another object of the present invention is to provide a semiconductor package with a heat sink, so that moisture inside the substrate will not be absorbed by the adhesive, so as to prevent the adhesive from absorbing moisture and causing gas explosion or bonding layer bulging in the high temperature process. Maintain excellent reliability in wafer bonding. ^ Another object of the present invention is to provide a semiconductor package with a heat sink, so that the chip and the external printed circuit board are blocked by the heat sink to increase the electricity.

526600 V. Description of the invention (4) Magnetic shielding effect, to reduce improper electromagnetic interference and significantly improve the electrical function of the package. In order to achieve the disclosure and other purposes, the semiconductor package with a heat sink provided by the present invention includes a substrate having at least one through hole formed thereon; a heat sink (such as a copper sheet) having a first surface And an opposite second surface, a copper-containing adhesive is arranged on the first surface, so that the heat sink is adhered to the substrate to close one side opening of the through opening; at least one chip, It is stored in the through hole of the substrate, and the adhesive is used to make the chip firmly adhered to the first surface of the heat sink; a plurality of first conductive elements (such as gold wires) are provided for the semiconductor wafer. Forming an electrical connection with the substrate; a plurality of second conductive elements (such as solder balls) are disposed on the substrate on the same side as the heat sink, so as to provide the substrate with electrical conduction to the external environment; and An encapsulating gel covering the semiconductor wafer. The semiconductor package of the present invention uses a heat sink as a carrier for wafer adhesion. Therefore, the adhesive for providing wafer adhesion only needs to be coated on the heat sink, and the substrate does not need to be directly attached to the surface of the wafer. The conductive vias (Vias) are invaded by external moisture, and will not affect the adhesive on the heat sink. At the same time, the Chip Paste is provided because it is rich in most Copper Particles with good thermal conductivity. ), Then directly apply an adhesive on the heat sink to carry the wafer, so that the heat generated by the semiconductor wafer can be directly transferred to the heat sink through the adhesive to escape, so that the heat dissipation path is minimized. Furthermore, since the heat sink is disposed on the surface of the substrate on the same side as the second conductive element, that is, the heat sink and the active surface of the wafer and the area where the gold wires are laid out, etc.

16578.ptd Page 10 526600 V. Description of the invention (5) The part that needs to be covered by the encapsulating colloid is divided into the front and back sides of the substrate. Therefore, it is not necessary to consider the height of the cavity top wall and the heat sink when the semi-finished package is subjected to the molding process Whether it cooperates, there is no risk of chip fracturing or glue overflow. In addition, when the packaged semiconductor device is re-soldered to the printed circuit board, the heat sink is hidden in the gap between the bottom of the chip and the original printed circuit board for the second conductive component. The addition of the heat sink will not increase the package at all. The overall thickness of the finished product; further, the electromagnetic shielding effect of the chip can be enhanced by the electromagnetic shielding wall formed by the metal thin plate (ie, heat sink) between the bottom of the chip and the printed circuit board, so that improper electromagnetic interference can be reduced to make the finished product Has better electrical quality. [Brief description of the drawings]: The following is a detailed description of the features and effects of the present invention with preferred specific examples and the attached drawings: Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. The figure is a schematic cross-sectional view of the semiconductor package of the present invention after being electrically connected to an external device; FIG. 3 is a cross-sectional view of the semiconductor package of US Patent No. 5, 72 6, 07 9 is not intended, and FIG. 4 is conventional A partially enlarged view of a semiconductor package that is missing during high temperature and molding. [Detailed description of the invention]: As shown in FIG. 1, the semiconductor package 1 of the present invention includes a substrate 11 which is provided with at least one through-hole 1 1 3 therein; a heat sink 12 for

16578.ptd Page 11 526600 V. Description of Invention (6)

An opening ii 3 a is closed on one side of the through-opening hole 11 3; an adhesive 丨 3 is a coating part on the heat sink 12 for the heat sink 12 to be adhered to the surface of the substrate u; at least one semiconductor wafer 14 The adhesive 13 is adhered to the heat sink I ?; a plurality of gold wires 15 provide a conductive connection between the wafer 4 and the substrate 丨; most of the solder balls 17 are placed in contact with the The heat sink 12 is on a substrate ii on the same side for the substrate 11 to be electrically connected to an external device (such as a printed circuit board 8); and, a packaging gel for covering the semiconductor wafer 14 and the gold wires 15 16. However, according to the application range of the actual finished product, the semiconductor package 1 can be manufactured by batch manufacturing or one-by-one assembly. The material of the substrate 11 is made of FR-4 resin, FR-5 resin, BT (Bismaleimide Triazine) resin, or one of organic materials such as tape and polyimide. Wherein, the substrate 11 has an upper surface 110, a lower surface 111 ′ opposite to the upper surface 110, and a plurality of conductive vias 112 (V1 as) communicating with the upper and lower surfaces 110, Π1; At least one through-opening hole 11 3 is provided, and the size of the through-opening hole 1 1 3 must be larger than the area of the wafer (not shown) for wafer storage and placement. In addition, a plurality of conductive traces 114 (conductive traces) are formed on the upper and lower surfaces of the substrate 11 so that the chip signals can be transmitted to the substrate through the conductive vias 114 on the upper surface 11 of the substrate 11 through the conductive vias 112. 11 on the lower surface 丨 丨 丨. The heat sink 12 is a thin plate structure made of steel, copper alloy, silver, silver alloy, or other metal material with good thermal conductivity; it has a first surface 120 and a first surface 120 opposite to the first surface 120.二 表面 121。 Two surfaces 121. However, in order to prevent the heat sink 12 from hindering the subsequent ball planting operation, the thickness t of the heat sink 12 is t

16578.ptd Page 12 526600 V. Description of the invention (7) The vertical height h of the solder ball (represented by the virtual circle on the lower surface of the substrate) after reflow must be limited; the heat sink is blackened (B1 ack Oxidation), browning (Brown Oxidation) or horizontal browning, etc., to passivate the first surface 120 of the heat sink 12 to improve the insulation and adhesiveness of the first surface 120. Adhesive 1 3 Ability to join 0

The adhesive 13 is an adhesive material made of at least one organic medium (〇rganic Vehicle) and a solvent uniformly mixed with a metal powder selected from the group consisting of copper, steel alloy, silver, silver alloy, and the like. After the adhesive 13 is coated on the first surface of the sheet, the adhesive 13 filled with metal particles having excellent thermal conductivity such as copper and silver also has a good thermal conductivity function; so that the heat generated by the operation of the chip can be quickly It is transferred to the heat sink 12 through the adhesive layer 13. The heat sink 1 2 coated with the adhesive 1 3 is adhered to the lower surface 111 of the substrate 11 to close the through opening! After one of the three sides is opened, the heat sink i 2 can be used to carry the chip 1 4.

The semiconductor wafer 14 has an active surface 140 (that is, a surface on which most electronic circuits and electronic components are arranged) and an opposite non-active surface 1 4 1 ′ + when the wafer is received into the substrate 1 and the through hole is provided. After the non-active surface 141 of the wafer is adhered to the first surface ι20 of the heat sink 12 with the adhesive 13, the semiconductor wafer 14 is electrically connected to the upper surface 110 'of the substrate 11 with a plurality of gold wires 15 and the encapsulation gel is used. 16 The coated semiconductor wafer 14 and the gold wires 15 maintain the airtight isolation state of the wafer active surface 140 and the distribution area of the gold wires 15 for telecommunication transmission from the outside. Because the heat sink 12 and the encapsulant 16 cover the chip 14 and the gold wire

16578.ptd Page 13 526600 V. Description of the invention (8) The 15 area is divided into the front and back sides of the substrate Π, so the mold (not shown) used to form the encapsulant 16 need not be set with the height of the heat sink 12 There is also no risk of chip fracturing or glue overflow. The heat sink 12 connected to the lower surface ui of the substrate can also completely avoid being formed on the upper surface of the substrate u. The gel 16 causes the heat sink 12 to be completely exposed and lifted up. Lu Yuda ... significant heat dissipation The planting of these solder balls 17 is to place the chip on the circuit board 18. As shown in Figure 2 #, the loose film '; tin: Bu Bu printed board on the same side can ensure solder balls! 7 times fresh to the printed circuit board, the female piece of soil is hidden in the semiconductor wafer 1 4 and the printed circuit / scattered ", the planting of the space ', so the heat sink 18: two: for the tin ball The overall thickness of 17; at the same time, the electromagnetic shielding wall formed by the semiconductor wafer «packaged finished products, 1000-day solar panels 1 4 and printed circuit 柘 metal material heat sink 12 (Electromagnetic Shield) can provide an electromagnetic shielding effect Less electromagnetic interference from the chip, so that the packaged products are better. However, the above are only specific embodiments of the present invention and are not applicable. For those who are familiar with this technology, they will not detain from this month. One of the modifications completed under the spirit and principle should be covered by the following patent application. * 2 changes or [component symbol description] · 1.2 semiconductor package 110 upper surface of the substrate 112, 212 conductive Holes 114, 214 conductive traces

I 11.21 Base plate 111, 211 Base plate bottom surface 113 Through hole 1 2, 22 Heat sink

526600

V. Description of the invention (9) 120,220 First surface 121 Second surface 13, 23 Adhesive 14, 24 Semiconductor wafer 140 Active surface 141 Non-active surface 15 Gold wire 16, 26 Packaging gel 17, 27 Solder ball 18, 28 Exterior Printed Circuit Board h Vertical height of solder ball after soldering t Thickness of scatter sheet 16578.ptd Page 15

Claims (1)

526600 VI. Scope of patent application 1. A semiconductor package with a heat sink comprising: a substrate having at least one through-hole formed thereon; a heat sink having a first surface and an opposite second surface Pre-arranged an adhesive containing metal particles on the first surface, thereby adhering the heat sink to the substrate, so that one side of the through-hole is formed into a closed state; at least one semiconductor wafer, It is stored in the through-hole of the substrate, and the semiconductor wafer is firmly fixed on the first surface of the heat sink by the adhesive; a plurality of first conductive elements are provided for the semiconductor wafer and the substrate. An electrical connection relationship is formed between the boards; a plurality of second conductive elements are implanted on a substrate on the same side as the heat sink to provide the substrate to be electrically connected to external devices; and a packaging gel for packaging Covering the semiconductor wafer and the first conductive elements. 2. The semiconductor package according to item 1 of the patent application scope, wherein the semiconductor package is a ball grid array (B a 1 1 G r i d A r r ay, B G A) semiconductor package. 3. The semiconductor package according to item 1 of the patent application scope, wherein the heat dissipation sheet is a thin metal plate. 4. The semiconductor package of claim 1 in which the material of the heat sink is one selected from the group consisting of copper, copper alloy, silver, silver alloy, and other metals with good thermal conductivity. 16578.ptd Page 16 526600 VI. Scope of patent application 5. Such as the first application for the film). 6. If the application is the first one). 7. If you apply for the first film 8. If you apply for a special particle system, select one of the groups. 9. If you apply for a special adhesive, the media is evenly mixed. 10. If you apply for a special agent, the surface should be made of copper. From the top to the top of the thermal range of the thermal range of the favorable range, the semiconductor package of the first range of the thermal range of the profit range is on the surface of the first range of the cloth range. Among them, the heat-dissipating glue is blackened before (the semiconductor package of the first category of Black Oxidation, where the heat dissipation Standardize before glue (Brown Oxidation semiconductor package of item 1), where the heat is horizontally browned before the glue is applied. The semiconductor package of item 1, wherein the metal, copper alloy, The semiconductor package of item 1 or 8 composed of metal powder such as silver, silver alloy, etc., wherein the one organic vehicle (organic vehicle) and the molten metal powder are produced. The semiconductor package of item 1, wherein: The Thermal Conductive Paste 1 1. For the semiconductor package of the first scope of the patent application, wherein the first conductive element is a gold wire. 1 2. For the semiconductor package of the first scope of the patent application The thickness of the heat sink must be smaller than the vertical height of the second conductive element after reflow. 1 3. For the semiconductor package of item 1 of the patent application scope, wherein the first 2. The conductive element is a tin ball. 1 4. The semiconductor package according to item 1 of the patent application scope, wherein the external 16578.ptd Page 17 526600 16578.ptd Page 18