TWI249231B - Flip-chip package structure with embedded chip in substrate - Google Patents

Flip-chip package structure with embedded chip in substrate Download PDF

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Publication number
TWI249231B
TWI249231B TW093138303A TW93138303A TWI249231B TW I249231 B TWI249231 B TW I249231B TW 093138303 A TW093138303 A TW 093138303A TW 93138303 A TW93138303 A TW 93138303A TW I249231 B TWI249231 B TW I249231B
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Taiwan
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wafer
layer
substrate
embedded
conductive
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TW093138303A
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Chinese (zh)
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TW200620598A (en
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Shih-Ping Hsu
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Phoenix Prec Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A flip-chip package structure with an embedded chip in a substrate is proposed. A heat sink having a plurality of cavities and openings is provided. At least one semiconductor chip is received in one of the cavities of the heat sink. An insulating layer is applied on upper and lower surfaces of the heat sink and the semiconductor chip, and fills a gap between the semiconductor chip and the heat sink, as well as covers walls of the openings of the heat sink. At least one circuit layer is formed on the insulating layer, and is electrically connected to the semiconductor chip by conductor structures formed in the insulating layer. A plurality of conductive vias are formed in the openings having their walls covered by the insulating layer, and electrically connect the circuit layers located above the upper and lower surfaces of the heat sink to each other. The heat sink provides good support and heat dissipation efficiency, such that the semiconductor chip can be embedded in the corresponding cavity of the heat sink to make good use of substrate space, and the semiconductor chip can be directly electrically connected to the circuit layers, thereby simplifying the semiconductor fabrication processes and the integration problem.

Description

1249231 九、發明說明： 【發明所屬之技術領域】 - 本發明係有關於一種具有晶片埋入基板之覆晶封裝 結構，尤指一種以散熱板作為電路板核心，並將半導體元 件收納於通孔開孔之半導體裝置，用以提升半導體裝置之 電性及散熱功能。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 * (Integration )以及微型化（Miniaturization )的封裝需求， 提供多數主、被動元件及線路載接之電路板（Circuit Board )亦逐漸由單層板演變成多層板（Multi-layer Board )，俾於有限白勺空間下，藉由層間連接技術（Interlayer Connection )擴大電路板上可利用的電路面積而配合高電 子密度之積體電路（Integrated Circuit )需求。 目前，大多數半導體封裝件中，半導體元件（例如半鲁 導體晶片，被動元件等）係放置於封裝基板表面，而作為 半導體元件承載件（Chip carrier)之基板，通常具有一芯層 (Core layer)，該芯層得以樹脂材質如環氧樹脂（Epoxy resin)、聚亞醯胺（Polyimide)樹脂、BT(Bismaleimide Trazine) 樹脂、FR4樹脂等製成。然後於芯層之相對上、下表面進 行壓合或增層絕緣材料，並形成導電金屬層，使導電金屬 層經圖案化製程而形成多數導電線路。接著，敷設防銲層 (Soldermask)等絕緣性材料於最外層以形成保護層，而完 6 18109 1249231 成半導體基板結構。 現今業界常用之覆晶基板所存在之技術及缺點特徵 如下： 1·被動元件和IC晶片是置放於基板表面，因ic晶片 和被動元件相連接路徑長，使得電性品質不易提昇，且表 面有限之設計佈線空間受到限制。 2·被動tl件置於基板表面須經多次回銲過程，使有機 基板再次遭受高溫回焊之破壞，尤其是在焊接不良重工時 更易發生。 3. IC晶片散熱功能僅藉由在晶片上方置放散埶月加 以散熱。 … 【發明内容】 鑒；上述4知技術之缺點及限制，本 =-種具加強散熱功能之具有晶片埋入基板= 旦構’係可有效逸散半導體晶片於運作時所產生之熱 之另—目的在於提供一種具有晶片 二：:斗藉以減少半導體裝置承载晶片嶋 產生，以提升半導體產品製程信賴性。1249231 IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip package structure having a wafer embedded in a substrate, and more particularly to a heat sink as a core of a circuit board and housing the semiconductor component in the through hole A semiconductor device for opening a hole for improving the electrical and heat dissipation functions of the semiconductor device. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high-integration* (Integration) and miniaturization packaging requirements of semiconductor packages, circuit boards that provide most of the main and passive components and line-loading circuits have gradually evolved from single-layer boards to multi-layer boards. (Multi-layer Board), in the limited space, expand the circuit area available on the board by Interlayer Connection to match the high-electron density integrated circuit requirements. At present, in most semiconductor packages, semiconductor components (such as semi-lub conductor wafers, passive components, etc.) are placed on the surface of the package substrate, and as a substrate of a semiconductor carrier carrier, there is usually a core layer (Core layer). The core layer is made of a resin material such as an epoxy resin, a polyimide resin, a BT (Bismaleimide Trazine) resin, an FR4 resin, or the like. Then, the opposite upper and lower surfaces of the core layer are pressed or layered with an insulating material, and a conductive metal layer is formed, and the conductive metal layer is patterned to form a plurality of conductive lines. Next, an insulating material such as a solder mask is applied to the outermost layer to form a protective layer, and the semiconductor substrate structure is completed by 6 18109 1249231. The techniques and shortcomings of the flip-chip substrates commonly used in the industry today are as follows: 1. The passive component and the IC chip are placed on the surface of the substrate, and the connection path between the ic chip and the passive component is long, so that the electrical quality is not easily improved, and the surface is Limited design wiring space is limited. 2. Passive tl parts are placed on the surface of the substrate through multiple reflow processes, so that the organic substrate is again subjected to high temperature reflow damage, especially when the welding is poor. 3. The IC chip heat dissipation function is only used to dissipate heat by placing it on top of the wafer. The invention has the disadvantages and limitations of the above-mentioned four known technologies. The present invention has a wafer-embedded substrate with a heat-dissipating function, which can effectively dissipate the heat generated by the semiconductor wafer during operation. - The objective is to provide a wafer 2: to reduce the generation of wafers for semiconductor devices to enhance the reliability of semiconductor product process.

之覆一目的在於提供一種具有晶片埋入基板 曰““構’俾提昇基板之佈 局靈活性及半導體元件之佈設數量。 θ加線W 本發明之又—目的在於提供 之覆晶封裝結構，俾可同時整a 埋入基板 了正〇日日片承载件之製造與晶片 7 18109 1249231 封裝f标，以簡化半導體業者製程與界面整合問題。 本發明之又-目的係提供一種具有晶片埋入其板之 人基：目:包:發”露;種具有“埋 孔開孔之散熱板；至少一半導雕曰 、 之nm — ,丰^肢日日片，係收納於該散熱板 =，㈤、、、"，係形成於該散熱板及半導體晶片上、 =面上，並充填於散熱板之開口與晶片間之間隙，以及♦ 之通孔開孔的孔壁；至少—線路層，係形成於該絕 、、象層上，且該線路層係可藉由形成於該絕 導 t:=r該半導體晶片；複數導電通孔，婉 mir絕緣層中’用以電性連接在該絕緣層兩側 增層結構，並可於該半導體裳置之外緣線路表面；= 兀件，以供該半導體裝置得以與外部電子裝置作電性連 接；再者’該線路層及線路增層結構係可與該散熱 藉以提供半導體裝置較佳之電性及散熱品質。 ,、因此，本發明之具有晶片埋入基板：貝覆晶封裝結構’ 係以散熱板作為半導體裝置之加強材與散熱導體，以提供 良好之散熱性及支撐結構’可視實際需求設計該電路板為 上下具不同線路層數之非對稱結構，亦可藉該散熱板以作 為半導體元件之散熱途徑及承载件，以提供良好之命性功 能及散熱功能。此外，本發明中係可將主動式晶片:被動 18109 8 1249231 嵌埋於通孔開孔中，有效利用基板空間，且不致$ nt佈局二同時，該半導體裝置中亦結合有晶片與： 〜¥ =構’藉以整合晶片承載件之製造與晶片構裝技 術’俾簡化半導體業者製程與界面整合問題。 【實施方式】 以下稭由特$的具體實施例說明本發明之實施方 二=技藝之人士可由本說明書所揭示之内容輕易地 午X日之其他優點及功效。本發㈣可藉由1他不 =體實施例加以施行或應用，本說明書中的各項^ :基於不同的觀點與應用，在不_本發明之'；= 各種修制5與變更。 f下進订 請參閱第1圖，係為本發明之具有 晶封裳結構第-實施例之剖面示意圖。 彳基板之復 ，圖所不’該具有晶片埋入基板之覆晶封裳結 一散熱板ίο，該散熱板1〇具有 ° '、匕 _及通孔開孔120 ;至少—半導有：曰數；；其表面之開口 散熱板1。之開口 100中；二!:二11，係收納於該· ㈣及半導體晶片u上、下=，12、,，係_^^ 之開口 100,以及通孔開孔12:的孔壁『一充：於散熱板10 分別形成於該絕緣層12上、下茅 :路層131，係 係可藉由形成於該絕緣層12中：線路層131 至該半導體wn;複數導電通=4、，:3^電性連接 通孔開孔no具有充填絕緣層12中，用以^於佈設在該 該絕緣層12上、下表面上之線路層ΐ3ι。电導接形成於 18109 9 1249231 該散熱板Η)，係具有一第一表自心及與該第―表面 他相對之第二表® 10b，以及複數貫穿該散熱板1〇之第 一及弟二表面10a、10b之開口 1〇〇，且該些開口 i⑼中至 少具有-開口 _彳供後續收納半導體晶片u。該散献板 10係由具導熱性及高硬度之金屬材質所組成，例如金屬 銅’銅合金，金屬！呂，銘合金等材料製成，此外，該散熱 板10亦可為具散熱性及不易彎曲變形之陶究材料，例如、、， 氮化紹或二氧化二紹等製成’主要係提供半導體農置於製 程中良好之結構強化支撐特性與熱傳導特性。 & 該半導體晶片11具有一第一表面lla及與該第一表 面lla相對之第二表面llb，其收納於該散熱板1〇之開口 100中，且该半導體晶片n之第一表面lla上具有多數電 墊110。該半導體晶片u係可為被動式晶片，例= 毛谷晶片，亦或為主動晶片，例如記憶體晶片（memory)， ASIC (Application Specific Integrated Circuit)晶片等。 泫絕緣層12係形成於該散熱板l o及半導體晶片i j 之第一及第二表面上，並使該絕緣層12得充填於該散熱板 1〇與半導體晶片π間之間隙，以及散熱板1〇之通孔開孔 12〇的孔壁，以覆蓋住該散熱板10及半導體晶片11。該絕 緣層12係可由例如環氧樹脂（Ep〇xyresin)、聚乙醯胺 (Polyimide)、順雙丁稀二酸醯亞胺/三氮阱（Bismaleimide triazme-based)樹脂、氰酯（Cyanateester)及 ABF(味之素公 司出產之增層材料）等材料所構成。 該線路層131係例如為一圖案化之銅層，其可藉由電 10 18109 1249231 2、=鑛、物理或化學沈積等方切成 上，而對應於接置在半導體晶片 巴，、彖層】2 之絕緣層上之線路層丨31係可藉c接塾-側 如導電盲孔或凸塊以電性連接電結構心例 連接墊m，俾供收納於該散 之U生 得以藉由該線路層】31作直接之带地中之+導體晶片Η 導路徑，進而描# 书I生延伸，以縮短電性傳 夺塔k進而鈇較佳電性功能。同 上之線路層⑶亦可藉由導電結構132= ^絕_ U =，以藉由該散熱板10作為接地件以提供較二::熱板. 提供一良好之熱傳導路I構132與線路層⑶進一步 ❹電通孔14係穿過充填於該通孔開孔⑽中之絕 、-’藉Μ電性連接形成於該絕 線路層131。 曰“不间表面上之 覆晶：；圖:其係為本發明之具有晶片埋入基板之 大致二例之剖面示意圖。其與第-實施例· 術以在第在於第二實施例中係利用線路增層技 構，丄:卜:：Γ層及線路層上形成咖 之線路結構。表面形成防銲層，藉以保護覆蓋其下 括晶片埋入基板之覆晶封裝結構係包 開孔220;至少气放熱板20具有多數開口 200及通孔 之開口咖内；上體晶片2:，係收納於該散熱板20 、、’巴緣層22，係形成於該散熱板20及半 11 18109 1249231 導體曰曰片 1 曰曰 上、下表面上，並充填於散熱板20之開孔200 開口 200與半導體晶片21間之間隙，以及散熱板20之通 孔開孔220的孔壁；一線路層231，係分別形成於該絕緣 層 2 2 卜、丁主 、面上，且該線路層23 1係可藉由形成於該絕 ^ 22中之‘電結構232以電性連接至該半導體晶片 21 ;複數導電通孔24，係形成於充填在該通孔開孔220内 ^緣層22中’用以電性導接形成於該絕緣層22上、下 之線路層231 ;至少一線路增層結構25，係形成於 可且該線路增層結構25係 J书丨生連接至該線路層231 〇 另外，於最外緣之線路增層結構25纟面復可形成一 =二並令該防銲層26形成有複數開孔以外露出部 二層結構25之電性連接塾250部分，俾供後續得 亍）連㈣250上設置導電元件27(如第3圖所 透過”=收納於該散熱板2()中之半導體晶#21得以 線路層231、線路增層結構”及導電 件2 7而與外界作電性車技 側择心y f包&連接，例如’在該半導體裝置之一 側係了供一例如為覆晶 銲錫封粗4入反 飞千蛉版日日片28之電子元件透過 鮮錄材科或金屬凸塊等導電元 增；S| 7 s %性連接至該線路 曰層、、、。構25,而在該半導體裝 金屬凸塊等導電元件植設鮮球或 卩裝置作電性連接。 该散熱板20係具有多數貫穿 孔開孔220,且i中至!； t胃及通 ,〇1 中至少一開口 200係用以收 片21，其餘開孔22〇係可供 射—粗曰曰 ^电通孔24。該散熱板 18109 12 1249231 =係人由具導熱性及高硬度之金屬材料，例如金屬銅，銅合 土屬！呂，銘合金等材料製成，此外，該散熱板別亦可 散熱f不易·f曲變形之陶莞材料，例如，氮化紹或三 ，化一鋁等製成’主要係提供製程中良好之結構強化支撐 4寸性與熱傳導特性。 该半導體晶片21係收納於該散熱板20之開口 200 盡雕t該半導體^ 21上具有多數電性連接墊训。該半 ::片2“系可例如為電容晶片等被動式晶片，或例如為 心思組晶片（memory)或繼晶片等主動式晶片。 /、邑、，彖層22係形成於該散熱板2〇及半導體晶片幻 ttrt並使該絕緣層22得以充填於該散熱板之開 2 〇 〇與晶片21間之間隙，以敕邮七 半導體晶片21。 體包覆住該散熱板20及 ^路層231係例如為一圖案化之銅層，其可藉由電 、·又、無笔鍍、物理或化學沈積等方式形成於該絕緣層U 上，而對應於接置在半導體晶K !曰$ 今妨^ 片21具電性連接墊210 —側 之、線路層231係可藉由複數導電結構加， 目孔或凸塊以電性連接至該半導體晶片η之電 性連接塾210,俾供钱於該散熱板2()巾μ :以藉由該線路層23!作直接之電性延伸，以縮= —路徑’進而提較佳電性功能。同時，接 上之線路層231亦可藉由導電結構232 蛀緣層 2。’以藉由該散熱板2。作為接地件以提供5=板 另可透過該散熱㈣、導電結構232與線路層23ι進力:步 18109 13 1249231 提供一良好之熱傳導路徑。 么该導電通孔24係穿過充填於該通孔開孔22〇中之絕 緣層22，藉以電性連接形成於該絕緣層22不同表面上之 線路層23!。該線路增層結構25，係形成於該絕緣層22 /泉路層231上，其包括有絕緣層25】，疊置於該絕緣 a ^251上之線路層252，以及穿過該絕緣層以電性連 接4線路層252之導電結構253(例如導電盲孔）。而在該線 =增層結構25之最外表面之線路層上則形成有複數電性 处接墊250’用以提供植置多數導電元件27，於線路增層 :=一侧之導電元件27可供接置電子元件，例如覆晶 LΪ版曰曰片28 ’以供該覆晶式半導體晶片28藉由該線 g每結構25電性連接至該線路層231及該半導體晶片 ^ L而在該線路增層結構2 5另—侧外表面上復植設有多數 '电兀件27 ’俾供該半導體裝置得以與外部電子裝置電性 首另外，該線路增層結構25亦可透過導電結構253而 該線路層231及散熱板，藉以透過散熱板20、影 路增層結構25、绫踗；s b道+ —从 ’ 散熱途徑。 策路層231及導電兀件W而提供一良好 路并可形成同時整合有散熱板、半導體晶片、潮 孔=孔(件之半導體裝置’並得以提供收納於該遥 開之體日日日片透過該散熱板較大的外表面積，該錄 構中之線路層’以及植設於線路增層結構外表面 H件所形成的散熱路徑而將其運作產生的熱量有效 18109 14 1249231 =遞=外界。此外，可提供後續接置於導電元件上之外部 電子裝置藉由該導電元件，線路增層結構，導電通孔，線 路層，以及導電元件❿電性連接至外部裝i ,同時另可藉 由°亥線路增層結構，散熱板，以及該些導電元件所構成之 散熱路徑將其運作產生的熱有效傳 遞至外界。 另相較於先月ί』技術，本發明之具有晶片埋入基板之覆晶 封j結構，係以散熱板以作為該半導體裝置之加強材盥散 熱導體，俾提供該半導體裝置良好之散熱性及支撐結構， 因此，可視實際需求設計該電路板為上下具不同線路層數 構’亦可藉該散熱板以作為半導體元件之：熱 二ί ’以提供良好之電性功能及散熱功能，並不 致影響線路之佈局。 中，：二:：本發明之具有晶片埋入基板之覆晶封裝結構 等）承載:爲晶片（包括主動式晶片及被動式晶片 ，且將半導體晶片收納於散熱板之開孔中，有 二利=基板空間’同時本發明係以散熱板作爲晶片承載 :=需於電路板上增設散熱元件，俾可簡化半導體1 :路板較大的面積’線路增層結構* 日卩及琶路板外表面之導電元件（例如，鲜球， 二 所形成的散熱路徑而將鑲埋於電路板結 者= 時產生的熱量有效傳遞至外界。再 線路增層製程，於鑲埋有半 "，、板上下表面形成具多層線路層之結構，藉以提:半導 18109 15 1249231 體晶片直接向外部作電性延伸。 係以本發明之具有晶片埋人基板之覆晶封I结構， 二放熱板以作為該半導體裝置加強材與散熱導體，以提 熱性及支撐結構，因此，可視實際需求設計該 $路板為上下具不同線路層數之料稱結構，亦 熱板以作為半導體元件之散献 9 ^ ^ ^ ^ 政…述位及承載件，以提供電路 明^ 5 ¥具有良好之電性功能及散熱功能，此外，本發 =可將主動式晶片或被動式晶片嵌埋於通孔開孔中， /、電路板結構厚度，且不致影響電路扳表面線路之佈 二二了Λ導：裝置中亦結合有晶片與線料^ ::二曰片承载件之製造與晶片構裝技術，俾簡化半導 月豆業者‘程與界面整合問題。 ι貝知例僅為例示性說明本發明之原理及1功 效’而非用於限制本發明。任何熟習此項技藝之;;士 在不違背本㈣之精神及範訂，對上述實施例進雜 改。因此本發明之權利保護範圍，應如 利 圍所列。 τ月寻利乾 【圖式簡單説明】 〃第1圖係為本發明之具有晶片埋入基板之覆处 構第一實施例之剖面示意圖； 、、° 第2圖係為本發明之具有晶片埋入基板之覆晶士 構第二實施例之剖面示意圖；以及 衣、、，口 第3圖係為本發明之具有晶片埋入基板之覆晶 構植設有導電元件與接置電？元件之剖面示意圖。、'。 18109 16 1249231 【主要元件符號說明】 10、20 散熱板 100 ^ 200 開口 10a、11a 第一表面 10b 、 lib 第二表面 11、21 半導體晶片 110 、 210 電性連接墊 12、22、51 絕緣層 120 ^ 220 通孔開孔 131 、 231 線路層 132 、 232 導電結構 14 > 24 導電通孔 250 電性連接墊 252 線路層 253 導電結構 25 線路增層結構 26 防銲層 27 導電元件 28 覆晶式半導體晶片 17 18109The purpose of the present invention is to provide a layout flexibility in which the wafer is embedded in the substrate, "configuration", and the number of semiconductor elements to be laid. θ plus line W. The purpose of the present invention is to provide a flip chip package structure, which can simultaneously bury the substrate and manufacture the wafer carrier and the wafer 7 18109 1249231 package f standard to simplify the semiconductor industry process. Integration with the interface. A further object of the present invention is to provide a human base having a wafer embedded in a plate thereof: a package: a hair "dew; a heat dissipation plate having a buried hole; at least a half of a guide, a nanometer, a The limbs are stored in the heat sink = (5), , and ", formed on the heat sink and the semiconductor wafer, on the surface, and filled in the gap between the opening of the heat sink and the wafer, and a hole wall of the through hole opening; at least a circuit layer formed on the insulating layer, the image layer, and the circuit layer can be formed on the semiconductor wafer by the extruding t:=r; the plurality of conductive vias , 婉 mir insulating layer 'used to electrically connect the two sides of the insulating layer to build a layer structure, and the semiconductor can be placed on the outer edge of the line surface; = 兀, for the semiconductor device to be used with external electronic devices Electrical connection; in addition, the circuit layer and the line build-up structure can be combined with the heat dissipation to provide better electrical and heat dissipation qualities of the semiconductor device. Therefore, the present invention has a wafer embedded substrate: a flip-chip package structure uses a heat sink as a reinforcing material and a heat dissipating conductor of the semiconductor device to provide good heat dissipation and support structure. The circuit board can be designed according to actual needs. In order to provide an asymmetric structure with different number of circuit layers, the heat dissipation plate can also be used as a heat dissipation path and a carrier for the semiconductor component to provide a good life function and a heat dissipation function. In addition, in the present invention, the active wafer: passive 18109 8 1249231 can be embedded in the through-hole opening, and the substrate space can be effectively utilized, and the semiconductor device is also combined with the wafer and the: = "To integrate the fabrication and wafer fabrication technology of wafer carriers" to simplify semiconductor industry process and interface integration issues. [Embodiment] The following description of the embodiment of the present invention is made by the specific embodiment of the present invention. The person skilled in the art can easily use the other contents and effects of the present invention by the contents disclosed in the present specification. The present invention (4) can be implemented or applied by the embodiment of the present invention, and the various items in the present specification are based on different viewpoints and applications, and are not in the present invention; F downward ordering Referring to Fig. 1, a cross-sectional view of a first embodiment of the present invention having a crystal sealing structure is shown. The substrate is not covered, and the wafer has a wafer embedded in the substrate, and the heat sink 1 has a '°, a 匕 _ and a through hole 120; at least the semi-conductive has: Number of turns;; the opening of the surface of the heat sink 1. In the opening 100; two!: two 11, is stored in the (four) and the semiconductor wafer u upper, lower =, 12,, the opening _ ^ ^ opening 100, and the through hole opening 12: the wall of the hole The heat dissipation plate 10 is respectively formed on the insulating layer 12 and the lower layer: the road layer 131, and the system can be formed in the insulating layer 12: the circuit layer 131 to the semiconductor wn; the plurality of conductive wires = 4, The 3^ electrical connection via opening no has a filling insulating layer 12 for routing the wiring layer ΐ3ι on the upper surface and the lower surface of the insulating layer 12. The electric conduction joint is formed at 18109 9 1249231, and has a first watch self-centered and a second watch® 10b opposite to the first surface, and a plurality of first and second brothers running through the heat sink 1 The openings of the two surfaces 10a, 10b are 1 〇〇, and at least the openings i (9) have openings - for subsequent storage of the semiconductor wafer u. The slab 10 is composed of a metal material having thermal conductivity and high hardness, such as a metal copper 'copper alloy, metal! It is made of materials such as Lu, Ming alloy, etc. In addition, the heat dissipation plate 10 can also be a ceramic material which has heat dissipation and is not easily bent and deformed, for example, , and is made of a nitride system or a second semiconductor. The agricultural structure is placed in the process to strengthen the support characteristics and heat transfer characteristics. The semiconductor wafer 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a, and is received in the opening 100 of the heat dissipation plate 1 and on the first surface 11a of the semiconductor wafer n. There are a plurality of pads 110. The semiconductor wafer u can be a passive wafer, for example, a brown wafer, or an active wafer, such as a memory chip, an ASIC (Application Specific Integrated Circuit) wafer, or the like. The insulating layer 12 is formed on the first and second surfaces of the heat dissipation plate lo and the semiconductor wafer ij, and the insulating layer 12 is filled in a gap between the heat dissipation plate 1 and the semiconductor wafer π, and the heat dissipation plate 1 The through hole of the through hole 12 is bored to cover the heat sink 10 and the semiconductor wafer 11. The insulating layer 12 may be, for example, an epoxy resin (Ep〇xyresin), a polyimide, a bissuccinimide triazame-based resin, or a cyano ester (Cyanateester). And ABF (additive materials produced by Ajinomoto Co., Ltd.) and other materials. The circuit layer 131 is, for example, a patterned copper layer which can be cut by electric 10 18109 1249231 2, = mineral, physical or chemical deposition, etc., and corresponds to the semiconductor wafer, the germanium layer The circuit layer 丨31 on the insulating layer of the second layer can be electrically connected to the electrical structure by using a connection hole-side such as a conductive blind hole or a bump to connect the pad m. The circuit layer] 31 is used as a direct conduction path of the + conductor wafer in the ground, and then extends to shorten the electrical transmission tower k and further optimize the electrical function. The same circuit layer (3) can also provide a better thermal conduction path I structure 132 and the circuit layer by using the heat dissipation plate 10 as a grounding member by using the heat dissipation plate 132 as a grounding member. (3) Further, the electric through hole 14 is formed in the absolute circuit layer 131 through the electrical connection filled in the through hole (10).曰 "The flip-chip on the surface: Figure: It is a schematic cross-sectional view of a substantially two-piece substrate with a wafer embedded in the present invention. It is in the second embodiment. By using the line-adding layer structure, 丄: ::: Γ layer and the circuit layer form a line structure of the coffee. The surface forms a solder resist layer, thereby protecting the flip-chip package structure opening 220 covering the underlying wafer embedded in the substrate. At least the gas heat release plate 20 has a plurality of openings 200 and openings therein; the upper body wafer 2: is received in the heat dissipation plate 20, and the 'bar edge layer 22 is formed on the heat dissipation plate 20 and the half 11 18109 1249231 The upper and lower surfaces of the conductor cymbal 1 are filled in the gap between the opening 200 of the heat sink 20 and the semiconductor wafer 21, and the hole wall of the through hole 220 of the heat sink 20; The layer 231 is formed on the insulating layer 2, the main surface, and the surface layer 23 1 is electrically connected to the semiconductor wafer by the electrical structure 232 formed in the insulating layer 22 21; a plurality of conductive vias 24 are formed in the via opening 220 of the via hole ^ In the edge layer 22, a circuit layer 231 is formed on the insulating layer 22 for electrical conduction; at least one line build-up structure 25 is formed on the line-enhanced structure 25 In addition, the circuit layer 231 〇 〇 , 于 于 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路250 parts, for subsequent succession) (4) 250 is provided with a conductive element 27 (as shown in Fig. 3) = semiconductor crystal #21 received in the heat sink 2 () can be provided by the circuit layer 231, the line build-up structure" The conductive member 27 is connected to the outside of the electric vehicle technology side yf package & for example, 'on one side of the semiconductor device is provided for one, for example, a flip chip solder seal 4 into the anti-flying version of the day The electronic component of the sheet 28 is increased by a conductive element such as a fresh recording material or a metal bump; S|7 s% is connected to the wiring layer, and the structure 25, and the conductive component such as the metal bump is implanted in the semiconductor The fresh ball or the cymbal device is electrically connected. The heat dissipation plate 20 has a plurality of through hole openings 220, and i is in the middle! t stomach and pass, at least one opening 200 in the 〇1 is used to receive the piece 21, and the remaining openings 22 are available for shooting - rough 曰曰^ electric through hole 24. The heat sink 18109 12 1249231 = the person has heat conduction Metal materials with high hardness and high hardness, such as metal copper, copper and earth genus! Lu, Ming alloy and other materials. In addition, the heat sink can also dissipate heat. Shao or San, Huayi Aluminum, etc. are mainly made to provide good structural strengthening support 4 inch and heat conduction characteristics in the process. The semiconductor wafer 21 is housed in the opening 200 of the heat sink 20 to sculpt the semiconductor ^ 21 Has a majority of electrical connection training. The half:: sheet 2" may be, for example, a passive wafer such as a capacitor wafer, or an active wafer such as a memory or a wafer. The /, 邑, 彖 layer 22 is formed on the heat sink 2 And the semiconductor wafer ttrt and the insulating layer 22 is filled in the gap between the opening 2 of the heat sink and the wafer 21 to cover the semiconductor wafer 21. The heat sink 20 and the layer 231 are covered. For example, it is a patterned copper layer which can be formed on the insulating layer U by electricity, and also without pen plating, physical or chemical deposition, etc., and corresponds to the semiconductor crystal K 曰The circuit board 231 is electrically connected to the electrical connection port 210 of the semiconductor wafer η by means of a plurality of conductive structures, and the mesh holes or bumps are electrically connected to the semiconductor chip η. In the heat sink 2 () towel μ: by the circuit layer 23! for direct electrical extension, to reduce the path - and then improve the electrical function. At the same time, the connected circuit layer 231 can also borrow From the conductive structure 232, the edge layer 2' is used to provide a 5= plate through the heat sink 2. The heat dissipation (four), the conductive structure 232 and the circuit layer 23ι push force: step 18109 13 1249231 provides a good heat conduction path. The conductive through hole 24 passes through the insulating layer 22 filled in the through hole opening 22, thereby Electrically connecting the circuit layer 23 formed on different surfaces of the insulating layer 22. The circuit build-up structure 25 is formed on the insulating layer 22/spring layer 231, and includes an insulating layer 25] The wiring layer 252 on the insulating layer a 251, and the conductive structure 253 (for example, a conductive blind via) passing through the insulating layer to electrically connect the 4 wiring layer 252. On the outermost surface of the line = buildup structure 25 A plurality of electrical pads 250' are formed on the circuit layer for providing a plurality of conductive elements 27, and the conductive elements 27 on the side are connected to the electronic components, such as a flip chip. The sheet 28 ′ is used for the flip-chip semiconductor wafer 28 to be electrically connected to the circuit layer 231 and the semiconductor wafer by the line g, and the other side of the line build-up structure 25 Planted with a majority of 'Electrical Parts 27' for the semiconductor device to be mounted with external electronics In addition, the line build-up structure 25 can also pass through the conductive structure 253 and the circuit layer 231 and the heat dissipation plate, thereby passing through the heat dissipation plate 20, the shadow path build-up structure 25, the 绫踗; sb track + - from the 'heat dissipation path The routing layer 231 and the conductive member W provide a good path and can be formed while integrating a heat sink, a semiconductor wafer, a tidal hole = a hole (a semiconductor device of the piece) and can be provided in the body of the remotely opened day The sheet transmits the heat generated by the operation of the circuit layer in the recording layer and the heat dissipation path formed by the H piece on the outer surface of the line build-up structure through the large outer surface area of the heat sink. 18109 14 1249231 = hand = external. In addition, an external electronic device that is subsequently placed on the conductive element can be provided by the conductive element, the line build-up structure, the conductive via, the circuit layer, and the conductive element are electrically connected to the external device, and at the same time The structure of the layered structure, the heat sink, and the heat dissipation path formed by the conductive elements effectively transfer the heat generated by the operation to the outside. In addition, compared with the first month 』 technology, the structure of the overlying crystal sealing j with a wafer embedded in the substrate is a heat dissipating plate as a reinforcing material and a heat dissipating conductor of the semiconductor device, and provides good heat dissipation of the semiconductor device. Support structure, therefore, the circuit board can be designed according to actual needs to have different circuit layer numbers. It can also be used as a semiconductor component by the heat sink: to provide good electrical function and heat dissipation function. Affect the layout of the line. Medium: two:: the flip chip package structure with a wafer embedded in the substrate of the present invention, etc.) is a wafer (including an active wafer and a passive wafer, and the semiconductor wafer is housed in the opening of the heat dissipation plate, and there is a benefit = Substrate space 'At the same time, the present invention uses a heat sink as a wafer carrier: = need to add heat dissipating components on the circuit board, which can simplify the semiconductor 1: large area of the road board 'line buildup structure * outside the day and outside the board The conductive elements on the surface (for example, the fresh balls, the heat dissipation path formed by the two, the heat generated when embedded in the circuit board is effectively transmitted to the outside. The circuit is further layered and embedded in the semi-quot; The upper and lower surfaces of the board are formed with a structure of a plurality of circuit layers, so as to: the semiconductor wafer is electrically extended directly to the outside. The invention has the above-mentioned structure of the wafer-embedded substrate with the wafer embedded in the substrate, and the second heat release plate As the reinforcing material and the heat dissipating conductor of the semiconductor device, the heat-reducing property and the supporting structure are designed. Therefore, the $-way plate can be designed according to actual needs, and the hot plate is used as the material structure of the different circuit layers. Dissipation of semiconductor components 9 ^ ^ ^ ^ political ... description and carrier to provide a circuit with a good electrical function and heat dissipation function, in addition, this issue = can be embedded in active or passive wafers In the opening of the through hole, /, the thickness of the circuit board structure, and does not affect the circuit surface of the circuit board. The device also incorporates the fabrication and wafer of the wafer and the wire material. Constructing technology, simplifies the problem of 'transformation and interface integration' of the semi-conducting peas. The examples are merely illustrative of the principles and functions of the present invention, and are not intended to limit the invention. Any skill in the art; The above-mentioned embodiments are modified without violating the spirit and scope of this (4). Therefore, the scope of protection of the present invention should be listed as the right. τ月寻利干 [Simple description] 〃第1 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view showing a first embodiment of a substrate having a wafer embedded in a substrate; and FIG. 2 is a cross section of a second embodiment of the cladding of the present invention having a wafer embedded in a substrate. Schematic; and clothing,,, mouth, Figure 3 A schematic cross-sectional view of a flip-chip structure having a wafer embedded in a substrate of the present invention, wherein the conductive element and the connected electrical element are provided., '. 18109 16 1249231 [Description of main components] 10, 20 heat sink 100 ^ 200 opening 10a 11a first surface 10b, lib second surface 11, 21 semiconductor wafer 110, 210 electrical connection pads 12, 22, 51 insulating layer 120 ^ 220 through hole opening 131, 231 circuit layer 132, 232 conductive structure 14 > 24 Conductive via 250 Electrical connection pad 252 Circuit layer 253 Conductive structure 25 Line buildup structure 26 Solder mask 27 Conductive component 28 Flip-chip semiconductor wafer 17 18109

Claims (1)

1249231 、申請專利範圍： 種具有晶片埋入基板之覆晶封裝結構，係包括： 一具複數貫穿開口及通孔開孔之散熱板； 至少一收納於該散熱板之開口内之半導體晶片； —形成於該散熱板及半導體晶片上、下表面上並充 填於散熱板之開口與晶片間之間隙與通孔開孔之孔壁 的絕緣層； v从々、成、吧琢層上之線路層，且該線路層係 成於該絕緣層中之導電結構以電性連接至該 半導體晶片；以及 複數形成在該通孔開孔内之絕緣層中之導電通 孔，用以電性連接在該絕緣層兩側之線路層。 2.=請範圍第1項之具有晶片埋入基板之覆晶封裝 、广二中，該散熱板部分開口係用以收納半導體晶 月，邛为開孔係用以形成導電通孔。 .11 圍弟1項之具有晶片埋入基板之覆晶封裝 結構’其中，該散熱板之材質係為金屬及㈣之其中ΐ 者。 18 1249231 結構，其中，★玄本道 \ 構而與線路層電ΖΓ。電料㈣絲過導電結 請::㈣圍第】項之具有晶片埋入基板之覆晶封裝 一者/、料電結構為導電盲孔及導電凸塊之其中 8. =1請=範圍第1項之具有晶片埋入基板之覆晶封裝 熱板。糸了精由導電結構以導接至該散 9. 一種具有晶片埋入其 一且㈣… 曰封裝結構，係包括·· · 具妓數貝穿開口及通孔開孔之散熱板； 至>、一收納於該散熱板之開σ 殖於=成於該散熱板及半導體晶片上、下表面曰上片並充 的絕、;層…’口與晶片間之間隙與通孔開孔之孔壁 、”'，豕瑨上之線路層，且該線路層係 J猎由形成於該絕緣層中之導 半導體晶片； 守包、、、口構以电性連接至該 孔， 構， 成有 ==該通孔開孔内之絕緣層中之導電通 电性連接在魏緣層兩側之線路層； 至少-形成在該絕緣層及線路層上之線路增層結 且该線路增層結構係可電料接至該線路層·， 佈覆於該㈣增層結構上之㈣層，錢 開口以外以料線料層結構； 7 m線路增層結構外緣表面形成有複數個導電 18109 19 1249231 元件；以及 至少一電子裝置與增層結構外緣表面之複數個導 笔元件電性連接。 10·如申請專利範圍第9項之具有晶片埋入基板之覆晶封 裝結構，其中，該線路增層結構包括有一絕緣層、疊置 於該絕緣層上之線路層，以及提供該線路層電性連接之 導電結構。 11. ^申請專利範圍第9項之具有晶片埋入基板之覆晶封 裝結構，其中，該散熱板部分開口係用以收納半導體晶 片’部分開孔係用以收納導電通孔。 以申請專利範圍第9項之具有晶片埋人基板之覆晶封 裝結構，其中，該散熱板之材質係為金屬及陶瓷之其 —者。 〆、 1申請專利第9項之具有晶片埋人基板之覆晶封 袁結構，其中，該半導體晶片係可選擇 被動式晶片。 巧勤式曰曰片/ 範圍第、9項之具有晶片埋人基板之覆晶封 、 ’、中’ 3半導體晶片具有多數電性連接塾。 .:申請專利範圍第i 4項之具有晶片埋 裝結構，其中，該半導 反之復曰曰封 結構而與線路層電性連接。$陸連接墊係透過導1 16·如申請專利範圍第9項之且右b P 士播“ 片埋入基板之覆晶封 其中，該導電結構為導電盲孔及導電凸塊之, 18109 20 1249231 丨7專利範圍第9項之具有晶片埋入基板之覆晶封 其中’該線路層係可藉由導電結構以導接至該 18·如申請專利範圍第9 裳結構，其中，該電二置片埋入基板之覆晶封 、置係可為一半導體晶片。1249231, the scope of the patent application: a flip chip package structure having a wafer embedded in a substrate, comprising: a heat dissipation plate having a plurality of through openings and through hole openings; at least one semiconductor wafer received in the opening of the heat dissipation plate; An insulating layer formed on the upper and lower surfaces of the heat dissipation plate and the semiconductor wafer and filled in the gap between the opening of the heat dissipation plate and the gap between the wafer and the hole of the through hole; v. The circuit layer on the layer of the 々, 、, 琢And the circuit layer is electrically connected to the semiconductor wafer in the conductive layer; and a plurality of conductive vias formed in the insulating layer in the via hole for electrically connecting The circuit layer on both sides of the insulation layer. 2. = Please cover the flip chip package with the wafer embedded in the substrate in the first item, and the second part of the heat dissipation plate is used for accommodating the semiconductor crystal, and the opening is for forming the conductive via. .11 A flip-chip package structure in which a wafer is embedded in a substrate, wherein the material of the heat dissipation plate is metal and (4). 18 1249231 structure, in which ★ Xuan Ben Road \ structure and circuit layer electricity. The electric material (4) wire through the conductive junction:: (4) the fourth item of the chip-embedded substrate with the wafer embedded in the substrate /, the material electrical structure is the conductive blind hole and the conductive bump. 8. =1 please = range A flip-chip package hot plate having a wafer embedded in a substrate.精 精 由 导电 导电 导电 导电 导电 导电 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ; an opening σ contained in the heat sink is formed on the heat sink and the semiconductor wafer, and the upper surface is filled and filled; the layer...the gap between the mouth and the wafer and the opening of the through hole a hole wall, "', a circuit layer on the upper layer, and the circuit layer J is guided by a semiconductor wafer formed in the insulating layer; the package, the mouth, and the mouth are electrically connected to the hole, and Having == the conductive layer in the insulating layer in the via hole is connected to the circuit layer on both sides of the Wei edge layer; at least - the line buildup layer formed on the insulating layer and the circuit layer and the line buildup structure The electric material is connected to the circuit layer, and the (four) layer is covered on the (four) build-up structure, and the material layer structure is formed outside the money opening; the outer surface of the 7 m line build-up structure is formed with a plurality of conductive layers 18109 19 1249231 component; and a plurality of at least one electronic device and the outer peripheral surface of the buildup structure The device is electrically connected. The chip-on-package structure having a wafer embedded in a substrate according to claim 9 wherein the circuit build-up structure comprises an insulating layer and a circuit layer stacked on the insulating layer. And a flip-chip package structure having a wafer embedded in a substrate, wherein the heat sink is partially open for receiving a semiconductor wafer. The utility model relates to a flip chip package structure with a wafer buried substrate according to claim 9 , wherein the material of the heat dissipation plate is metal and ceramic. 〆, 1 patent application The nine-layered crystal-covered structure of the wafer-embedded substrate, wherein the semiconductor wafer can be selected as a passive wafer. The smart-type enamel/range, the ninth item has a wafer-embedded substrate, The '3 semiconductor wafer has a plurality of electrical connections. . . : Patent application No. i 4 has a wafer embedded structure, wherein the semiconductor is reversed and the structure is closed. Electrically connected to the circuit layer. $ land connection pad through the guide 1 16 · as claimed in the scope of the ninth item and the right b P 士 "" is embedded in the substrate, the conductive structure is a conductive blind hole and Conductive bump, 18109 20 1249231 丨7 Patent scope No. 9 has a wafer-embedded substrate embedded in a substrate, wherein the circuit layer can be guided to the 18 by a conductive structure. The structure, wherein the electric two-chip embedded in the substrate is covered by a crystal, and the system can be a semiconductor wafer. 18109 2118109 21
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CN101937899B (en) * 2010-05-17 2013-04-17 日月光半导体制造股份有限公司 Semiconductor packaging structure and packaging technology thereof
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TWI739027B (en) * 2018-08-30 2021-09-11 恆勁科技股份有限公司 Core structure of flip chip package substrate and preparation method thereof

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