TWI283055B - Superfine-circuit semiconductor package structure - Google Patents

Superfine-circuit semiconductor package structure Download PDF

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Publication number
TWI283055B
TWI283055B TW094100802A TW94100802A TWI283055B TW I283055 B TWI283055 B TW I283055B TW 094100802 A TW094100802 A TW 094100802A TW 94100802 A TW94100802 A TW 94100802A TW I283055 B TWI283055 B TW I283055B
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TW
Taiwan
Prior art keywords
layer
insulating layer
ultra
circuit
line
Prior art date
Application number
TW094100802A
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Chinese (zh)
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TW200625575A (en
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
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Priority to TW094100802A priority Critical patent/TWI283055B/en
Publication of TW200625575A publication Critical patent/TW200625575A/en
Application granted granted Critical
Publication of TWI283055B publication Critical patent/TWI283055B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

A superfine-circuit semiconductor package structure includes a carrier board; a support board having at least one opening and mounted on the carrier board; at least one semiconductor chip received in the opening of the support board and mounted on the carrier board; at least one circuit built-up structure electrically connected to the semiconductor chip and formed on the support board and the semiconductor chip, wherein the circuit built-up structure includes at least two insulation layers, a plurality of conductive vias formed in the lower insulation layer, and a circuit layer electrically connected to the conductive vias and flush with a surface of the upper insulation layer; and a plurality of conductive elements mounted to the circuit built-up structure, such that the semiconductor chip can be electrically connected to an external device by the circuit built-up structure and the conductive elements.

Description

1283055 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種超細線路半導體封裝結構，尤指 種同B寸整合有承載板、半導體晶片與線路結構之 路半導體封裝結構。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semlconductor device)已開發出不同的封裝型態，其中球 栅陣列式（Ball grid array，BGA)為一種先進的半導體封裝 技術，其特點在於採用—基板來安置半導體晶片，並^用 自動對位（Self-aiignment)技術以於該基板背面植置複數個 =狀陣列排列之錫球（s〇lder ball)，使相同單位面積之半 導體晶片承载件上可以容納更多輸人/輸出連接端⑽ 加^^…以付合咼度集積化山^^以也⑽彡之半導體晶片 所需，以藉由此些錫球將整個封裝單元銲結並電性連接至 φ 外部之印刷電路板。 請參閱第1圖，為解決上述問題，一種習知之底穴置 曰曰型球拇陣型式封裝結構（Cavity_d〇wn ball array， C士DBGA) ’係為一種特殊形態的球柵陣列式封裝結構，其 占在於其巾之基板形成有—開口朝下底穴，並將半導體 、幻置方式女置於该底穴之中。此習知之球柵陣列式 封ίΓί10至少包含·· 一基板11、一承載板12、至少一 半卵片1 3、祓數條銲線丨4、一封裝膠體丨5以及複數 錫球16。忒基板11形成有至少一開口 m ;該承載板12 18102 5 1283055 ::合板11的正面上，以使得該基板u的開口⑴ 形成一開口朝下之底穴；於組裝過程中，係將半導體晶, 13以倒置方式安置於基板u的開口⑴中，並將其非電 路面黏結至承載招12，妙、你、仏 ^ 銲線14將半導體 二’進行—鮮線製程，藉以利用 連接墊，接著進 15來完全包覆半;二二泰藉此而形成封裳膠體 +兀王匕伋牛¥脰日日13片和銲線Μ，之後，進 樹’藉此而於基板11的背面上植置複數個錫球16。 置晶型，列式(⑽GA則結構… ,L、衣早兀雖然付以利用該承載板解決其散埶與、庶 敵效果（Shleldlng)，但—般為能夠將㈣ 部印刷電路板，該錫球配置高度必須大於該輝線 度，嚴重影響該基板之佈月枓 斤佔阿 4之佈局雖_ablIlty)與軸配 度，另-方面，由於晶片周圍之線弧密度極 金線不慎觸接產生短路，增加打線作業困難度；再 進打模壓封膠製程時，係將完成佈設晶片置 於一封裝模具中，俾供-環氧樹脂材料注入模4 = 用：包覆該晶片與銲線之封裝膠體，然而，於實際製程; 巍…： 件之設計’故其模穴尺寸與 戶斤差異而造成無法緊密夾固等問題，俟注 入树月曰材料時，容易導致封裝膠體溢膠至該基板表面 但降低該半導體封裝件之表面 污举兮其抬μ % # 又/、夷戒问時更可能 心絲板上“欲植置錫叙銲墊位置，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-fine-line semiconductor package structure, and more particularly to a semiconductor package structure in which a carrier board, a semiconductor wafer, and a wiring structure are integrated with a B-inch. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices (Semlconductor devices) have developed different package types, in which Ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized by The semiconductor wafer is disposed by using a substrate, and a plurality of semiconductor balls arranged in the same array are mounted on the back surface of the substrate by a self-aiigning technique to make a semiconductor wafer of the same unit area. The carrier can accommodate more input/output connections (10) plus ^^... to meet the needs of the semiconductor wafers that are also (10) ,, so that the entire package unit can be soldered by the solder balls. The junction is electrically connected to the printed circuit board external to φ. Referring to FIG. 1 , in order to solve the above problem, a conventional ball-shaped ball array package structure (Cavity_d〇wn ball array, CJ DBGA) is a special form of ball grid array package structure. The base of the towel is formed with an opening facing the lower hole, and a semiconductor, a phantom female is placed in the bottom hole. The conventional ball grid array package comprises at least one substrate 11, a carrier plate 12, at least one half of the egg piece 13, a plurality of wire bonds 4, an encapsulating glue 5, and a plurality of solder balls 16. The substrate 11 is formed with at least one opening m; the carrier plate 12 18102 5 1283055: on the front surface of the plywood 11 such that the opening (1) of the substrate u forms an opening with a downward opening; during assembly, the semiconductor is The crystal, 13 is placed in the opening (1) of the substrate u in an inverted manner, and the non-circuit surface is bonded to the carrier 12, and the solder wire 14 is used to carry out the process of the semiconductor two-on-line process, thereby utilizing the connection pad. Then, enter 15 to completely cover the half; 2nd and 2nd to form the sealant colloid + 兀王匕汲牛¥脰日日13片 and wire bonding Μ, after that, enter the tree 'by this and plant on the back of the substrate 11 Set up a number of solder balls 16. Crystallization type, column type ((10)GA structure..., L, clothing early, although the use of the carrier plate to solve its divergence and enemy effect (Shleldlng), but generally can (4) printed circuit board, the The height of the solder ball must be greater than the height of the glow, which seriously affects the layout of the substrate. Although the layout of the A4 is _ablIlty) and the axis is matched, the other side is inadvertently touched by the arc density around the wafer. The short circuit is generated to increase the difficulty of the wire bonding operation; when the molding process is completed, the laying wafer is placed in a package mold, and the epoxy resin material is injected into the mold 4 =: coating the wafer and welding The encapsulation colloid of the line, however, is in the actual process; 巍...: the design of the piece', so the difference between the cavity size and the household size causes the problem that it cannot be tightly clamped, and when the material is injected into the tree, the encapsulation colloid is likely to overflow. To the surface of the substrate, but to reduce the surface contamination of the semiconductor package, and the surface of the substrate is more likely to be implanted.

體封裝件之電性連接口所·、w 〇 . -¾ + V 連接1，況且，該樹脂材料於注躍時乃 6 18102 1283055 •為-流體，於注入該模穴時將對該完成晶片與基板電性連 接之導線產生模流壓力，若注入速度控制不當時，即合因 該壓力衝擊導線，使導線產生碰觸而發生短路問題，^重 影響該半導體封裝件之生產品質及產品信賴度。 此外，為提供^皆電子產品之需求，並在增層基板不 .斷追求細線路化之情況下’目前細線路製減力係為線寬 ⑹/線距⑻比為20/20微米，其細線路製程技術於使用半 加成’SAP)愈來愈難符合需求，尤其是在l/s㈣微米以 下更是難以精確地完成所需之尺寸精度，且其所花費之成 =。況且’在細線路製程要求下，基板中線路結 接著面將愈來愈小，因此，在形成細線路結構時、， 泉路結構有效貼合於崎層表面，勢必要求保持絕緣 平ΐ性’否則，若無法維持、絕緣層之平整性時， 產口 ι貝堆豐其上之線路層極易產生剝離問題，嚴重 度；例如’在原本已具内層圖案化線路之基i ·;=路增層結構時，必須先在該具内層圖案化線路之 声，妙 、、、、θ W後才此在該絕緣層上形成線路 ^化線Γ際製程中，由於受制基板先前所形成之内 層勢必㈣4凹凸表面影響，將使後_合其上之絕緣 凹凸不；!平之狀況發生，如此，後續在該具 之沒路岛 絕緣層上形成增層線路層時，其所形成 。路層即會受制於該絕緣層 線路層I牛 丁正衣囬之〜音，而導致 離問題了it Γ附於該絕緣層上，嚴重者將造成線路制 、此—t月況對於欲形成細線路結構時，將因線路層 18102 7 1283055 .與絕緣層間之接合面積愈小，而更形嚴重。 . 料，一般半導體裝置之製程，係首先由晶片承載件 製邊業者生產適用於該半導體裝置之晶片承載件，如 =線；：之:复’再將該些晶片承載件交由半導體封 = 以及提供對外導電連接元件等 .衣私取後，方可完成客戶端所需之電子功妒夕主言 置’其間涉及不同萝程業去 b半蛉體裴 -盥半導體封”者有晶片承載件製造業者 牛¥^衣#者），因此於實際製造 有 •且界面整合不易，況且，若客戶端欲須瑣 其牽涉變更與整合層面更是複雜 -:广’ 與經濟效益。 订口而求变更彈性 【發明内容】 雲於以上所述習知姑Μ 技術之缺點，本發明之主要日 美供-種超細線路半導體封裝結構 =要目的係 件之製造與晶片封裝技術之製程，以提二客晶月承載 本發明之再-二=與界面整合問題。 構，俾可形成細線路結構，以 #路^體封裝結 本發明之又—……月认制製程精度尺寸。 構，俾可提供線路4士禮 種超細線路半導體封h 制和 線路結構與絕緣層間良好衣結 衣釭可罪度之品質。 .者力，進而維持 本务明之另一目的儀接租— ::俾得有效逸散半導體晶;:運二 =半導體封裝結 0讀供電磁遮蔽效果，避免受外界電：生之熱量，同 电磁及雜訊之干擾。 8 】8】〇2 1283055 本發明之又再一目的係提供一種超 結構，避免習知半導親製程中，模覆之溢 晶片之導電元件佈設問題 ：：’版 品質及產品信賴度。 “ + ¥體裳置之生產 姓槿為^揭及其它目的，本發明之超細線路半導體封事 、、、口構，主要係包括一承載板；— 衣 係接置於該承载板上；至少—半/'^7 W之支承板’ 載板上並容置料古μ叫曰曰片’係接置於該承 體晶片之線路增層结構，择报士、 ^ 电性連接该半導 上，i中，=σ 〃》成於該支承板及半導體晶片 /、中该線路增層結構係包含有至少二；ρ 數形成於下層絕緣層中之 曰、、、巴、、、彖g，複 電盲孔並盥上^_ 以及一電性連接該導 /、JL智乡巴緣層表面齊平 . 於該線路增層結構上之導電元件1 S，以及複數接置 可藉由導電盲孔以電性連接半導邮該線路增層結構係 半導體晶片直接透過該導電亡孔^片與線路層’俾可供 性延伸。 、目孔人、、泉路層而據以向外作電 整合Ϊ = 線路半導體封褒結構主要係可同時 業，路板)之製程以及半導體晶片封裝作 猎以間化習知半導俨掣 使用習知半導體封裝製程；:；：： =題，同時免除 結構時之打轉式步曰1、— 而电性連接晶月與其承載 製程及成本。同：:9:::::步驟與製妓^ 用複數層之絕緣層，以用之線路增層結構中係使 層部分先在該複數絕緣層之上 σ ， 又置線路層之開口，再於該開口中進—步形 18102 9 1283055 成=牙，亥才夂數絕緣層下層部分之盲孔，如此即得於後續在 .该複數絕緣層之下層部分中形成導電盲孔，在該複數絕緣 2上層#刀开/成線路層，俾使該線路層有效貼附於絕緣 =以維持製程可靠度之品f，並令該線路層表面與該複 H緣層之上層部分表面齊平’以提供後續線路增層結構 相互接置間之平智:料、隹、去 ^進而達到細線路製程之目的。 料=本發明係可提供至少一半導體晶片透過-導熱 •二承載板上，以有效逸散該半導體晶片於運 以：“之熱置，並可藉由該承載板，通常為金屬材質， 以有效提供該半導體裝置電磁遮蔽效果，且該 曰 ;=於:置在該承載板上之金屬板、絕緣板或電路： :的；此外可：=導體裝置之整體厚度，以達輕薄短小 直接m δ」明Γ於該容置有半導體晶片之支承板上 I 夕一堆豐線路結構，俾得以提供半導許曰片 向外作電性延伸，最後，可在該堆疊線路 々且曰曰片 >有多數之導電元件，例如錫球、銲柱或導電。柱々' _設 該，合晶片之構裝結構電性連接至外部裝^。寻’以提供 【實施方式】 為使本發明之目的、特徵及功效 與認同，兹配合詳細揭露及圖式詳加說明2 —=的瞭解 發明可以多種形式實施之，以下所述係為本；；明备然，本 轭例，而非用以限制本發明之範圍，合先敘日^。之幸乂佳貫 請翏閱第2Α至2Η圖’係為本發 封裝結構之製作方法剖面示意圖。月之Κ線路半導體 18102 10 1283055 如第2A圖所示，提供一承載板21，以於該承載板21 上接置一設有間口 220之支承板22，俾供至少一半導體晶 片23接置於該承載板21±並容置於該支承板22之開口 220中。其中該支承板22可為一金屬板、絕緣板或電路板， 且該支承板22形成有至少—貫穿表面之開口，，而該承 載板21係、封閉該支承板開口 22〇之一側以形成一凹部，俾 至夕半導肢日日片23可藉由導熱黏著層24接置於該承 載板21上且容置於該支承板22之開口細中，而使該半 導體晶片23電路面上之電極墊咖得以顯露於該支承板開 所2〇其中’ 5玄支承板22為金屬板時，其可為-金屬材 貝例如銅.、鎂、紹、錄、不錄鋼等金屬或其合金所形成之 上、且之"玄支承板22為絕緣板時，其可為陶竟基板、環 乳樹脂（EpGxyresin)、聚乙㈣㈣yimide)、氰脂咖績 :〇、碳纖維（Carbon flber)、雙順丁稀二酸醒亞胺/三氮 =y職alelmlde tnazme)或混合環氧樹脂與玻璃纖維 =貝所構成；該支承板22為電路板時，其可為一完成前 處理之具線路層之電路板。 如第2B圖所示，於該支承板22及半導體晶片 =形成第-絕緣層251及第二絕緣層况，並使該第— ::層251得以充填至該晶片幻與支承板開口⑽間隙。 質二=絕緣層251及第二絕緣層252係採用不同材 料而；：：：感光性或非感光性材料，抑或-為感光性材 而另為非感光性材料。 如第2C圖所示，先對該第二絕緣層252進行圖案化 18102 11 1283055 製程，以於該第二絕緣層252中形成有複數開口灿。其 中係可藉由曝光、顯影、钱刻等方式，並利 251作為停止層’以在該第二絕緣層252中形成多數開口 252a而外露出部分第一絕緣層251。 如第2D圖所不’復對該第一絕緣層藉由雷射開口 O-er dnH)或電㈣刻（pia_⑽㈣等 …使該晶片23之電極塾23〇外露出該盲孔二 如弟2E圖所示，於該第一絕緣層251及第二 外露表面及電極墊230上形成導電層26,該_: 主要作為後述進行電鍍金屬所需、 該導電層-作為電流導通路徑，以 f在該導電層26上形成金料體結構〜其中; 層26之材質可為金屬或導電高分子材料。 …电 —、、、巴緣層252上表面之金屬導體結構27 弟 :該第二絕緣層252上表面與形成於其開口中:；導： 、、、。構維持平整表面，藉以供後 蜀¥體 :整性，進而得提供細線路製程。其；上維持 ^層251盲孔中之金屬導體結構部分即H ^ ‘絕The electrical connection port of the body package, w 〇. -3⁄4 + V connection 1, and the resin material is 6 18102 1283055 when the injection is a fluid, which will be completed when the cavity is injected The wire electrically connected to the substrate generates a mold flow pressure. If the injection speed is not properly controlled, the wire is struck by the pressure, causing the wire to come into contact and short-circuiting, which affects the production quality and product reliability of the semiconductor package. degree. In addition, in order to provide the demand for electronic products, and in the case where the substrate is not broken, the current fine line reduction is a line width (6) / line spacing (8) ratio of 20 / 20 microns, Fine line process technology is increasingly difficult to meet the needs of using semi-additive 'SAP', especially below l/s (four) microns, it is difficult to accurately complete the required dimensional accuracy, and its cost =. Moreover, under the requirements of the fine line process, the junction surface of the substrate in the substrate will become smaller and smaller. Therefore, when the fine circuit structure is formed, the spring structure is effectively adhered to the surface of the saddle layer, and it is necessary to maintain the insulation flatness. Otherwise, if it is impossible to maintain the flatness of the insulating layer, the circuit layer on the production port is prone to peeling problems and seriousness; for example, 'the base of the inner patterned circuit i; When the layered structure is formed, it is necessary to first form the inner layer formed on the substrate by the sound of the inner layer patterned circuit, after the wonderful, the, and the θ W are formed on the insulating layer. It is bound to (4) 4 the surface of the concave and convex surface, which will make the insulation of the back and the joints not; the flat condition occurs, so that it is formed when the build-up circuit layer is formed on the insulating layer of the island. The road layer will be subject to the sound layer of the insulation layer I, and the result will be attached to the insulation layer. In severe cases, the line system will be formed. In the case of a fine line structure, the smaller the joint area between the circuit layer 18102 7 1283055 and the insulating layer, the more serious it is. Generally, the process of a general semiconductor device is to first produce a wafer carrier suitable for the semiconductor device by a wafer carrier manufacturer, such as a = line;: a: 'replace the wafer carrier with a semiconductor package = And to provide external conductive connection components, etc., after the private access to the client, to complete the electronic skills required by the client, the main words of the "in the case of different processes, to the b-semiconductor 盥-盥 semiconductor package" have wafer bearing The manufacturer is a cow manufacturer, and therefore the interface is not easy to integrate. Moreover, if the client wants to involve changes and integration, it is more complicated - wide and economic benefits. In order to change the elasticity of the invention, the main disadvantages of the above-mentioned Japanese and American-made ultra-fine-line semiconductor package structure are as follows: the manufacturing process of the target component and the process of the chip packaging technology. The guest crystal carries the re-second=the interface integration problem of the present invention. The structure can form a fine circuit structure, and the invention can be packaged with the #路^ body. The invention is further characterized by the accuracy of the process. It can provide the quality of the circuit of the ultra-fine circuit semiconductor package and the structure and the insulation layer between the circuit structure and the insulation layer. The power of the person, and then maintain the other purpose of the instrument to rent - :: Chad Effectively dissipating semiconductor crystals;: Yun 2 = semiconductor package junction 0 read for electromagnetic shielding effect, to avoid external electricity: heat generated, interference with electromagnetic and noise. 8] 8] 〇 2 1283055 The purpose is to provide a super structure to avoid the problem of the layout of the conductive components of the overmolded wafer in the conventional semi-conductive process:: 'Version quality and product reliability. · + ¥ The production name of the body is set to ^ For other purposes, the ultra-fine line semiconductor sealing, and mouth structure of the present invention mainly comprises a carrier plate; the clothing is attached to the carrier plate; at least - a half/'^7 W support plate' carrier plate The upper and lower accommodating material is called the 增 ' ' 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 系 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The board and the semiconductor wafer/, the line build-up structure includes at least The ρ number is formed in the lower insulating layer of 曰, ,, 巴,, 彖g, the complex electric blind hole and the upper surface ^_ and an electrical connection of the guide /, JL Zhixiang bar edge layer surface is flat. The conductive component 1 S of the line build-up structure, and the plurality of contacts can be electrically connected to the semiconductor via the conductive via hole, and the semiconductor wafer is directly transmitted through the conductive hole and the circuit layer. Availability extends. , the eye hole people, the spring road layer and according to the external power integration Ϊ = line semiconductor sealing structure is mainly for the simultaneous industry, the process of the circuit board and the semiconductor chip package for hunting and learning the semi-guided Using the conventional semiconductor packaging process;:;:: = problem, while eliminating the structure of the spinning step 1, - and electrically connected to the crystal moon and its carrying process and cost. Same as::9:::::Steps and 妓^ Use a plurality of layers of insulating layer, in the line-adding structure used to make the layer portion first above the complex insulating layer σ, and then the opening of the circuit layer, Further, in the opening, the step shape is 18102 9 1283055, and the blind hole of the lower layer portion of the insulating layer is obtained, so that a conductive blind hole is formed in the lower layer portion of the plurality of insulating layers. Multiple insulation 2 upper layer #刀开/成线层, so that the circuit layer is effectively attached to the insulation = to maintain the process reliability of the product f, and the surface of the circuit layer is flush with the surface of the upper layer of the complex H edge layer 'To provide the smooth connection between the subsequent line-added structures, the material, the 隹, go to ^ to achieve the purpose of the fine line process. The present invention provides at least one semiconductor wafer through-heat-conducting/two-carrier board for effectively dissipating the semiconductor wafer to be: "hot-set, and by means of the carrier plate, usually of a metal material, Effectively providing the electromagnetic shielding effect of the semiconductor device, and the 曰;=: metal plate, insulating plate or circuit placed on the carrier plate:: in addition: = the overall thickness of the conductor device, to achieve a light and thin short direct m δ Γ Γ Γ Γ 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体> There are many conductive elements, such as solder balls, solder posts or conductive. The column structure is configured to electrically connect the structure of the wafer to the external device. [Embodiment] In order to make the object, the features, the effects and the recognition of the present invention, the detailed disclosure and the detailed description of the drawings can be implemented in various forms, and the following is a description; It is expressly stated that this yoke is not intended to limit the scope of the present invention. Fortunately, please refer to Sections 2 to 2, which is a schematic cross-sectional view of the manufacturing method of the package.月 Κ Κ 半导体 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 Κ The carrier plate 21 is accommodated in the opening 220 of the support plate 22. The support plate 22 can be a metal plate, an insulating plate or a circuit board, and the support plate 22 is formed with at least a through-surface opening, and the carrier plate 21 is closed to one side of the support plate opening 22 Forming a concave portion, the semiconductor wafer 23 can be placed on the carrier plate 21 by the heat conductive adhesive layer 24 and accommodated in the opening of the support plate 22 to make the circuit surface of the semiconductor wafer 23 The upper electrode pad can be exposed to the support plate. Where the '5 mystery support plate 22 is a metal plate, it can be - metal material such as copper, magnesium, Shao, recorded, non-recorded steel or the like or When the alloy is formed on the upper side, and the "manufactured plate 22" is an insulating plate, it may be a ceramic substrate, a ring-shaped resin (EpGxyresin), a polyethylene (four) (four) yimide, a cyanide performance: 〇, carbon fiber (Carbon flber) , bis-butyl succinic acid amide / trinitrogen = y (alelmlde tnazme) or mixed epoxy resin and glass fiber = shell; when the support plate 22 is a circuit board, it can be a pre-treatment Circuit board of the circuit layer. As shown in FIG. 2B, the support layer 22 and the semiconductor wafer=form the first insulating layer 251 and the second insulating layer, and the first layer 251 is filled into the gap between the wafer and the support plate opening (10). . The second layer = the insulating layer 251 and the second insulating layer 252 are made of different materials;::: photosensitive or non-photosensitive material, or - is a photosensitive material and is also a non-photosensitive material. As shown in FIG. 2C, the second insulating layer 252 is first patterned by 18102 11 1283055 to form a plurality of openings in the second insulating layer 252. A portion of the first insulating layer 251 may be exposed by forming a plurality of openings 252a in the second insulating layer 252 by exposure, development, etching, or the like. As shown in FIG. 2D, the first insulating layer is exposed by the laser opening O-er dnH or the electric (four) engraving (pia_(10) (four), etc.), and the electrode 23 of the wafer 23 is exposed to the blind hole. As shown in the figure, a conductive layer 26 is formed on the first insulating layer 251 and the second exposed surface and the electrode pad 230. The _: is mainly used as a current conduction path for conducting metal plating, which will be described later. The conductive layer 26 is formed with a gold material structure. The material of the layer 26 may be a metal or a conductive polymer material. The metal conductor structure on the upper surface of the electrode layer 252 is the second insulating layer. The upper surface of 252 is formed in the opening thereof; the guide: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The metal conductor structure is H ^ ' absolutely

Jif該第二絕緣層252開口中之金屬導體結構部〜 為線路層270，俾使該線路| 27〇得 ^刀即 而f連接至半導體晶W之電極be，V；目二171 一線路增層結構27a。 此即元成 如第扣圖所示，復可持續形成線路增層結構27a。其 18102 12 1283055 :’：於，線路增層結構27a中係使用複數層 二絕緣層251,252)，以供後續得以先在該=⑽ 、、層252中形成供設置線路層270之開口，再於 : r “， 邑緣層251之盲孔，再進行電” =，如㈣寻形成導電盲孔271，俾使該線路層27〇二 1附方U緣層251 i，以維持製程可靠度之品質/、， 令該線路層270表面與該第二絕緣層25 八声亚 齊平’以提供線路增層結構27a相互接置間之；整= 而達到細線路製程之目的。 進 一防==所Λ’於該線路增層結構…之外緣覆蓋 干Μ 亚進行圖案化製程以於該防焊層28中形点 開孔以供接置例如為錫球或導電柱之導電元件29。 口此，设睛麥閱第2Η圖所示，透過前述之製程所 本發明之超細線路半導體封裝結構主要係包#:一= :1; -具有至少一開口 220之支承板22,係接置於該承= 反21上，至少一半導體晶片23，係接置於該承載板幻 ，容置於該支承板開口 22〇中；至少一電性連接該半導體 Β23之線路增層結構27&，係形成於該支承板22及^ ‘妝日日片23上，其中，該線路增層結構27a係包含有至少 二層絕緣層251,252，形成於下層絕緣層（亦即本圖示之^ 、、’巴緣層251)中之導電盲孔271 ’以及電性連接該導電盲 孔271並與上層絕緣層（亦即本圖示之第二絕緣層252)表 面月平之線路層270 ;以及複數接置於該線路增層結構 部分外緣表面之導電元件29。其中該線路增層結構27a係 18102 1283055 導電盲孔271以電性連接半導體晶片23與線路層 路戶供半導體晶片23直接透過該導電盲孔271與線 路層270而據以向外作電性延伸。 …泉 例如人/p 載板21係採用—具有導熱性及硬度材質， 轉金屬及其合金，或為不‘ 相對凹 =結=:在該承載板_ 積與熱傳效率。；俾增加該承載板21有效散熱面 n 1板22可為—金屬板，而該金>1板之材質係可等 冋於或不同於該承載板 4貝你]寺 則可直接整人兮承葡^ 材貝，而虽彼此材質相同時， 度較厚之全尸:：：該金屬板，例如藉由提供-厚 之金屬塊：： 刻等製程形成-具有至少-凹槽 中；再者，★，、後績將至少—半導體晶片接置於該凹槽 瓷美板或右°1支承板22亦可為-絕緣板，該絕緣板可由陶 =或有機材質與纖維強化有機材質 树脂聚乙醯胺、顺雔 Λ ^ FR-4樹脂、FR 稀二馱醯亞胺/三氮阱樹脂、氣酯或 日 4树脂等，該絕緣板可藉由一庐翔Μ十古 接麼合至該承載板21上；….黏層或直 路板。 上，田然’该支承板22亦可為—電 其伟Cl用2 3圖所示，若該支承板22為刪質時， 伸出例如導電亡而另於該線路增層結構27a中延 板22兔命§寻蛤電結構30至該金屬板；抑或該支承 層結構27::Τ或該電路板嵌埋有被動元件時，該線路增 a σ延伸出例如導電盲孔等導電結構3〇以電性連 14 18102 1283055 接至该電路板’藉以提供本發 ^ 义月之構裝結構更佳之電性功 月匕^ 5亥半導體晶片23具有一電路面 遑雕曰u ^ 兒峪面和另一表面，且在該半 V脰日日片23之電路面上形成有帝 鈐曰±朱V戚有电極墊230,其係將該半導 月旦日日片23之一表面透過—導埶 η與該支承板開σ 22G所形成、之凹接置於該承載板 地私# R 成之凹槽中，藉以透過該導埶 性#者層㈣承載板21所構成的散熱途徑（Th_ally ===)直接逸散該半導體w 23㈣所產生之 果。 以‘供電磁遮蔽（Shielding)效 該線路增層結構27a係包含 絕緣層批形成於第—絕緣層251中之導 =2= 及電性連接該導電盲孔27 ， “ 之後踗羼97η甘+ ”弟―、纟巴緣層252表面齊平 路層270。其中，該線路層 + 而雷柯准拉石丄> … 270侍以稭由導電盲孔271 而电性連接至半導體晶片23之帝权也n 士 电極塾23〇，亦即’該半導 月且日日片23係可直接透過該導 ^ 以向外作電性延伸。W目孔271與線路層270而據 請參閱第4圖，係尨太a 構第-每Μ&…S月之超細線路半導體封裝結 傅乐一貝知例之剖面示意圖。 例之構裝結構係與第—實施::|明第二實施 處係在於使用於該線路增層;不大致相同，其不同 於-层 n + 智、、、"構37a中之絕緣層並非侷限 万、一層，而可使用三層絕 h们哏 卜*丄 录層351，352,353，甚或二声以 上，其中該線路增層結構37a 飞;層以 丁属 中之^r笔目孔3 71係形成於 下層二絕緣層(亦即本圖 …成於 u不之弟—及第二絕緣層Μ〗，％〕） 18102 15 1283055 二:而：線路層370係電性連接該導電盲孔 於該上層絕緣層（亦即本 夏形成 與其表面背平，盆中兮綠 f且 亡$ 371、，、中该、，泉路增層結構37a係可藉由其導 目孔371以電性連接半導曰 、兒 位於該三層絕⑽中之第;以33與線路層37°。另外， 、巴、.象層中之罘二絕緣層352可設 程中之曝光、顯影、钱 …、開口衣 層，藉以提供該線路==止銅離子遷移之阻障 性傳導品質。 構37a良好之線路平整性與電 可η=二ί過本發明之超細線路半導體封裝結構主要係 3::正合電路板之製程以及半導體晶、 半導體封裝製程中，所需！:遠=同時免除使用習知 ,„^ φ . 所而电性連接晶片與其承载結構時之 、核彳是晶繁複製程步驟與製程設備，進 本。同時，本發明所偵用夕始& ’才及成 彳❹之線路增層結構巾係使用複數層 ^緣層，以供後續得以先在該複數絕緣層之上層部 ，供設置線路層之開口，再於該開口中進一步形成 複數絕緣層下声邻分夕亡了, 、 ^ 缝思 層^刀之目孔，如此即得於後續在該複數絕 、、彖層之下層部分中形成導^>亡 刀甲升乂成"^目孔，在該複數絕緣層之上層 =形成線路層，俾使該線路層有效貼附於絕緣層，以維 之=可靠度之品質，並令該線路層表面與該複數絕緣層 上層部分表面齊平’以提供後續線路增層結構相互接置 3之平整性’進而達到細線路製程之目的。另外，本發明 =可提供至少-半導體晶片透過一導熱黏著層接置於一承 載板上，以有效逸散該半導體晶片於運作時產生之熱量， 18102 16 1283055 亚可藉由該承載板’通常為金屬材質，以有效提供該半導 體裝置電磁遮蔽效果，且該半導體晶片係收納於接置在該 承載板上之金屬板、絕緣板或電路板之開口中，俾可缩短 半導體裝置之整體厚度，以達輕薄短小目的；此外 明並於該容置有半導體晶片之支承板上直接形成有至少_： 堆豐線路結構’俾得以提供半導體晶片向外作電性延伸， 取後’可在該堆疊線路結構之外緣植設有多數之導電元 ^例如錫球、銲柱或導電柱等，以提供該整合晶片 裝結構電性連接至外部裝置。 點/Γί上所述之具體實施例，僅係用以例釋本發明之特 广力效’而非用以限定本發明之可實施範嘴， =明上揭之精神與技術範訂，任何運用本發明所揭示 内谷而完成之等效改變及修鋅，均仍 範圍所涵蓋。 、心甲Μ專利 【圖式簡單說明】 第^圖係習知之CDBGA半導體龍件之剖 弟2ADH圖係為形成本發明之超 ^； 結構之製法剖面示意圖； 峪牛V脰封裝 、，第3圖係為本發明之超細線路半導體封裝結 增層結構電性延伸至金屬板之剖面示意圖；以及、’^ 施例2_為本發明之超細線路半導體料結構第二實 施例之剖面示意圖。 外 只 【主要元件符號說明】 10 封裝結構 18102 17 1283055 11 基板 12 承載板 13 半導體晶片 14 銲線 15 封裝膠體 16 錫球 21 承載板 22 支承板 220 開口 23?33 半導體晶片 230 電極墊 24 黏著層 251,351 第一絕緣層 251a 盲孑L 252,352 第二絕緣層 252a 開口 26 導電層 27 金屬導體結構 270,370 線路層 271,371 導電盲孔 27a，37a 線路增層結構 28 防焊層 29 導電元件 30 導電結構 353 第三絕緣層 18 18102Jif the metal conductor structure portion in the opening of the second insulating layer 252 is the circuit layer 270, so that the circuit is connected to the electrode be, V of the semiconductor crystal W; Layer structure 27a. This element is formed as shown in the figure, and the line buildup structure 27a is continuously formed. Its 18102 12 1283055: ': In the line build-up structure 27a, a plurality of layers of two insulating layers 251, 252) are used for the subsequent formation of the openings for the circuit layer 270 in the layer 252, and then : r ", the blind hole of the edge layer 251, and then electric" =, as (4) to find the conductive blind hole 271, so that the circuit layer 27 〇 2 1 attached U edge layer 251 i to maintain process reliability The quality/, the surface of the circuit layer 270 and the second insulating layer 25 are accommodating to provide a line-up structure 27a to each other; the whole = to achieve the purpose of the fine line process. In the case of the line build-up structure, the outer edge of the line is covered with a dry process, and a patterning process is formed to form a hole in the solder resist layer 28 for receiving conductive wires such as solder balls or conductive posts. Element 29. According to the second embodiment of the present invention, the ultra-fine circuit semiconductor package structure of the present invention is mainly packaged by the above-mentioned process: #:一=:1; - a support plate 22 having at least one opening 220, which is connected Placed on the substrate 21, at least one semiconductor wafer 23 is attached to the carrier plate and placed in the opening 22 of the support plate; at least one circuit build-up structure 27 & electrically connected to the semiconductor device 23 Formed on the support plate 22 and the makeup day 23, wherein the line build-up structure 27a includes at least two insulating layers 251, 252 formed on the lower insulating layer (ie, the figure of the figure) a conductive via hole 271 ′ in the 'bar edge layer 251 ′′ and a circuit layer 270 electrically connected to the conductive blind via 271 and having a surface flattening with the upper insulating layer (ie, the second insulating layer 252 of the figure); A plurality of conductive elements 29 are attached to the outer peripheral surface of the portion of the line build-up structure. The line build-up structure 27a is 18102 1283055. The conductive blind hole 271 electrically connects the semiconductor wafer 23 and the circuit layer for the semiconductor wafer 23 to directly pass through the conductive blind hole 271 and the circuit layer 270 to electrically extend outward. . ... Springs For example, the person/p carrier board 21 is used—having a material with thermal conductivity and hardness, a metal and its alloy, or not “relatively concave = knot=: in the carrier plate _ product and heat transfer efficiency.俾 increasing the effective heat dissipating surface of the carrier plate 21, the plate 22 may be a metal plate, and the material of the gold > 1 plate may be equal to or different from the carrier plate 4, and the temple may be directly兮 葡 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Furthermore, the final performance will be at least - the semiconductor wafer is placed on the grooved porcelain plate or the right side 1 support plate 22 may also be an insulating plate, which may be made of ceramic or organic material and fiber reinforced organic material. Resin polyacetamide, cis 雔Λ ^ FR-4 resin, FR diimide imine / trinitrogen well resin, gas ester or day 4 resin, etc., the insulation board can be used by a 庐 Μ Μ 十 古 古Attached to the carrier plate 21; .... adhesive layer or straight plate. In the above, the support plate 22 can also be as shown in Fig. 3, and if the support plate 22 is depleted, it protrudes, for example, electrically conductive and extends in the line build-up structure 27a. 22 rabbit life § seek electrical structure 30 to the metal plate; or the support layer structure 27:: or the circuit board embedded with passive components, the line increases a σ to extend a conductive structure such as conductive blind holes 3 Electrical connection 14 18102 1283055 is connected to the circuit board 'to provide a better electrical structure of the present invention. ^ 5H semiconductor wafer 23 has a circuit surface 遑 ^ u ^ 峪 和 and On the other surface, an electrode pad 230 is formed on the circuit surface of the half-V solar dipole 23, which is a surface of the semi-conducting moon day 23埶η is formed by the support plate opening σ 22G, and is recessed in the groove formed by the carrier plate, so as to transmit the heat dissipation path formed by the conductive layer (4) carrier plate 21 (Th_ally) ===) directly dissipates the result of the semiconductor w 23 (four). The circuit build-up structure 27a includes an insulating layer formed in the first insulating layer 251, and is electrically connected to the conductive blind hole 27, "after the Shielding effect." "Di" - 纟 缘 层 layer 252 surface flush road layer 270. Wherein, the circuit layer + and the Lei Ke Zhuo Lashi 丄 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 270 The guide month and the day piece 23 can be directly electrically extended through the guide. W mesh hole 271 and circuit layer 270, and referring to FIG. 4, is a schematic cross-sectional view of the ultra-fine-line semiconductor package of the 尨太 a 第 Μ Μ amp 。 。 。 。 。 。. The structure of the structure and the first implementation:: the second implementation of the system is used in the line build-up; not roughly the same, it is different from the - layer n + wisdom,,, " insulation in the structure 37a It is not limited to 10,000, one layer, but can use three layers of 哏 哏 丄 丄 351 351 351 351 351, 352, 353, or even more than two sounds, wherein the line build-up structure 37a fly; layer is in the genus ^r pen hole 3 The 71 series is formed on the lower two insulating layers (that is, the figure is formed in the middle of the U-different - and the second insulating layer ,, %)) 18102 15 1283055 2: And: the wiring layer 370 is electrically connected to the conductive blind hole In the upper insulating layer (that is, the summer is formed to be flat with the surface thereof, the green in the basin and the death of $ 371, and the middle, the spring road layering structure 37a can be electrically connected by the guide hole 371 thereof. Connecting the semi-conductive 曰, the child is located in the third layer (10); 33 and the circuit layer 37 °. In addition, the Ba, the image layer of the second insulating layer 352 can be set in the process of exposure, development, money ..., opening The coating layer, in order to provide the barrier conduction quality of the line == copper ion migration. Structure 37a good line flatness and electricity η = two The ultra-fine circuit semiconductor package structure of the present invention is mainly required for the process of 3::positive circuit board and semiconductor crystal and semiconductor packaging process!: far = simultaneous use of conventional, „^ φ. When the wafer is connected to the load-bearing structure, the core is a crystallization process step and a process device, and at the same time, the circuit of the present invention is used in a multi-layered layer. The edge layer is provided for the subsequent opening of the layer above the plurality of insulating layers for providing the opening of the circuit layer, and further forming a plurality of insulating layers in the opening, and the sound is adjacent to the singer, and The eye hole, so that it can be formed in the lower part of the layer and the lower layer of the layer, and the hole is formed into a hole in the upper layer of the insulating layer. The circuit layer is effectively attached to the insulating layer to maintain the quality of the reliability, and the surface of the circuit layer is flush with the surface of the upper portion of the plurality of insulating layers to provide a flattening of the subsequent line build-up structures. Sexuality In addition, the present invention provides that at least a semiconductor wafer is placed on a carrier plate through a thermally conductive adhesive layer to effectively dissipate heat generated by the semiconductor wafer during operation, 18102 16 1283055 The carrier plate ′ is generally made of a metal material to effectively provide an electromagnetic shielding effect of the semiconductor device, and the semiconductor wafer is housed in an opening of a metal plate, an insulating plate or a circuit board attached to the carrier plate, thereby shortening the semiconductor device The overall thickness is for the purpose of lightness and shortness; in addition, at least the _: stacking circuit structure is formed directly on the support plate on which the semiconductor wafer is housed, so that the semiconductor wafer can be electrically extended outward, and then taken A plurality of conductive elements, such as solder balls, solder posts or conductive posts, may be implanted on the outer edge of the stacked wiring structure to provide electrical connection of the integrated wafer package to an external device. The specific embodiments described above are merely used to illustrate the invention of the invention, and are not intended to limit the scope of the invention. Equivalent changes and zinc repairs performed using the inner valley disclosed in the present invention are still covered. , the cardiamine patent [simplified description of the diagram] The first diagram of the CDBGA semiconductor dragon piece of the 2ADH diagram is the formation of the super-structure of the invention; schematic diagram of the structure of the structure; yak V脰 package, 3rd The figure is a schematic cross-sectional view of the ultra-fine line semiconductor package junction layer structure electrically extending to the metal plate of the present invention; and, ^^ Example 2_ is a schematic cross-sectional view of the second embodiment of the ultra-fine line semiconductor material structure of the present invention . External only [Main component symbol description] 10 Package structure 18102 17 1283055 11 Substrate 12 Carrier plate 13 Semiconductor wafer 14 Bond wire 15 Package colloid 16 Tin ball 21 Carrier plate 22 Support plate 220 Opening 23? 33 Semiconductor wafer 230 Electrode pad 24 Adhesive layer 251, 351 first insulating layer 251a blind 孑 L 252, 352 second insulating layer 252a opening 26 conductive layer 27 metal conductor structure 270, 370 circuit layer 271, 371 conductive blind hole 27a, 37a line build-up structure 28 solder resist layer 29 conductive element 30 conductive structure 353 third Insulation layer 18 18102

Claims (1)

1283055 申請專利範圍： 種超細線路半導體封裝結構，係包括： 一承載板； 置於該承載板 一具有至少一開口之支承板，係接 上 ▲至少-半導體晶片’係接置於該承载板上並容置於 該支承板開口中；以及 至少一形成於該支承板及半導體晶片上並電性連 晶片之線路增層結構，其中，該線路增層結 ，“至少二層呈上下疊置關係之絕緣層，複數形 士於下層絕緣層中之導電盲孔，以及—電性連接該導電 盲孔並設置於上層絕緣層開口中主 面齊平之線路層。 …亥上層絕緣層表 2·如申請專利範圍第μ之超細線路半導體難結 包括複數接置於該線路增層結構部分外 元件。 〜_包 3.如申請專利第丨歡超細線路 ^ :導;=!電性連接半導體晶片與線二： 導電盲孔與線路層以向外作電 m利/已圍第1項之超細線路半導體封裝結n 圍第丨項之超細線路半導體封，： 中，料導體晶片係藉由導熱黏著層接置於該承載板、 18102 19 別 3〇Ss 1項之超細線路半導體封装結構，其 具複數電極墊’以供電性連接至該導 7’ 範圍第1項之超細線路半導體封農結構，其 ’“緣層係充填至該晶片與支承板開σ之間隙。1283055 Patent application scope: an ultra-fine-line semiconductor package structure, comprising: a carrier plate; a support plate having at least one opening disposed on the carrier plate, and tying at least a semiconductor wafer to be attached to the carrier plate And an upper layer is disposed in the opening of the supporting plate; and at least one circuit layering structure formed on the supporting plate and the semiconductor wafer and electrically connected to the chip, wherein the line is layered, "at least two layers are stacked one on another The insulating layer of the relationship, the conductive blind hole in the lower insulating layer, and the circuit layer electrically connected to the conductive blind hole and disposed in the upper surface of the upper insulating layer opening. · For example, the ultra-fine line semiconductor hard-to-knot of the application range of the μth includes a plurality of external components placed in the layer-added structure of the line. ~_Package 3. If the patent application is the first line of the Huanhuan ultra-fine line ^: guide; =! Connecting the semiconductor wafer and the wire 2: the conductive blind hole and the circuit layer to make an external power supply / the ultra-fine circuit semiconductor package of the first item is surrounded by the ultra-fine line semiconductor package of the first item, in: The conductor chip is connected to the carrier board by a thermally conductive adhesive layer, and the plurality of electrode pads are electrically connected to the guide 7'. The ultra-fine line semiconductor sealing structure has a 'edge layer filling the gap between the wafer and the supporting plate. 如申請專利範圍第 中’該半導體晶片 電盲孔。 .°申請專利範圍第W之超細線路半導體封裝妹構，立 中申緣層係採感光性及非感光性材料搭配組合。 …申明專利範圍第W之超細線路半導體封裝結構，史 中，該線路增層結構係延伸出導電結構至該支承板。 ίο.如申請專利範圍第！項之超細線路半導體封裝結構，其 中亥些絕緣層係包含上、下二層絕緣層，其中，该下 層：緣層中形成有導電盲孔，而上層絕緣層中形綱 路層。 11. 如申請專利範圍第丨項之超細線路半導體封裝結構，其 中’該些絕緣層係包含三層絕緣層，其中，該下二声絕 緣層中形成有導電盲孔，而上層絕緣層中形成有線ς 層。 12. 如申請專利範圍第u項之超細線路半導體封裝結構， 其中’該三層絕緣層中之中間絕緣層可設置為開口製程 中：*光頒景彡、蝕刻之停止層與防止銅離子遷移之阻 陳層。 18102 20As in the patent application, the semiconductor wafer is electrically blind. .° Patent application No. W ultra-fine line semiconductor package sister structure, Lizhong Shenyuan layer is a combination of photosensitive and non-photosensitive materials. ... the ultra-fine line semiconductor package structure of the patent scope W, in the history, the line build-up structure extends the conductive structure to the support plate. Ίο. If you apply for a patent scope! The ultra-fine line semiconductor package structure, wherein the insulating layer comprises two upper and lower insulating layers, wherein the lower layer: a conductive blind hole is formed in the edge layer, and the upper insulating layer is formed in the upper insulating layer. 11. The ultrafine line semiconductor package structure of claim </ RTI> wherein the insulating layer comprises three insulating layers, wherein the lower insulating layer is formed with a conductive blind via, and the upper insulating layer is Form a wired layer. 12. The ultra-fine line semiconductor package structure of claim U, wherein the intermediate insulating layer of the three insulating layers can be set in an open process: *lighting, etching, stopping layer and preventing copper ions The migration is blocked by the layer. 18102 20
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TWI426588B (en) * 2010-10-12 2014-02-11 Advanced Semiconductor Eng Package structure and package process
US10383226B2 (en) 2017-10-13 2019-08-13 Unimicron Technology Corp. Multi-layer circuit structure and manufacturing method thereof

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TWI426585B (en) * 2008-10-02 2014-02-11 Nat Univ Tsing Hua An electronic packaging structure with enhanced design
TWI691062B (en) * 2016-09-20 2020-04-11 英屬開曼群島商鳳凰先驅股份有限公司 Substrate structure and manufacturing method thereof
TWI698971B (en) * 2017-05-18 2020-07-11 欣興電子股份有限公司 Package structure
CN108962839B (en) * 2017-05-26 2021-02-19 欣兴电子股份有限公司 Packaging structure
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426588B (en) * 2010-10-12 2014-02-11 Advanced Semiconductor Eng Package structure and package process
US10383226B2 (en) 2017-10-13 2019-08-13 Unimicron Technology Corp. Multi-layer circuit structure and manufacturing method thereof

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